© 2003 xilinx, inc. all rights reserved synthesis techniques fpga design flow workshop
TRANSCRIPT
![Page 1: © 2003 Xilinx, Inc. All Rights Reserved Synthesis Techniques FPGA Design Flow Workshop](https://reader030.vdocuments.net/reader030/viewer/2022032607/56649ed95503460f94be7947/html5/thumbnails/1.jpg)
© 2003 Xilinx, Inc. All Rights Reserved
Synthesis TechniquesFPGA Design Flow Workshop
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Synthesis Techniques - 6 - 2 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Objectives
• Select a proper coding style to create efficient FPGA designs• Specify Xilinx resources that need to be instantiated for various FPGA
synthesis tools• Describe an approach to using your synthesis tool to obtain higher
performance
After completing this module, you will be able to:
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Synthesis Techniques - 6 - 3 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Outline
• Coding Tips• Instantiating Resources• Synthesis Options• Summary• Appendix:
– Inferring Logic and Flip-Flop Resources– Inferring Memory– Inferring I/Os and Global Resources– Inference versus Instantiation by Synthesis Vendor
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Synthesis Techniques - 6 - 4 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Instantiation versus Inference
• Instantiate a component when you must dictate exactly which resource is needed
– Synthesis tool is unable to infer the resource– Synthesis tool fails to infer the resource
• Xilinx recommends inference whenever possible– Inference makes your code more portable
• Xilinx recommends using the CORE Generator™ system to create ALUs, fast multipliers, FIR filters, etc. for instantiation
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Synthesis Techniques - 6 - 5 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Coding Flip-Flops
• Control signal precedence: Clear, Preset, Clock Enable
VHDL
FF_AR_CE: process(CLK)beginif (CLK’event and CLK = ‘1’) then if (RST = ‘1’) then Q <= ‘0’; elsif (SET = ‘1’) then Q <= ‘1’; elsif (CE = ‘1’) then Q <= D_IN; end if;end if;end process
Verilog
always @(posedge CLK) if (RST) Q = 1’b0; else if (SET) Q = 1’b1; else if (CE) Q = D_IN;
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Synthesis Techniques - 6 - 6 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
State Machine Design
• Put the next-state logic in one CASE statement
– The state register may also be included here or in a separate process block or always block
• Put the state machine outputs in a separate process or always block
– Easier for synthesis tools to optimize logic this way
S1
S5 S4
S3
S2
StateMachineModule
Inputs to FSM
Next-state logic
State register
State machine outputs
HDL Code
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Synthesis Techniques - 6 - 7 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
The Perfect State Machine
• The perfect state machine has– Inputs: input signals, state jumps– Outputs: output states, and control/enable signals to the rest of the design– NO arithmetic logic, datapaths, or combinatorial functions inside the state
machine
StateJumps Only!Input Signals
Next State
Current State Feedback to Drive State JumpsS
tate R
egiste
r
Output State and Enables
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Synthesis Techniques - 6 - 8 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
State Machine Encoding
• Use enumerated types to define state vectors (VHDL)– Most synthesis tools have commands to extract and re-encode state
machines described in this way• Use one-hot encoding for high-performance state machines
– Uses more registers, but simplifies next-state logic– Experiment to discover how your synthesis tool chooses the default
encoding scheme• Register state machine outputs for higher performance
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Synthesis Techniques - 6 - 9 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Outline
• Coding Tips• Instantiating Resources• Synthesis Options• Summary• Appendix:
– Inferring Logic and Flip-Flop Resources– Inferring Memory– Inferring I/Os and Global Resources– Inference versus Instantiation by Synthesis
Vendor
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Synthesis Techniques - 6 - 10 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Instantiation Tips
• Use instantiation only when it is necessary to access device features or increase performance or decrease area
– Exceptions are noted at the end of this section• Limit the location of instantiated components to a few source files, to
make it easier to locate these components when porting the code
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Synthesis Techniques - 6 - 11 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
FPGA Resources
• Can be inferred by all synthesis tools:
– Shift register LUT (SRL16 / SRLC16)
– F5, F6, F7, and F8 MUX– Carry logic– MULT_AND– MULT18x18 / MULT18x18S– Memories (ROM)– Global clock buffers (BUFG)– SelectIO (single-ended)– I/O registers (single data rate)– Input DDR registers
• Can be inferred by some synthesis tools:
– Memories (RAM)– Global clock buffers (BUFGCE,
BUFGMUX, BUFGDLL**)
• Cannot be inferred by any synthesis tools:
– SelectIO (differential)– Output DDR registers– DCM
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Synthesis Techniques - 6 - 12 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Suggested Instantiation
• Xilinx recommends that you instantiate the following elements:– Memory resources
• Block RAMs specifically (use the CORE Generator™ system to build large memories)
– SelectIO resources– Clock management resources
• DCM (use the Architecture Wizard)• IBUFG, BUFG, BUFGMUX, BUFGCE
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Synthesis Techniques - 6 - 13 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Suggested Instantiation
• Why do we suggest this?– Easier to change (port)
to other and newer technologies
– Fewer synthesis constraints and attributes to pass on
• Keeping most of the attributes and constraints in the Xilinx UCF file keeps it simple—one file contains critical information
• Create a separate hierarchical block for instantiating these resources– Above the top-level block, create a Xilinx “wrapper” with Xilinx-specific
instantiations
Top-Level Block
Top-Level Block
BUFGDCMIBUFG
Xilinx “wrapper” top_xlnx
IBUF_SSTL2_I
OBUF_GTL
OBUF_GTL
OBUF_GTL
STARTUP
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Synthesis Techniques - 6 - 14 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Outline
• Coding Tips• Instantiating Resources• Synthesis Options• Summary• Appendix:
– Inferring Logic and Flip-Flop Resources– Inferring Memory– Inferring I/Os and Global Resources– Inference versus Instantiation by Synthesis
Vendor
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Synthesis Techniques - 6 - 15 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Synthesis Options
• There are many synthesis options that can help you obtain your performance and area objectives:
– Timing Driven Synthesis– Timing Constraint Editor– FSM Extraction– Retiming– Register Duplication– Hierarchy Management– Schematic Viewer– Error Navigation– Cross Probing– Physical Optimization
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Synthesis Techniques - 6 - 16 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Timing Driven Synthesis
• Timing driven synthesis uses performance objectives to drive the optimization of the design
– Based on your performance objectives, the tools will try several algorithms to attempt to meet performance while keeping the amount of resources in mind
– Performance objectives are provided to the synthesis tool via timing constraints
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Synthesis Techniques - 6 - 17 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
FSM Extraction
• Finite State Machine (FSM) extraction optimizes your state machine by re-encoding and optimizing your design based on the number of states and inputs
– By default, the tools will use FSM extraction
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Synthesis Techniques - 6 - 18 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Retiming
• Retiming: The synthesis tool automatically tries to move register stages to balance combinatorial delay on each side of the registers
D Q D Q D Q
Before Retiming
After Retiming
D Q D Q D Q
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Synthesis Techniques - 6 - 19 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Register Duplication
• Register duplication is used to reduce fanout on registers (to improve delays)
• Register duplication of the output 3-state register is used so that the IOB 3-state register can be moved inside the IOB to reduce clk-to-output delays
• Xilinx recommends manual register duplication– Most synthesis vendors create signals <signal_name>_rep0, _rep1, etc.
• Implementation tools pack these signals into the same slice• Not necessarily wrong, but it may prohibit a register from being moved closer to its
destination– When manually duplicating registers, do NOT use a number at the end
• Example: <signal_name>_0dup, <signal_name>_1dup
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Synthesis Techniques - 6 - 20 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Hierarchy Management
• The basic settings are:– Flatten the design: Allows total combinatorial optimization across all
boundaries– Maintain hierarchy: Preserves hierarchy without allowing optimization of
combinatorial logic across boundaries• If you have followed the synchronous design guidelines, use the setting
-maintain hierarchy• If you have not followed the synchronous design guidelines, use the
setting - flatten the design
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Synthesis Techniques - 6 - 21 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Hierarchy Preservation Benefits
• Easily locate problems in the code based on the hierarchical instance names contained within static timing analysis reports
• Enables floorplanning and incremental design flow• The primary issue is optimization of combinatorial logic across
hierarchical boundaries– The easiest way to eliminate this problem is to register the outputs of leaf-
level blocks
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Synthesis Techniques - 6 - 22 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Schematic Viewer
• Allows you to view synthesis results graphically– Check the number of logic levels between flip-flops– Quickly locate net and instance names
• Works best when hierarchy has been preserved during synthesis
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Synthesis Techniques - 6 - 23 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Error Navigationand Cross Probing
• Error Navigation– Allows you to click on errors in Xilinx reports and cross-navigate to the
problem area by using the synthesis tool• You must set some environment variables for this to work
– For more information, see application note XAPP406
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Synthesis Techniques - 6 - 24 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Increasing Productivity
• Use synchronous design techniques• Preserve hierarchy during synthesis
– Aids in debugging and cross-referencing to report files• Use timing-driven synthesis if your tool supports it
– Check the synthesis report for performance estimates• After implementation, look at timing reports and identify critical paths
– Double-check the HDL coding style for these paths– Try some of the synthesis options discussed earlier
• For paths that continually fail to meet timing, add path-specific constraints during synthesis
– Add corresponding path-specific constraints for implementation
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Synthesis Techniques - 6 - 25 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Outline
• Coding Tips• Instantiating Resources• Synthesis Options• Summary• Appendix:
– Inferring Logic and Flip-Flop Resources– Inferring Memory– Inferring I/Os and Global Resources– Inference vs. Instantiation by Synthesis Vendor
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Synthesis Techniques - 6 - 27 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Review Questions
• Which encoding scheme is preferred for high-performance state machines?
• Which Xilinx resources, generally, must be instantiated?
• List a few of the options that the synthesis tools provide to help you to increase performance
• What is the synthesis approach presented here for obtaining higher performance?
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Synthesis Techniques - 6 - 28 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Answers
• Which encoding scheme is preferred for high-performance state machines?– One-hot
• Which Xilinx resources generally must be instantiated?– Double-data-rate output registers– Differential I/O– BUFGMUX– BUFGCE– DCM– Complex block RAMs
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Synthesis Techniques - 6 - 29 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Answers
• List a few of the options that the synthesis tools provide to help you to increase performance
– Timing driven synthesis– FSM extraction– Retiming– Register duplication– Physical optimization
• What is the synthesis approach presented here for obtaining higher performance?
– Follow synchronous design techniques– Preserve hierarchy during synthesis– Use timing-driven synthesis
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Synthesis Techniques - 6 - 30 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Summary
• Your HDL coding style can affect synthesis results• Infer functions whenever possible • Use one-hot encoding to improve design performance• When coding a state machine, separate the next-state logic from the
state machine output equations• Most resources are inferable, either directly or with an attribute• Take advantage of the synthesis options provided to help you meet your
timing objectives• Use synchronous design techniques and timing-driven synthesis to
achieve higher performance (more on this later)
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Synthesis Techniques - 6 - 31 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Where Can I Learn More?
• Synthesis & Simulation Design Guide: – http://support.xilinx.com > Software Manuals
• User Guides: – http://support.xilinx.com > Documentation
• Technical Tips: http://support.xilinx.com > Tech Tips– Click Xilinx Synthesis Technology, Synopsys FPGA and Design Compiler,
or Synplicity• Synthesis documentation or online help