λογική σχεδίαση
DESCRIPTION
σημειώσειςTRANSCRIPT
Εργαςτήριο Μικροεπεξεργαςτών και Υλικού
MHL
Ευριπίδης Σωτηριάδης
26/2/2015
Εισαγωγή στην τεχνολογία και στην Μεθοδολογία Σχεδίασης
Blo
ck R
AM
s
Blo
ck R
AM
s
Configurable
Logic
Blocks
I/O
Blocks
Xilinx FPGA
Block
RAMs
16-bit SR
flip-flop
clock
mux
y
qe
a
b
c
d
16x1 RAM
4-input
LUT
clock enable
set/reset
Simplified view of a Xilinx Logic Cell
Design process (1)
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be able
to perform an encryption algorithm by itself,
executing 32 rounds…..
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;
Specification
VHDL description (Your VHDL Source Files)
Functional simulation
Post-synthesis simulationSynthesis
Design process (2)
Implementation
(Mapping, Placing & Routing)
Configuration
Timing simulation
On chip testing
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
beginA1<=A when (NEG_A='0') else
not A;B1<=B when (NEG_B='0') else
not B;Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;MUX_1<=A1 or B1;MUX_2<=A1 xor B1;MUX_3<=A1 xnor B1;
with (L1 & L0) selectY1<=MUX_0 when "00",
MUX_1 when "01",MUX_2 when "10",MUX_3 when others;
end MLU_DATAFLOW;
VHDL description Circuit netlist
Logic Synthesis
Mapping
LUT2
LUT3
LUT4
LUT5
LUT1FF1
FF2
LUT0
Placing
CLB SLICES
FPGA
Routing
Programmable Connections
FPGA
Εισαγωγή στην VHDL
Εργαςτήριο Μικροεπεξεργαςτών και Υλικού
MHL
Ευριπίδης Σωτηριάδης
26/2/2015
VHDL
VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
VHDL for Specification
VHDL for Simulation
VHDL for Synthesis
Entity Declaration
Entity Declaration describes the interface of the component,
i.e. input and output ports.
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC
);
END nand_gate;
Reserved words
Entity namePort names Port type
Semicolon
No Semicolon
Port modes (data flow directions)
Entity declaration – simplified syntax
ENTITY entity_name ISPORT (
port_name : signal_mode signal_type;port_name : signal_mode signal_type;………….port_name : signal_mode signal_type);
END entity_name;
Architecture
Describes an implementation of a design entity.
Architecture example:
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
Architecture – simplified syntax
ARCHITECTURE architecture_name OF entity_name IS[ declarations ]
BEGINcode
END architecture_name;
Entity Declaration & Architecture
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
nand_gate.vhd
Library declarations
Use all definitions from the packagestd_logic_1164LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
Library declaration
Library declarations - syntax
LIBRARY library_name;USE library_name.package_name.package_parts;
STD_LOGIC type demystified
Value Meaning
‘X’ Forcing (Strong driven) Unknown
‘0’ Forcing (Strong driven) 0
‘1’ Forcing (Strong driven) 1
‘Z’ High Impedance
‘W’ Weak (Weakly driven) Unknown
‘L’Weak (Weakly driven) 0.
Models a pull down.
‘H’Weak (Weakly driven) 1.
Models a pull up.
‘-’ Don't Care
Standard Logic Vectors
SIGNAL a: STD_LOGIC;SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0);
……….a <= ‘1’;b <= ”0000”; -- Binary base assumed by defaultc <= B”0000”; -- Binary base explicitly specifiedd <= ”0110_0111”; -- You can use ‘_’ to increase readabilitye <= X”AF67”; -- Hexadecimal basef <= O”723”; -- Octal base
Structural VHDL
Structural Architecture (xor3 gate)
ARCHITECTURE structural OF xor3 IS
SIGNAL U1_OUT: STD_LOGIC;
COMPONENT xor2 IS
PORT(
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
U1: xor2 PORT MAP (I1 => A,
I2 => B,
Y => U1_OUT);
U2: xor2 PORT MAP (I1 => U1_OUT,
I2 => C,
Y => Result);
END structural;
I1
I2Y
XOR2
A
BC
RESULT
U1_OUT
XOR3
A
B
C
ResultXOR3
Component and Instantiation (1)
Named association connectivity (recommended)
COMPONENT xor2 ISPORT(
I1 : IN STD_LOGIC;I2 : IN STD_LOGIC;Y : OUT STD_LOGIC);
END COMPONENT;
U1: xor2 PORT MAP (I1 => A,I2 => B,Y => U1_OUT);
For Generate Statement
ECE 545 – Introduction
to VHDL
For - Generate
label: FOR identifier IN range GENERATE
BEGIN
{Concurrent Statements} eg Port Map
END GENERATE;
For Generate
Statement
ARCHITECTURE structural OF or6 IS
SIGNAL temp: STD_LOGIC_VECTOR (0 to 3);
COMPONENT or5 ISPORT(
I1 : IN STD_LOGIC;I2 : IN STD_LOGIC;Y : OUT STD_LOGIC
);END COMPONENT;
BEGINU0: or2 PORT MAP ( I1 => A(0),
I2 => A(1),Y => temp(0) );
For i in 0 to 3 generate U1: or2 PORT MAP ( I1 => A(i+2),
I2 => temp(i),Y => temp(i+1) );
end generate;
U0: or2 PORT MAP ( I1 => A(6),I2 => temp(4),
Y => result );END structural;
Conditional concurrent signal assignment
ECE 545 – Introduction
to VHDL
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;
When - Else
.…Value N
Value N-1
Condition N-1
Condition 2
Condition 1
Value 2
Value 1
Target Signal
…01
01
01
When - Elselibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux_4X1 is
Port ( sel : in STD_LOGIC_VECTOR (1 downto 0);
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
y : out STD_LOGIC);
end test;
architecture Behavioral of Mux_4X1 is
Begin
Y <= A when SEL = "00" else
B when SEL = "01" else
C when SEL = "10" else
D;
end Behavioral;
When - Elselibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux_4X1 is
Port ( sel : in STD_LOGIC_VECTOR (1 downto 0);
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
y : out STD_LOGIC);
end test;
architecture Behavioral of Mux_4X1 is
Begin
Y <= A when SEL = "00" else
B when SEL = "01" else
C when SEL = "10" else
D;
end Behavioral;
When - Elselibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux_4X1 is
Port ( sel : in STD_LOGIC_VECTOR (1 downto 0);
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
y : out STD_LOGIC);
end test;
architecture Behavioral of Mux_4X1 is
Begin
Y <= A when SEL = "00" else
B when SEL = "01" else
C when SEL = "10" else
D;
end Behavioral;
VHDL Example – Half adderlibrary ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port (x, y : in std_logic;
s, c : out std_logic);
end half_adder;
architecture dataflow_3 of half_adder is
begin
s <= x xor y;
c <= x and y;
end dataflow_3;
VHDL Example – Full adderlibrary ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port (x, y, z : in std_logic;
s, c : out std_logic);
end full_adder;
architecture struc_dataflow_3 of full_adder is
component half_adder
port (x, y : in std_logic;
s, c : out std_logic);
end component;
signal hs, hc, tc: std_logic;
VHDL Example – Full adderbegin
HA1: half_adder
port map ( x => x,
y => y,
s => hs,
c => hc);
HA2: half_adder
port map ( x => hs,
y => z,
s => s,
c => tc);
c <= tc or hc;
end struc_dataflow_3;
Sites
www.xilinx.com
www.digilentinc.com