מודלים של חיבורי ביניים

מודלים חשמליים של חיבורי •VLSIביניים עבור מעגלי

פרופ’ יוסי שחם

המחלקה לאלקטרוניקה פיזיקלית, אוניברסיטת ת”א.

Device scaling laws

Quantity Scale factorDimensions (W,L) SArea (WxL) S2

Gate oxide thickness (dox) SSupply voltage (VDD) SDrain current (IDS) SGate capacitance [Cg~

ox (WL/ dox)] STransistor on -resistance (Rtr~VDD/I IDS) 1Intrinsic gate delay (~ Rtr Cg) SClock frequency (f) fPower dissipation per gate (P=(f/2) Cg VDD

2 f S3

Power dissipation density (P/A) fS

Interconnect scaling lawsQuantity Scale factor

Dimensions (Wint,Hint,Hsp,dox) SLocal interconnects resistivity (loc) r loc

Metal resistivity (int) rILD dielectric constant (ild) k

Resistance per unit length (Rint=int/WintHint) r/S2

Capacitance per unit length (Cint=ildWint/dILD) k

RC delay per unit length (Rint Cint) rk/S2

Local interconnect length (lloc) SLocal interconnect RC delay (Rloc Cint lloc

2) k rloc

Local int. dissipation per wire (~f lloc Cint Vdd2) k f S3

Global interconnect length (lint) DGlobal interconnect RC delay (Rint Cint lint

2) krD2/S2

Global int. dissipation per wire (~f lint Cint Vdd2) f D kS2

Example: Al and oxide technologyTypical scaling factor over 4 years are:

• S=0.6, f=2, D=1.3, Since the metal and the dielectric materials are the same: • rloc=2/3, r=1, k=1.

•The intrinsic gate delay drops by a factor of 0.6The intrinsic gate delay drops by a factor of 0.6

•The local interconnect delay drops by 2/3The local interconnect delay drops by 2/3

•The global interconnect delay increases by krDThe global interconnect delay increases by krD22/S/S22=4.69=4.69

Example: Switching to Cu and low-k technologyExample: Switching to Cu and low-k technology

Typical scaling factor over 4 years are:• S=0.6, f=2, D=1.3, The metal and the dielectric materials have been changed,The local interconnect technology has not changed: • rloc=2/3, r~1/2, k~1/2.

•The intrinsic gate delay drops by a factor of 0.6The intrinsic gate delay drops by a factor of 0.6

•The local interconnect delay drops by 1/3The local interconnect delay drops by 1/3

•The global interconnect delay increases by krDThe global interconnect delay increases by krD22/S/S22=1.17=1.17

The signal propagation effectThe signal propagation effect

Quantity Scale factorTransmission line time of flight D/k

•The signal can not propagate faster than the speed of the electromagnetic wave: Vc

• The speed of the electromagnetic wave: Vc is proportional to 1/(LC)

The inductance L is constant while the capacitance is proportional to k. Therefore:

• Clock frequency increases

• The global interconnect delay becomes dominant

• Coupling capacitance becomes important

• Inductance becomes an issue

• Clock skew variations limits the clock frequency

Effect of scaling on TimingEffect of scaling on Timing

Gate and Interconnect delaysGate and Interconnect delays

1. Cross talk - signal propagation to neighboring wires

2. Simultaneous switching noise on the power line

3. Charge sharing effects - affects mostly dynamic logic

4. Leakage current - affects DRAM and switch capacitor filters.

Effect of scaling on noiseEffect of scaling on noise

1. Higher frequency - higher power dissipation (P)

2. Lowering VDD is a solution - limited by noise margins.

3. Higher capacitance increases P

4. Lowering threshold improves margins but increases the leakage current

5. Higher CMOS transition current and dissipation

Effect of scaling on the powerEffect of scaling on the power

1. Higher power per unit area higher working temperature

2. Higher current density higher electromigration

3. Higher interconnect stress levels stress voiding

Effect of scaling on the reliabilityEffect of scaling on the reliability

Interconnect modelsInterconnect models• Resistors:

R= L/A

At higher frequency the skin effect reduces the interconnect cross section. The skin depth, , is defined by the penetration distance at which the current density drops by 1/e:

πfμρ

δ Where f is the frequency, is the resistivity and is the magnetic permeability

Interconnect modelsInterconnect models• Capacitors:

C= A/d

• Inductors:

Inductors are more difficult to calculate. Some models will be described I the next lecture.