. . 2011 1This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved.. - . 2

(memory addressing). .

CISC RISC Superscalar VLIW Vector

/ & 2This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. .... - . 3 scalar: H

/ & . - . 4 (tightly coupled) - sec. (loosely coupled) - sec. (Non-Uniform Memory Access NUMA) = . . (UMA) = (Symmetric Multiprocessor SMP). .

/ & . - . 5 (Instruction Set) ( )

.

:Pipelining : / & 5This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. Pipeline (branch prediction). = if-then-else. conditional branches. (Data flow analysis) (Speculative execution) Superscalar (Very long Instruction Word VLIW)6. - . / & 6This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved.Pipeline 123456789 1IFIDEXMEMWB 2IFIDEXMEMWB 3IFIDEXMEMWB 4IFIDEXMEMWB 5IFIDEXMEMWB : IF = (Instruction Fetch) ID = / (Instruction decode / register fetch) EX = (Execution) MEM = / (Memory access) WB = / (Write back)7. - . / & 7This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. : DLX. - . 8

/ & 8This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. ( Branch prediction) 123456789 1IFID EXE MEMWBCONDITIONALBRANCH NIFIDEX MEM WB 3 IFIDEX MEM WB. . . . . . . . . NIFIDEX MEM WB +1 = false, jump. 3 true , 3 = true, jump 9. - . / & (Branch prediction) 123456789 1IFID EXE MEMWBCONDITIONALBRANCH NIFIDEX MEM WB 3 . . . . . . . . . NIFIDEX MEM WB +1 3 . 2 . = true N10. - . / & (Branch prediction) (if-then-else) . - (no branch prediction) , ( IF) . branch prediction . branch predictor branch. if true false. . -1 1 11. - . / & . - . 12 (registers, stacks)

(memory addressing) T / & 12This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. ()(register-memory)(register-register)PUSH ALOAD ALOAD R1, ALOAD R1, APUSH BADD BADD R1, BLOAD R2, BADDSTORE CSTORE C, R1ADD R3, R2, R1POP CSTORE C, R313. - . / & 13This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. / & . - . 14

14This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. / & . - . 15

15This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. register-memory / & . - . 16

16This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. Load-Store / & . - . 17

17This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. ;. - . 18

/ & 18This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. / Pipeline03Load-store ( Load, store)12Register-memory / 2 32 3Memory-memory /19. - . / & 19This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. 03SPARC, MIPS, PowerPC, DEC-Alpha12Intel 80x86, Motorola 6800022VAX33VAX20. - . / & 20This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. (memory addressing)Register Add R4, R3R4 R4 + R3H ImmediatehAdd R4, #90R4 R4 + 90H Displacement Add R4, 10(R1)R4 R4 + M[10+R1]H 10(R1)Register indirecth Add R4, (R1)R4 R4 + M[R1]H R1 Indexed Add R4, (R1+ R2)R4 R4+ [R1+R2]H R1 R2 21. - . / & 21This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. (memory addressing)

DirectAdd R1, (1001)R1R1 + M[1001] Memory indirect Add R1, @(R3)R1R1+ M[M[R3]] R3 Auto- increment -Add R1, (R2)+R1 R1 + M[R2]R2 R2 + d . R2: d: Auto- decrement -Add R1, -(R2)R2 R2 d R1 R1 + M[R2] ScaledAdd R1, 100(R2)[R3]R1 R1 + M[100*R2 + R3*d] 2D . R2: , R3: , 100: 22. - . / & 22This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. TeX( )Spice( )Gcc( C)Memory indirect1%6%1%Scaled0%16%6%Register indirect24%3%11%Immediate43%17%39%Displacement32%55%40%23. - . / & 23This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. / add, subtract, and, or, load, store, move, branch, jump, return, call, trap , , string move, string compare, string search, pixel operations24. - . / & 24This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. 80x86 load22%conditional branch20%compare16%store12%add8%and6%sub5%move register-register4%call1%return1%96%25. - . / & 25This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. (jumps)5% (conditional jumps)85% (procedure calls)5% (procedure returns)5% bit (condition code). (condition register). (compare and branch). 26. - . / & 26This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. CISC RISC Superscalar VLIW Vector27. - . / & 27This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved.CISC vs RISC CISC RISC (.. 400 ). 16 64 bits. (.. 150 ). . 12 25.3 5. cache8-24 . cache cache. (32-256). cache . ( 1 20).1 / < 1.5 / . ROM. /. .28. - . / & 28This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. superscalar pipeline 1 . . , 3 superscalar 3 IF, 3 ID, 3 EX, 3 MEM 3 WB.

superscalar :

29. - . / & 29This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved.Superscalar Pipeline / & . - . 30 1: ; 2: superscalar scalar; 1IFIDEXMEMWB2IFIDEXMEMWB3IFIDEXMEMWB4IFIDEXMEMWB5IFIDEXMEMWB6IFIDEXMEMWB7IFIDEXMEMWB8IFIDEXMEMWB9IFIDEXMEMWB10IFIDEXMEMWBSuperscalar pipeline (2) / & . - . 31 Front-End pipeline : IF, ID Back-End pipeline : EX, MEM, WB

: (in-order execution) (out-of-order execution) superscalar (in-order execution) / & . - . 32 front-end (IF-ID) . back-end (EX-MEM-WB) pipeline . in-order execution / & . - . 33 2- superscalar . :1: R1 R2 + R3# 2: R4 R1 R5# 3: R7 R8 R9 # 4: F0 F2 + F4# 1 pipeline. 2 pipeline R1 1. WB 1. 3 2 pipeline 4 3 H 2 R1 1 superscalar (out-of-order execution) / & . - . 34 front-end (IF-ID) . back-end (EX-MEM-WB) .

out-of-order execution / & . - . 35 2- superscalar . :1: R1 R2 + R3# 2: R4 R1 R5# 3: R7 R8 R9 # 4: F0 F2 + F4# 1 pipeline 1. 3 pipeline 1. E1. 4 pipeline 2 2 pipeline (. 4) 1 R1. 2 3.H 2 R1 1 E1: add r2 = r4,r5E2: store [addr1] = r2E3: fmul f5 = f2,f7E4: fmul f2 = f2,f8E5: add r4 = r12,r17E6: add r5 = r12,r20E7: add r7 = r4,r5E8: store [addr2] = r7fmul f5 = f2,f7 add r2 = r4,r5 add r5 = r12,r20 fmul f2 = f2,f8 add r4 = r12,r17store [addr1] = r2 add r7 = r4,r5 store [addr2] = r7 1 2 3r2, r4, r5, r6, r12, r17, r20 Integer registersf2, f5, f7, f8Floating point registers36. - . / & 36This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved.Superscalar: / & . - . 37100% pipelines n (Instruction Level Parallelism ILP). . : pipelines n6n (ALU FPU) n2 . . pipeline () pipelines . : . pipeline. Pentium D 31 () Intel Core 14 .

VLIW38. - . / & 38This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. VLIWLong Instruction Word39. - . / & FPU ALU-1 ALU-2 Load / StoreALU 2ALU 1FPU39This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved.VLIW vs SuperscalarSuperscalarVLIW

( ) 40. - . / & 40This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved.Iter. 1Iter. 2 loadloadaddstoreloadloadaddstore VectorloadloadaddstoreloadloadaddstoreIter. 1Iter. 2 for (i=0; i < N; i++) C[i] = A[i] + B[i]; 41. - . / & : scalar / & . - . 42 :for (i=0; i