embedded digital signal processing (dsp) systems specification with floating-point data types ...

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Embedded Digital Signal Processing (DSP) systems Specification with floating-point data types Implementation in fixed-point architectures Precision evaluation based on simulation [Coster98], [Keding01], [Kim98] Long simulation time [Coster98] Optimization process requires multiple simulations [Sung95] Definition of a new methodology based on an analytical approach 1 0 2 1 0 2 2 1 0 1 0 2 e ej g gi e ej g gi N j b N i b N j b N i b q b E ) ( n b j e ) ( n x j ) ( n b j h ) ( 1 n b g ) ( 1 n b g ) ( n b gi ) ( n b gi 1 g h i g h j h j h j h ) ( n b y ) ( n y Signal Noise sources (generated during a cast operation) Output noise Output signal Input noises Error due to coefficient quantization ) ( n b Ng g ) ( n b Ng g Ng g h ) ( 0 n b e ) ( 0 n x ) ( 0 n b e ) ( 0 n b h 0 h 0 h 0 h + ) ( n b j e System Inputs A METHODOLOGY FOR EVALUATING THE PRECISION OF FIXED- POINT SYSTEMS Daniel MENARD 1 , Olivier SENTIEYS 1,2 1 LASTI - University of Rennes I F-22300 Lannion, France [email protected] 2 COSI Project - IRISA/INRIA F-35042 Rennes cedex, France [email protected] . Linear Time-Invariant System Model 1 0 1 0 1 0 ) ( * ) ( ) ( ' * ) ( ) ( ' * ) ( ) ( e e g N j j j N j ej j N i gi gi y n x n h n b n h n b n h n b h q b b h q y b E b E b E 2 2 2 2 SQNR G s DFG Generation SFG Generation SUIF SQNR Determination G sn G H Back End Source C algorithm Experimentation, Results and Perspectives SQNR Computation Methodology Output quantization noise d e H e b E j j j x x h j j j 2 2 . 2 1 d e H e H e b b E j k j j j x x h h k j k j . . . 2 1 1 0 1 0 1 0 2 2 , e e k j e j N j N k h h N j h h b b E b E b E Noise due to coefficient quantization ) ( n x j ) ( n b j h (n) h j d e H e H j k b b j k b b k k k k 2 2 2 0 2 ) ( n b k i j g e b b or i j g e b b or ) ( n b k (n) h k i g j h h or Quantization noise ) ( ) ( ˆ ) ( n y n y n b y #define pi 3.1416 #define pi 3.1416 main() { float x,h,z for(i=1;i<n;i++) { *z= *y++ + *h++ } for(i=1;i<n;i++) { *z= *y++ + *h++ } VIRGULE FLOTTANTE.C Fixed-point coding Precision evaluation #define pi 3.1416 #define pi 3.1416 main() { float x,h,z for(i=1;i<n;i++) { *z= *y++ + *h++ } for(i=1;i<n;i++) { *z= *y++ + *h++ } VIRGULE FLOTTANTE.C Floating-point description Fixed-point specification Optimization Introduction Propagation noise models: Addition: z = u + v Multiplication: z = u v Quantization noise model: b gi (n): additive random variable Stationary and uniformly distributed white noise Uncorrelated with y(n) First and second-order moments: Noise models ) ( ˆ n y + ) ( n y ) ( n b i g ) ( ˆ n y Q ) ( n y k b g k b g q b E q b E gi gi i 2 2 2 2 2 1 12 2 1 2 (Noise (Signa N N N S S S v u z v u z N N S N S N N S S S v u u v v u z v u z Front End System noise model determination H(z) Determination SFG to DAG transformation Detection of cycles in the SFG Enumeration of the cycles Dismantling of the cycles DAG linear function computation Partial T.F. determination Global T.F. determination Noise modelization Signal Flow Graph + fixed-point specifications Transfer Function (T.F.) determination Noise source detection and insertion in the SFG Replacement of operators by their propagation noise model Test of the tool on classical DSP algorithms: FFT, FIR and IIR filters Precision of the estimation: Measurement of the relative error between our estimation and the one obtained by simulation IIR 2 < 8.2 % FIR 16 < 1.5 % FFT 16 < 2.3 % Execution time of the tool: Perspectives: Hardware synthesis: minimization of the chip area under SQNR constraint: Most of the time is consumed by the cycle enumeration stage Applications T 2 Execution tim e (s) IIR 2 0.08 IIR 4 0.45 IIR 4 (cascaded) 0.65 FIR 16 0.01 FIR 256 0.86 Abstract : The minimization of cost, power consumption and time to market of DSP applications requires the development of methodologies for the automatic implementation of floating-point algorithms in fixed-point architectures. In this paper, a new methodology for evaluating the quality of an implementation through the automatic determination of the Signal to Quantization Noise Ratio (SQNR) is under consideration. The modelization of the system at the quantization noise level and the expression of the output noise power have been detailed for linear systems. Then, the different phases of the methodology are explained and the ability of our approach for computing the SQNR efficiently is shown. + ) ( n b q ) ( n b h j j k k b e H e H SQNR ) SQNR(b b S k max min as such ) ( Min

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Page 1: Embedded Digital Signal Processing (DSP) systems  Specification with floating-point data types  Implementation in fixed-point architectures  Precision

Embedded Digital Signal Processing (DSP) systems Specification with floating-point data types Implementation in fixed-point architectures

Precision evaluation based on simulation [Coster98], [Keding01], [Kim98] Long simulation time [Coster98] Optimization process requires multiple simulations [Sung95]

Definition of a new methodology based on an analytical approach

Embedded Digital Signal Processing (DSP) systems Specification with floating-point data types Implementation in fixed-point architectures

Precision evaluation based on simulation [Coster98], [Keding01], [Kim98] Long simulation time [Coster98] Optimization process requires multiple simulations [Sung95]

Definition of a new methodology based on an analytical approach

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A METHODOLOGY FOR EVALUATING THE PRECISION OF FIXED-POINT SYSTEMS Daniel MENARD1, Olivier SENTIEYS1,2

1 LASTI - University of Rennes I F-22300 Lannion, France [email protected]

2 COSI Project - IRISA/INRIA F-35042 Rennes cedex, France [email protected]

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Linear Time-Invariant System Model

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SFG GenerationSFG Generation

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SQNR Determination SQNR Determination

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Experimentation, Results and Perspectives

SQNR Computation Methodology

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#define pi 3.1416#define pi 3.1416main(){float x,h,z for(i=1;i<n;i++) { *z= *y++ + *h++ }

for(i=1;i<n;i++) { *z= *y++ + *h++ }

VIRGULE FLOTTANTE.C

Fixed-point coding

Precisionevaluation

#define pi 3.1416#define pi 3.1416main(){float x,h,z for(i=1;i<n;i++) { *z= *y++ + *h++ }

for(i=1;i<n;i++) { *z= *y++ + *h++ }

VIRGULE FLOTTANTE.C

Floating-pointdescription

Fixed-pointspecification

Optimization

Introduction

Propagation noise models:

Addition: z = u + v

Multiplication: z = u v

Quantization noise model:

bgi(n): additive random variable

Stationary and uniformly distributed white noise Uncorrelated with y(n) First and second-order moments:

Propagation noise models:

Addition: z = u + v

Multiplication: z = u v

Quantization noise model:

bgi(n): additive random variable

Stationary and uniformly distributed white noise Uncorrelated with y(n) First and second-order moments:

Noise models

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System noise model determination

H(z) DeterminationH(z) Determination

SFG to DAG transformation

Detection of cycles in the SFG Enumeration of the cycles Dismantling of the cycles

DAG linear function computationPartial T.F. determinationGlobal T.F. determination

SFG to DAG transformation

Detection of cycles in the SFG Enumeration of the cycles Dismantling of the cycles

DAG linear function computationPartial T.F. determinationGlobal T.F. determination

Noise modelizationNoise modelization

Signal Flow Graph + fixed-point specifications

Transfer Function (T.F.) determination

Noise source detection and insertion in the SFG

Replacement of operators by their propagation noise model

Test of the tool on classical DSP algorithms: FFT, FIR and IIR filters

Precision of the estimation: Measurement of the relative error between our estimation and the one obtained by simulation

IIR 2 < 8.2 % FIR 16 < 1.5 % FFT 16 < 2.3 %

Execution time of the tool:

Perspectives: Hardware synthesis: minimization of the chip area under SQNR constraint:

Most of the time is consumed by the cycle enumeration stage

Applications T2 Execution time (s)

IIR 2 0.08

IIR 4 0.45

IIR 4 (cascaded) 0.65

FIR 16 0.01

FIR 256 0.86

Abstract : The minimization of cost, power consumption and time to market of DSP applications requires the development of methodologies for the automatic implementation of floating-point algorithms in fixed-point architectures. In this paper, a new methodology for evaluating the quality of an implementation through the automatic determination of the Signal to Quantization Noise Ratio (SQNR) is under consideration. The modelization of the system at the quantization noise level and the expression of the output noise power have been detailed for linear systems. Then, the different phases of the methodology are explained and the ability of our approach for computing the SQNR efficiently is shown.

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