組合邏輯的函數 functions of combination logic
DESCRIPTION
Chapter 6. 組合邏輯的函數 Functions of Combination Logic. 基本的加法器 並聯二進位加法器 比較器 解碼器 編碼器 轉碼器. 多工器 ( 資料選擇器 ) 解多工器 同位元產生 / 檢查器 檢修 可程式邏輯 12. 以 VHDL 編寫邏輯函 數的程式. 1. 基本的加法器. 半加法器. Figure 6--1 Logic symbol for a half-adder( 半加器 ). Thomas L. Floyd Digital Fundamentals, 8e. 1. 基本的加法器. - PowerPoint PPT PresentationTRANSCRIPT
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組合邏輯的函數Functions of Combination Logic
Chapter 6
1. 基本的加法器2. 並聯二進位加法器3. 比較器4. 解碼器5. 編碼器6. 轉碼器
7. 多工器 ( 資料選擇器 )8. 解多工器9. 同位元產生 / 檢查器10. 檢修11. 可程式邏輯 12. 以 VHDL 編寫邏輯函 數的程式
2
Figure 6--1 Logic symbol for a half-adder( 半加器 ).
Thomas L. FloydDigital Fundamentals, 8e
1. 基本的加法器
A B Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
半加法器
3
Figure 6--2 Half-adder logic diagram.
Thomas L. FloydDigital Fundamentals, 8e
1. 基本的加法器
A B Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
4
Figure 6--3 Logic symbol for a full-adder ( 全加器 ).
Thomas L. FloydDigital Fundamentals, 8e
1. 基本的加法器
Cin A B Carry Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
全加法器
5
Figure 6--4 Full-adder logic. Open file F06-04 to verify operation.
Cin A B Carry Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1Thomas L. FloydDigital Fundamentals, 8e
1. 基本的加法器
( ) ( )
Let
( )
in in
in in
in in
Sum C A B C A B
Y A B C Y C Y
Sum C Y C A B
( ) ( ) ( )
out in in in
in
C C AB C A B C ABAB A B C
6
Figure 6--5 Full-adder implemented with half-adders.
Thomas L. FloydDigital Fundamentals, 8e
以 2 個半加器來實做全加器
7
例題 6-1 求 圖 6-6 所示的三個全加器的輸出
Thomas L. FloydDigital Fundamentals, 8e
1. 基本的加法器
1 0 0 11 0 (1 0)0 0outC
1 1 0 01 1 (1 1)0 1outC
1 0 1 01 0 (1 0)1 1outC
圖 6-6
8
Figure 6--7 Block diagram of a basic 2-bit parallel adder using two full-adders.
Thomas L. FloydDigital Fundamentals, 8e
2. 二進位平行加法器
9Figure 6-8 根據公式計算一下答案!
Thomas L. FloydDigital Fundamentals, 8e
2. 二進位平行加法器例題 6-2 如圖 6-8 所示,當輸入的二進位數為 101 與011 時,試求此 3位元平行加法器的總合與進位輸出。
10
Figure 6--9 A 4-bit parallel adder.
Thomas L. FloydDigital Fundamentals, 8e
2. 二進位平行加法器四位元平行加法器
11
進位傳遞 (carry propagation)
進位產生 進位傳遞iG iP
iii BAP
iii BAG iii CPS
iiii CPGC 1
12
進位遞迴產生器C0=輸入進位C1=G0+P0C0
C2=G1+P1C1=G1+P1G0+P1P0C0
C3=G2+P2C2=G2+P2G2+P1P2G0+P
2P1P0C0
13Figure A--2 Four-bit parallel adders.
Thomas L. FloydDigital Fundamentals, 8e
2. 二進位平行加法器
14
Figure A--3 Characteristics for the 74LS283. pp. A-3
Thomas L. FloydDigital Fundamentals, 8e
2. 二進位平行加法器
15
2. 二進位平行加法器
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四位元預見進位產生器
17Figure 6--10 Examples of adder expansion.Thomas L. FloydDigital Fundamentals, 8e
2. 二進位平行加法器
18Figure 6--11 Two 74LS83A adders connected as an 8-bit parallel adder (pin numbers are in parentheses).
Thomas L. FloydDigital Fundamentals, 8e
例題 6-4 將兩個四位元平行加法器,連接成八位元平行加法器,求輸入下列數值後,所產生之輸出位元2. 二進位平行加法器
19Figure 6--12 A voting system using full-adders and parallel binary adders.Thomas L. Floyd
Digital Fundamentals, 8e
2. 二進位平行加法器應用範例:簡單投票系統
20
Figure 6--13 Basic comparator operation.
Thomas L. FloydDigital Fundamentals, 8e
3. 比較器相等輸出
21Figure 6--14 Logic diagram for equality comparison of two 2-bit numbers. Open file F06-16 to verify operation.Thomas L. Floyd
Digital Fundamentals, 8e
3. 比較器A B F F
0 0 0 1
0 1 1 0
1 0 1 0
1 1 0 1
22
Figure 6--15
Thomas L. FloydDigital Fundamentals, 8e
例題 6-5 求下列電路的輸出3. 比較器
23Thomas L. FloydDigital Fundamentals, 8e
3. 比較器
1-bit comparator
1 1 1 1
1
in out in out
in out in out
in out out
in out
out
A
ABB AB
A B
不相等輸出
24Thomas L. FloydDigital Fundamentals, 8e
2-bit comparator
01
1 0
in out in out
in out in out
in out in out
AA
B B
0
1
0
3. 比較器
25Figure 6--16 Logic symbol for a 4-bit comparator with inequality indication.Thomas L. FloydDigital Fundamentals, 8e
3. 比較器
26
例題 6-6 求 Figure 6—17 的輸出
Thomas L. FloydDigital Fundamentals, 8e
3. 比較器
27
Figure A--4 Pin diagram and logic symbol for the 74HC85 4-bit magnitude comparator (pin numbers are in parentheses). pp. A-4
Thomas L. FloydDigital Fundamentals, 8e
3. 比較器
28
3. 比較器
29Figure 6--19 An 8-bit magnitude comparator using two 74HC85s.
Thomas L. FloydDigital Fundamentals, 8e
3. 比較器
30
Figure 6--20 Decoding logic for the binary code 1001 with an active-HIGH output.
Thomas L. FloydDigital Fundamentals, 8e
4. 解碼器基本的二進制解碼器
31
Figure 6--21 Decoding logic for producing a HIGH output when 1011 is on the inputs.
Thomas L. FloydDigital Fundamentals, 8e
例題 6-8 試設計一個解碼器 , 使得當輸入二進碼 1011 時 , 輸出 High
4. 解碼器
32Figure 6--22 Logic symbol for a 4-line-to-16-line (1-of-16) decoder. Open file F06-24 to verify operation.Thomas L. Floyd
Digital Fundamentals, 8e
4. 解碼器四位元解碼器
33Figure A—5a,b Pin diagram and logic symbol for the 74HC154 1-of-16 decoder. pp. A-5Thomas L. FloydDigital Fundamentals, 8e
4. 解碼器
34Figure A—5c Pin diagram and logic symbol for the 74HC154 de-multiplexer. pp. A-5Thomas L. FloydDigital Fundamentals, 8e
解多工器
Data input
Data selectorCS1=0 輸出為沒作用CS1=1 輸出由選擇線選到的為 Low
35Figure 6--23 A 5-bit decoder using 74HC154s.Thomas L. FloydDigital Fundamentals, 8e
4. 解碼器例題 6-9 某個應用電路需用五位元數值進行解碼,試使用兩個 4對 16線解碼器實作。
36Figure 6--24 A simplified computer I/O port system with a port address decoder with only
four address lines shown.Thomas L. FloydDigital Fundamentals, 8e
4. 解碼器應用範例:電腦輸入輸出裝置的選擇
37Figure 6--25 The 74HC42 BCD-to-decimal decoder.Thomas L. FloydDigital Fundamentals, 8e
4. 解碼器例題 6-10 BCD 轉十進位解碼器的邏輯圖如圖 6-25 ,如果將圖 6-26(a) 的輸入波形施加到輸入端,求其輸出波形?
38Figure 6--26
Thomas L. FloydDigital Fundamentals, 8e
4. 解碼器
39
Figure 6--27 Logic symbol for a BCD-to-7-segment decoder/driver with active-LOW outputs. Open file F06-30 to verify operation.
Thomas L. FloydDigital Fundamentals, 8e
4. 解碼器BCD 轉 7段顯示解碼器
40Figure A--6 Pin diagram and logic symbol for the 74LS47 BCD-to-7-segment decoder/driver. pp. A-5Thomas L. Floyd
Digital Fundamentals, 8e
0 A+B+C+D=0
BI/RBO=0 a~g disable
RBI
Light Test
BI=Blank InputRBI=Ripple BIRBO=Ripple Blank Output
4. 解碼器
41Thomas L. FloydDigital Fundamentals, 8e
Ripple Blanking(消零 )的用法
4. 解碼器
Figure A—7a Examples of zero suppression using the 74LS47 BCD to 7-segment decoder/driver. pp. A-6
42Thomas L. FloydDigital Fundamentals, 8e
Ripple Blanking(消零 )的用法
4. 解碼器
Figure A—7b Examples of zero suppression using the 74LS47 BCD to 7-segment decoder/driver. pp. A-6
43Figure 6--28 Logic symbol for a decimal-to-BCD encoder.
Thomas L. FloydDigital Fundamentals, 8e
5. 編碼器十進位轉 BCD編碼器
44
Figure 6--29 Basic logic diagram of a decimal-to-BCD encoder.
Thomas L. FloydDigital Fundamentals, 8e
沒有優先權編碼的缺點:兩輸入同時 active 會出錯
A 0-digit input is not needed because the BCD outputs are all LOW when there are no HIGH inputs.
45
編碼器•編碼器 : 解碼器的反函數 • 8 到 3 優先權編碼器 :
46
8 到 3 優先權編碼器c=y7y6y5y4y3y2y1+y7y6y5y4y3+y7y6y5+y7
=y7+y6y5+y6y4y3+y6y4y2y1
b=y7y6y5y4y3y2+y7y6y5y4y3+y7y6+y7
=y7+y6+y5y4y3+y5y4y2
a=y7y6y5y4+y7y6y5+y7y6+y7
=y7+y6+y5+y4
47
8 到 3 優先權編碼器 y7 y6 y5 y4 y3 y2 y1 y0
a
b
c
48Figure A--8 Pin diagram and logic symbol for the 74HC147 decimal-to-BCD priority
encoder (HPRI means highest value input has priority). pp. A-7Thomas L. FloydDigital Fundamentals, 8e
10 進位轉 BCD 編碼器
49Figure A--9 Logic symbol for the 74F148 8-line-to-3-line encoder. pp. A-8
Thomas L. FloydDigital Fundamentals, 8e
8 對 3 線 編碼器
EI=Low No Input Low EO=low
At least one Input Low GS=low
5. 編碼器
50Figure A--10 A 16-line-to-4 line encoder using 74F148s and external logic. pp. A-8
Thomas L. FloydDigital Fundamentals, 8e
EI=Low 8~15 pin No Input Low
EO=lowAt least one Input Low GS=low
5. 編碼器
51Thomas L. FloydDigital Fundamentals, 8e
提升電阻 (pull-up resistor): 確保無按鍵時,輸出仍為 High
Figure 6--30 A simplified keyboard encoder.
應用範例:鍵盤編碼器
52
Figure 6--31 Four-bit binary-to-Gray conversion logic. Open file F06-39 to verify operation.
Thomas L. FloydDigital Fundamentals, 8e
Binary 轉 Gray 轉碼器
Figure 6--32 Four-bit Gray-to-binary conversion logic. Open file F06-40 to verify operation.
1 0i
n n
ii
G BBG nB i
1 0i
n n
ii
B GBB nG i
Gray 轉 Binary 轉碼器
53Figure 6--33
Thomas L. FloydDigital Fundamentals, 8e
54Figure 6--36 Logic symbol for a 1-of-4 data selector/multiplexer. pp. A-8
Thomas L. FloydDigital Fundamentals, 8e
7. 多工器 ( 資料選擇器 )
Figure A—5c Pin diagram and logic symbol for the 74HC154 de-multiplexer. pp. A-5
Thomas L. FloydDigital Fundamentals, 8e
解多工器
Data input
Data selector
CS1=Low 則有輸出 0 , 否則為 1
55Figure 6--35 Logic diagram for a 4-input multiplexer. Open file F06-43 to verify
operation.Thomas L. FloydDigital Fundamentals, 8e
7. 多工器 ( 資料選擇器 )
56Figure 6--36
Thomas L. FloydDigital Fundamentals, 8e
7. 多工器 ( 資料選擇器 )
57
Figure A--11 Pin diagram and logic symbol for the 74HC157 A quadruple 2-input data selector/multiplexer. pp. A-9
i.e. 4-bit multiplexer ( 同時選 1A~4A(G1=0 時 , Y=A) 或 1B~4B(G1=1 時 ,Y=B) )
Thomas L. FloydDigital Fundamentals, 8e
7. 多工器 ( 資料選擇器 )
58Figure A--12 Pin diagram and logic symbol for the 74LS151 8-input data
selector/multiplexer. pp. A-10Thomas L. FloydDigital Fundamentals, 8e
7. 多工器 ( 資料選擇器 )
59Figure 6--37 A 16-input multiplexer.Thomas L. FloydDigital Fundamentals, 8e
7. 多工器 ( 資料選擇器 )
60Figure 6--38 Simplified 7-segment display multiplexing logic.Thomas L. Floyd
Digital Fundamentals, 8e
61Figure 6--39 Data selector/multiplexer connected as a 3-variable logic function generator.
1 3 5 6
2 1 0 2 1 0 2 1 0 2 1 0
0 0 1 0 1 1 1 0 1 1 1 0
Y Y Y Y Y
A A A A A A A A A A A A
Thomas L. FloydDigital Fundamentals, 8e
Yin A2 A1 A0 Yout
0 0 0 0 01 0 0 1 12 0 1 0 03 0 1 1 14 1 0 0 05 1 0 1 16 1 1 0 17 1 1 1 0
62
Figure 6--40 Data selector/multiplexer connected as a 4-variable logic function generator.
0
0
0
0
0
0
1
1
A
AA
A
A
A
Yin A3 A2 A1 A0 Yout Yout
00
0 0 0 0 0 A01 0 0 0 1 12
10 0 1 0 1 A0
'
3 0 0 1 1 04
20 1 0 0 0 A05 0 1 0 1 1
63
0 1 1 0 11
7 0 1 1 1 18
41 0 0 0 1 A0
'
9 1 0 0 1 010
51 0 1 0 1 A0
'
11 1 0 1 1 012
61 1 0 0 1
113 1 1 0 1 114
71 1 1 0 0 A015 1 1 1 1 1
Thomas L. FloydDigital Fundamentals, 8e
0 0 1 0 2 0 3
4 0 5 0 6 7 0
1
1
Y Y A Y A Y A Y
Y A Y A Y Y A
63
Figure 6--41 A 1-line-to-4-line demultiplexer.
Thomas L. FloydDigital Fundamentals, 8e
8.解多工器
Figure 6--42
64Figure A—5c The 74HC154 decoder used as a de-multiplexer. pp. A-5Thomas L. FloydDigital Fundamentals, 8e
8.解多工器
65
Figure 6--43
Thomas L. FloydDigital Fundamentals, 8e
基本同位元邏輯
66
Figure 6--44 The 74LS280 9-bit parity generator/checker.
Thomas L. FloydDigital Fundamentals, 8e
同位元產生 / 檢查器•Even parity checker•Odd parity generator
67Figure 6--45 Simplified data transmission system with error detection.Thomas L. FloydDigital Fundamentals, 8e
用 Decoder當 DeMUX用
68
Figure 6--46 Example of data transmission with and without error for the system in Figure 6-45.
Thomas L. FloydDigital Fundamentals, 8e
9. 同位元產生 / 檢查器
69Figure 6--47 Decoder waveforms with output glitches.
Thomas L. FloydDigital Fundamentals, 8e
10. 檢修
70Figure 6--48 Decoder waveform displays showing how transitional input states produce glitches in the output waveforms.Thomas L. Floyd
Digital Fundamentals, 8e
10. 檢修
71Figure 6--49 Application of a strobe waveform to eliminate glitches on decoder outputs.
Thomas L. FloydDigital Fundamentals, 8e
去除 Glitch 的方法之一 , 就是用Strobe
10. 檢修
72Figure 6--61 Typical configuration for conventional PLD programming.
Thomas L. FloydDigital Fundamentals, 8e
11. 可程式邏輯
73
位元向量 (Bit Vectors) 與陣列 ( Arrays)
• 位元向量 (bit_vector) 資料型別允許將若干位元編組成一個陣列。• 陣列是具有單一識別字,並且由個別元素所組合的有序集合。• 陣列中每一個元素都共用一個識別字,並利用數字索
引 (index) 去存取陣列中元素。• 例如:假如以 bit vector 資料型別去宣告識別字 A ,則我們可以 A(0) 存取 A中第一個元素,以 A(1) 存取 A中下一個元素。• Port(A: in bit_vector(0 to 7)); 表示輸入埠有 8個輸入 :
A(0), A(1), A(2), … A(7)
12. 以 VHDL 編寫邏輯函數的程式
74
BCD to 7 segment display decoder
ABCD
OA
ODOEOF
OCOB
OG
U1
BCD_7SEG_DCD~RBO
~BI~LT~RBI
A(0)
A(1)
A(2)
A(3)
X(0)
X(1)
X(2)
X(3)
X(4)
X(5)
X(6)
75
BCD to 7 segment display 解碼器使用資料流描述法entity BCD_to_seven_segment is
port( A: in bit_vector(0 to 3): X: out bit_vector(0 to 6));
end entity BCD_to_seven_segment
architecture decoder of BCD_to_seven_segment is
begin
X(0) <= (not A(1) and not A(3)) or (not A(1) and A(2)) or (A(1) and A(3)) or A(0);
X(1)<= (not A(2) and not A(3)) or (A(2) and A(3)) or not A(1);
76
BCD to 7 segment display 解碼器使用資料流描述法(續) X(2)<= A(1) or A(3) or not A(2)
X(3) <= (not A(1) and A(2)) or (A(1) and not A(2) and A(3)) or (A(2) and not A(3)) or (not A(1) and not A(3));
X(4) <= (A(2) and not A(3)) or (not A(1) and not A(3));
X(5) <= (not A(2) and not A(3)) or (A(1) and not A(2)) or (A(1) and not A(3)) or A(0);
X(6) <= (A(1) xor A(2)) or A(0);
end architecture decoder
77
-- 全加器使用資料流描述法 .
entity FULLADDER is
port (X: in bit; Y: in bit; Cin: in bit;
Cout: out bit; Sum: out bit);
end FULLADDER;
architecture full_adder_logic of FULLADDER is
begin
Sum <= X xor Y xor Cin;
Cout <= (X and Y) or (X and Cin) or (Y and Cin);
end full_adder_logic;
78
全加器測試
79
End of Chapter 6