© kavita bala, computer science, cornell university kevin walsh cs 3410, spring 2010 computer...

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© Kavita Bala, Computer Science, Cornell University Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University Pipelining See: P&H Chapter 4.5

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© Kavita Bala, Computer Science, Cornell University

Kevin WalshCS 3410, Spring 2010

Computer ScienceCornell University

Pipelining

See: P&H Chapter 4.5

© Kavita Bala, Computer Science, Cornell University 2

The Kids

Alice

Bob

They don’t always get along…

© Kavita Bala, Computer Science, Cornell University 3

The Bicycle

© Kavita Bala, Computer Science, Cornell University 4

The Materials

Saw Drill

Glue Paint

© Kavita Bala, Computer Science, Cornell University 5

The Instructions

N pieces, each built following same sequence:

Saw Drill Glue Paint

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Design 1: Sequential Schedule

Alice owns the roomBob can enter when Alice is finishedRepeat for remaining tasksNo possibility for conflicts

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Elapsed Time for Alice: 4Elapsed Time for Bob: 4Total elapsed time: 4*NCan we do better?

Sequential Performance

time1 2 3 4 5 6 7 8 …

Latency:Throughput:Concurrency:

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Design 2: Pipelined Design

Partition room into stages of a pipeline

One person owns a stage at a time4 stages4 people working simultaneouslyEveryone moves right in lockstep

AliceBobCarolDave

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Pipelined Performancetime1 2 3 4 5 6 7…

Latency:Throughput:Concurrency:

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Unequal Pipeline Stages

0h 1h 2h 3h…

15 min 30 min 45 min 90 min

Latency:Throughput:Concurrency:

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Poorly-balanced Pipeline Stages

0h 1h 2h 3h…

15 min 30 min 45 min 90 min

Latency:Throughput:Concurrency:

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Re-Balanced Pipeline Stages

0h 1h 2h 3h…

15 min 30 min 45 min 90 min

Latency:Throughput:Concurrency:

© Kavita Bala, Computer Science, Cornell University 13

Splitting Pipeline Stages

0h 1h 2h 3h…

15 min 30 min 45 min 45+45 min

Latency:Throughput:Concurrency:

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Pipeline Hazards

0h 1h 2h 3h…

Q: What if glue step of task 3 depends on output of task 1?

Latency:Throughput:Concurrency:

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Lessons

Principle:Latencies can be masked by parallel execution

Pipelining:• Identify pipeline stages• Isolate stages from each other• Resolve pipeline hazards

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A Processor

alu

PC

imm

memory

memory

din

do

ut

addr

target

offset cmpcontrol

=?

new pc

registerfile

inst

extend

+4 +4

© Kavita Bala, Computer Science, Cornell University 17

Write-BackMemory

InstructionFetch Execute

InstructionDecode

registerfile

control

A Processor

alu

imm

memory

din

do

ut

addr

inst

PC

memory

computejump/branch

targets

new pc

+4

extend

© Kavita Bala, Computer Science, Cornell University 18

Basic Pipeline

Five stage “RISC” load-store architecture1. Instruction fetch (IF)

– get instruction from memory, increment PC2. Instruction Decode (ID)

– translate opcode into control signals and read registers3. Execute (EX)

– perform ALU operation, compute jump/branch targets4. Memory (MEM)

– access memory if needed5. Writeback (WB)

– update register file

Slides thanks to Sally McKee & Kavita Bala

© Kavita Bala, Computer Science, Cornell University 19

Pipelined Implementation

Break instructions across multiple clock cycles (five, in this case)

Design a separate stage for the execution performed during each clock cycle

Add pipeline registers to isolate signals between different stages