© lattice semiconductor corporation verilog training feb. 1998 0 lattice verilog training part i...

© LATTICE SEMICONDUCTOR CORPORATION

Verilog TrainingFeb. 19981

Lattice Verilog Training

Part I

Jimmy Gao



Verilog

Basic Modeling Structure



Verilog Design Description

• Verilog language describes a digital system as a set of modules

module counter(…); module module_name (port_list);

… … declares

endmodule module_items

module t_ff(…); endmodule

... ...

endmodule

module dff(…);

… …

endmodule

module inv(…);

… …

endmodule

Ripple CarryCounterRipple CarryCounter

T_FF(tff0)T_FF(tff0)




DFFDFF INVINV DFFDFF INVINV DFFDFF INVINV DFFDFF INVINV



The Black Box Example

• Verilog description of the black box:module black_box(Rst, Clk, D, Q, CO);

input Rst, Clk;

input[7:0] D;

output CO;

output[7:0] Q;

… … …

endmodule

Black Box

D[7:0]

Rst

CLK

Q[7:0]

CO



Simple Verilog Examplemodule logic ( a, b, w, x, y, z); // Module name & Port list

// Declaration section input a, b; output x, y, z; output [3:0] w;

// Module Items// Continuous Assignment assign z = a ^ b; // XORassign y = a & b; // ANDassign x = 1’b1;assign w = 4’b1010;

endmodule

ab z

y

x

w

1’b1

4’b1010

Describe Design I/Os

Describe Design Content



Verilog Design Description

The module_name is an identifier of the modules

The port_list is a list of input, output and inout ports which are used to connect to other modules

The declares section specifies the type of data objects (input, output, inout, regs, wires etc) and procedural constructs (functions and tasks)

The module_items may be

• always constructs => behavioral modeling

• continuous assignments => data flow modeling

• instantiation of modules => structural modeling

REMEMBER:

The identifiers in Verilog are case-sensitive and all keywords must be in lower-case



DECLARATIONSExternal Ports

• input A signal that goes into the module

• output A signal that goes out of the module

• inout A signal that is bi-directional (goes into and out of the module

Internal Data Objects

• wire A net without storage capacity

• reg can store the last value assigned; physical data type; not a hardware register yet

• integer

• real other register type declaration; abstract data type

• time



DECLARATIONS• Declaration FormatClass Width Data-Object Example

input [4:0] a; 5’b10001

inout b; 1’b1

output [3:0] c; 4’hF

reg [0:2] d; 3’b001

wire e; 1’b0

integer f; -40

real g; 3.12

time h; 6

Physical Data Type

Abstract Data Type

`timescale 1ns / 0.1ns time h; assign h = 6 ; 6ns



Data Types

• Physical Data Types (for reg and wire)0 logical zero or false

1 logical one or true

x unknown logical value

z high impedance of tristate gate

• Abstract Data Types integer a general purpose 32-bit variable

real a real number (no range declaration)

time units for simulation time



Number Specification

• Sized Number4’b1010 // 4-bit binary number “1010”

12’hafd // 12-bit hexadecimal number “afd”

16’d225 // 16-bit decimal number “225”

• Unsized Number 23456 // 32-bit decimal number

‘hc3 // 32-bit hexadecimal number

‘o21 // 32-bit octal number

• X or Z value6’hx // 6-bit hex number

32’bz // 32-bit high impedance number



Number Specificationwire [7:0] bus;

bus = 8’b10101010; bus = 8’bz;

bus = 8’hFF; bus = 8’hx;

reg reset;

reset = 1’b1;

integer counter;

counter = -1; counter = ‘hA;

real delta;

delta = 4e10;



Verilog Language Syntax &

Verilog Design Methods



Structure of Verilog Module

Port declarationWire, Regs declarationetc.

Continuous Assignments

Data Flow Modeling

Instantiation of lower level modules

Structural Modeling

Always blocks

Behavioral Modeling

module Name ( Port list );

endmodule

Module Items:

Declaration Sections



Structural Modelingmodule one_bit_full_adder ( sum, cout, a, b, cin );// Declaration sectioninput a, b, cin;output sum, cout;wire s1, s2, c1;// Structural Modeling Method - Instantiation of modules XOR2 X1(.Z0(s1), .A0(a), .A1(b)); AND2 A1(.Z0(c1), .A0(a), .A1(b)); XOR2 O1(.Z0(cout), .A0(s2), .A1(c1));

XOR2 X2(sum, s1, cin); AND2 A2(s2, s1, cin);

endmodule

A0

A1

Z0

Library Symbol: AND2

ab

cin

s1

c1 s2

sum

cout

module AND2 (Z0, A0, A1);

input A0, A1; output Z0;

endmodule

A1

X1X2

A2O1

A0

A1Z0

AND2



Verilog Exercise 1Complete the instantiation statements in following structural Verilog design. Use name association for the first one and positional association for the second.

module design (data_in, clock, clear, out_enable, data_out); input data_in, clock, clear, out_enable; output data_out; wire q;

FD21 dff1 ( ); // Name Association OT11 obuf1 ( ); // Position Association

endmodule

oe

XO0A0D0 Q0

CLKCD

data_out

out_enable

data_in

clock

clear

module OT11(XO0,A0,OE); input A0, OE; output XO0;

endmodule

q

OT11FD21



Verilog Exercise 1 - Answer

module design (data_in, clock, clear, out_enable, data_out); input data_in, clock, clear, out_enable; output data_out; wire q;

// Name Association FD21 dff1 (.D0(data_in), .Q0(q), .CLK(clock), .CD(clear)); // Position Association OT11 obuf1 ( data_out, q, out_enable );

endmodule

oe

XO0A0D0 Q0

CLKCD

data_out

out_enable

data_in

clock

clear

module OT11(XO0,A0,OE); input A0, OE; output XO0;

endmodule

q

OT11FD21



Data Flow Modeling - Continuous Assignment

• Continuous assignment Use assign key word; Execute concurrently

assign out = i1 & i2; // AND

assign addr[15:0] = addr1_bits[15:0] ^ addr2_bits[15:0]; // XOR

Implicit Continuous Assignment

// Regular continuous assignment

wire out;

assign out = in1 & in2;

// Implicit continuous assignment

wire out = in1 & in2;

Continuous Assignment with conditional operator

assign x = y ? b + a : b;NOTE: Variable = (Test Condition) ? (True logic) : (False Logic)



Continuous Assignment Format

• Assign (keyword) + Logical Expression;

assign out = a & b;

Left operand Right operands operator



Conditional Continuous Assignment Format

• Assign (keyword) + Conditional Logical Expression;

assign target = condition ? 1st-Expression : 2nd-Expression

If condition is TRUE or One, target = 1st-Expression;If condition is FALSE or Zero, target = 2nd-Expression.

Ex: x = y ? a + b + c : m - n - p;

if y = 1’b1, x = a + b + c; if y = 1’b0, x = m - n - p;



Operators• Binary Arithmetic Operators operate on two operands

Operator Name Comments+ Addition- Subtraction* Multiplication/ Division divide by zero produces an x.% Modulus

• Logical Operators operate on logical operands and return a logical value

Operator Name! Logical Negation&& Logical AND|| Logical OR



Operators• Relational Operators compare two operands and return a

logical value.

Operator Name Comments> Greater than< Less than>= Greater than or equal to<= Less than or equal to

• Equality Operators compare two operands and return a logical value.

Operator Name Comments== Equality result unknown if including x

or z!= Inequality result unknown if including x

or z=== Case Equality equal including x or z!== Case Inequality unequal including x or z



Operators• Bitwise Operators operate on the bits of operands

Operator Name~ Bitwise negation& Bitwise AND| Bitwise OR^ Bitwise XOR~& Bitwise NAND~| Bitwise NOR~^ or ^~ Bitwise NOT XOR



Operators ExamplesExample: a = 4’b1000 b=4’b0111

(1) a & b 4’b0000

a ^ b 4’b1111

(2) a - b 4’b1000 - 4’b0111 = 4’b0001 8 - 7 = 1

(3) a > b compare 4’b1000 > 4’b0111 TRUE

a == b compare 4’b1000 = =4’b0111 FALSE

(4) !(a > b ) !(TRUE) FALSE

( a > b ) || ( a == b ) TRUE || FALSE TRUE

1000

0111

0000

1000

0111

1111

Bitwise AND

BitwiseXOR



Operators• Shift Operators

Operator Name<< Shift Left>> Shift Right

// A = 4’b1010;Y = A << 1; // Y = 4’b0100; Y = A >> 2; // Y = 4’b0010;

• Concatenation Operator {,}

// A = 2’b00; B = 2’b10;Y = {A, B}; // Y = 4’b0010;Y = {2{A}, 3{B}}; // Y = 10’b0000101010;

Add Zero at the end while left shifting

Add Zero at the beginning while right shifting



Data Flow Modeling Examplemodule one_bit_full_adder ( sum, cout, a, b, cin );// Declaration sectioninput a, b, cin;output sum, cout;wire s1, s2, c1;// Structural Modeling Method - Continuous Statementassign s1 = a ^ b;assign c1 = a & b;

assign sum = s1 ^ cin;assign s2 = s1 & cin;

assign cout = s2 ^ cin;endmodule

ab

cin

s1

c1 s2

sum

cout



Verilog Exercise 2Please Complete the following Design in Data-Flow Modeling Method by using concurrent conditional assignment.

module four_to_one_mux ( a, b, c, d, s0, s1, o );// Declaration sectioninput a, b, c, d, s0, s1;output o;wire m0, m1;

// Module Items in Data-Flow Modeling Method

endmodule

a

b

c

d

m0

m1

os0

s1



Verilog Exercise 2 - Answermodule four_to_one_mux ( a, b, c, d, s0, s1, o );// Declaration sectioninput a, b, c, d, s0, s1;output o;wire m0, m1;// Structural Modeling Method - Continuous Statementassign m0 = s0 ? a : b;assign m1 = s0 ? c : d;assign o = s1 ? m0 : m1;

// assign o = s1 ? ( s0 ? a : b) : ( s0 ? c : d);endmodule

a

b

c

d

m0

m1

os0

s1



Behavioral Modeling• always Block

� Basic Structured Procedure in behavioral modeling

� All other behavioral statements can appear only inside the always Block

Timing ControlEvent Based Timing Control @

Procedural AssignmentsBlocking Assignment (sequential) =Non-Blocking Assignment (concurrent) <=

Conditional StatementIf-Else Statement

Multi-way BranchingCase Statement



always block with Event-Based Timing Control

• The syntax of an always block is:

always @ (event or event or ...)

begin statement1; statement2; …… statementN; statementN+1;

end

• Statements can be executed when the specified event occurs.

• A always block is generally used to implement latches or flip-flops.

Each statement executes sequentially



always block

• Simple example of always

reg q;always @(posedge clk) // the sensitivity list

begin

q = d; // define the always block

end;

• Here the signal ‘q’ is sensitive to a rising edge on signal ‘clk’. Whenever the condition is met, the statement inside the process will be evaluated

• ‘q’ is declared as reg type and ‘q’ is sensitive to a rising edge. Therefore ‘q’ becomes a hardware register.

clk

d q



always block vs. continuous assignment • Another example of always

input a, b, s; out x; reg x;

always @(a or b or s) // Behavioral Modeling

begin

if ( !s ) x = a; else x = b; Process activates when any of

these

end; signals change state

• ‘x’ is declared as reg type but ‘x’ is sensitive to level changes of signal ‘a’, ‘b’, ‘s’. Therefore ‘x’ is not hardware register.

• This example also can be implemented by using assign statement:

assign x = s ? b : a; // Data Flow Modeling

a

b

s

x



Procedural Assignments - Blocking Assignments

• Procedural assignments - Blocking Assignments

Procedural blocking assignments are sequential; Statements inside the block execute in sequence, one after another.

Example

// breg, creg, dreg are related.

reg breg, creg, dreg;

always @( posedge clk )

begin

breg = areg;

creg = breg;

dreg = creg;

end

clk

areg

breg

creg

dreg



Procedural Assignments - Non-Blocking Assignments

• Procedural assignments - Non-Blocking Assignments

Procedural Non-blocking assignments are concurrent; Statements inside the block execute right at the same time.

Example

// breg, creg, dreg are related.

reg breg, creg, dreg;

always ( posedge clk )

begin

breg <= areg;

creg <= breg;

dreg <= creg;

endclk

areg

breg

creg

dreg



Blocking Assignments vs. Non-Blocking Assignments always @( a )

begin

#10 b = a; // AT TIME UNIT 10

#10 c = b; // AT TIME UNIT 20

#10 d = c; // AT TIME UNIT 30

#10 o = d; // AT TIME UNIT 40

end

always @( a )

begin

#10 b <= a; // AT TIME UNIT 10

#10 c <= b; // AT TIME UNIT 10

#10 d <= c; // AT TIME UNIT 10

#10 o <= d; // AT TIME UNIT 10

end



Procedural Assignments - Blocking/Non-Blocking Assignments module regs (a, b, c, clk, q1, q2, q3);

output q1, q2, q3; input a, b, c, clk; reg q1, q2, q3;


begin

q1 = a;

q2 = b;

q3 = c;

end endmodule

module regs (a, b, c, clk, q1, q2, q3);

output q1, q2, q3; input a, b, c, clk; reg q1, q2, q3;


begin

q1 <= a;

q2 <= b;

q3 <= c;

end endmodule

a

clk

q1

b

clk

q2

c

clk

q3

q1 = a

q2 = a

q3 = a

t t

a

clk

q1

b

clk

q2

c

clk

q3

q1 = a

q2 = a

q3 = a



Procedural Assignment Format

always @ ( sensitive event list ) begin

// Procedural Assignmentsxyz <= m & n; // non-blocking assignmentout = a ^ b; // blocking assignment

Logical Expressionxyz <= m ^ n;

out = a & b;

Left operand Right operands operator

end



Continuous Asign. vs. Procedural Blocking Assign.

module design ( …. );…..// Continuous Assignments// Statements are executed concurrentlyassign sum = a + b;

assign z = x ^ y;

always @ ( sensitive event list ) begin

….// Procedural Blocking Assignments// Statements are executed sequentiallyw = m & n;

k = p ^ q; end

endmodule

The Statements inside the always block as a whole is executed concurrently



Conditional Statements -- if - else

• Conditional Statements -- if ... else if ... else statements execute a block of statements according to the

value of one or more expressions.

if (expressions)

begin

... statements ...

end

else statement-block

begin

... statements ...

end

if ( expressions ) single statement A;

else if ( expression ) single statement B;

else single statement C;



Multi-way Branching -- case

• Multi-way Branching -case case statement is a special multi-way decision statement that

tests whether an expression matches one of the other expressions, and branches accordingly

reg[1:0] rega;reg[3:0] result;... ...

case (rega)2’b00: result = 4’b0000;2’b01: result = 4’b0001;2’b10 : result = 4’b1000;default: result = 4’b1111;

endcase



Verilog Reviewmodule Example (a, b, c, d, s, o );// port declaration sectioninput a, b, c, d, s;output o;// wire & reg declaration sectionwire m0, m1;reg temp1, temp2, o;

// continuous assignmentassign m0 = a ^ b;// instantiation statementAND2 A1(.Z0( m1 ), .A0( c ), .A1( d ));

// always blockalways @(m0 or m1 or s) begin temp1 = m0; temp2 = m1;

if ( s == 1’b0 ) o = temp1; else o = temp2; endendmodule

a

b

c

d

s

om0

m1

always block as a whole is executed concurrently

statements outside always block executed currently

Statements inside always block executed sequentially



Verilog Exercise 3

• What kind of hardware function is composed by the following Verilog design?

• What is wrong with the following Verilog design code?

• Can you re-write the Verilog code by using if-then-else statement?



Verilog Exercise 3Module design (out, a, b, c, d, s0, s1);input a, b, c, d, s0, s1;output out;

always case ( {s1, s0} )

2’b00: out = a;2’b01: out = b;2’b10: out = c;2’b11: out = d;

endcaseendmodule



Verilog Exercise 3 - AnswerModule design (out, a, b, c, d, s0, s1);input a, b, c, d, s0, s1;output out;reg out;// left-hand value inside the always // statement must retain value. Therefore// “out” must be “reg” type. But “out” is // not hardware register.

always @(a or b or c or d or s0 or s1) // Sensitive Listcase ( {s1, s0} )

2’b00: out = a;2’b01: out = b;2’b10: out = c;2’b11: out = d;

endcaseendmodule

a

b

d

c

s0

s1

out



Verilog Exercise 3 - Answermodule mux4_to_1 (out, a, b, c, d, s0, s1);input a, b, c, d, s0, s1;output out;reg out;// left-hand value inside the always // statement must retain value. Therefore// “out” must be “reg” type. But “out” is // not hardware register.

always @(a or b or c or d or s0 or s1) // Sensitive Listif ( { s0, s1 } == 2’b00 )

out = a;else if ( { s0, s1 } == 2’b01 )

out = b;else if ( { s0, s1 } == 2’b10 )

out = c;else

out = d; endendmodule

a

b

d

c

s0

s1

out



Lab One - Combinatorial Logic

Please Turn to your Verilog Lab Book for the Verilog Design Lab No. One



Understand Verilog Synthesis &

Verilog Design Application



Registers in Verilog

• Registers -- declarations and triggers

declares:input clk, x_in;input data1, data2, data3;input [4:0] q_in;

reg x; // single bitreg a, b, c; // three single-bit registersreg[4:0] q; // a 5-bit vector

triggers:always @(posedge clk) begin

q = q_in;end

always @(negedge clk) beginx = x_in;a = data1;b = data2;c = data3;

end

q_in

clk

x_in

clk

q

x

0

1

1

0



Registers in Verilog -- asynchronous reset• Registers -- Asynchronous Reset

module async_reset(d, clk, rst, q);

input d, clk, rst;

output q;

reg q;

always @(posedge clk or posedge rst)

begin

if (rst)

q = 0; // asynchronous reset

else

if ( clk )

q = d;

end

endmodule

d

clk

rst

q



Registers in Verilog -- synchronous reset• Registers -- synchronous Reset

module sync_reset(d, clk, rst, q);

input d, clk, rst;

output q;

reg q;

always @(posedge clk)

begin

if (clk)

begin

if ( rst )

q = 0; // synchronous reset

else

q = d;

end

end

endmodule

clk

q

rst

d

1’b0



Registers in Verilog -- Short Format• Register -- synchronous Reset

module sync_reset(d, clk, rst, q);

input d, clk, rst; output q; reg q;

always @(posedge clk)

if ( rst )


else

q = d;

endmodule

• Register -- Asynchronous Reset module asyn_reset(d, clk, rst, q);

input d, clk, rst; output q; reg q;

always @(posedge clk or posedge rst)

if ( rst )


else

q = d;

endmodule

d

clk

rst

q

clk

q

rst

d

1’b0



Asynchronous Reset Counter

module counter(clock,asy_reset,count);

input clock, asy_reset;

output [0:3] count;

reg [0:3] count;

always @ ( posedge clock or posedge asy_reset )

begin

if ( asy_reset )

count = 4’b0000;

else begin

if (clock) count = count + 4’b0001;

end

end

endmodule

count

count

clock

asy_reset



Synchronous Reset Counter

module counter(clock,syn_reset,count);

input clock, syn_reset;

output [0:3] count;

reg [0:3] count;

always @ ( posedge clock )

begin

if ( clock )

begin

if ( syn_reset )

count = 4’b0000;

else

count = count + 4’b0001;

end

end

endmodule

count

count

clock

syn_reset



Latches in Verilog -- asynchronous reset• Latches -- asynchronous Reset

module async_reset_dlatch(d, enable, rst, q);

input d, enable, rst;

output q;

reg q

always @(enable or rst or d )

begin

if (rst)


else

begin

if ( enable )

q = d;

end

end

endmodule

d

enable

rst

q



Latches in Verilog -- synchronous reset• Latches -- synchronous Reset

module sync_reset_dlatch(d, enable, rst, q);

input d, enable, rst;

output q;

reg q;

always @(enable or d )

begin

if (enable)

begin

if ( rst )


else

q = d;

end

end

endmodule

d

enable

q

rst

1’b0



asynchronous/synchronous reset(cont’d)• Latches -- asynchronous Reset

module async_reset_dlatch(d, enable, Rst, Q);

input d, enable, Rst;

output Q;

// asynchronous reset D_Latch

assign Q = Rst ? 0 : ( enable ? d : Q );

// wire Q = Rst ? 0 : ( enable ? d : Q );

endmodule

• Latches -- synchronous Reset module sync_reset_dlatch(d, enable, Rst, Q);

input d, enable, Rst;

output Q;

// synchronous reset D_Latch

assign Q = enable ? ( Rst ? 0 : d ): Q;

// wire Q = enable ? ( Rst ? 0 : d ): Q;

endmodule



Output Enable

• Example 1:module oe1(data, data_in, enable);

output data;

input data_in, enable;

reg data;

always @(enable)

if(enable) data = data_in;

else data = 1’bz;

endmodule;


output data;


assign data = enable ? data_in : 1’bz;

endmodule;


output data;


wire data = enable ? data_in : 1’bz;

endmodule;

enable

data_indata



Bi-Directional Port

• Example 1:module bi-port1(data, data_in, enable, fb)

inout data;


output fb;

assign data = enable ? data_in : 1’bz;

assign fb = data;

endmodule

• Example 2: module bi-port2(data, data_in, enable, fb);

inout data;


output fb;

wire data = enable ? data_in : 1’bz;

wire fb = data;

endmodule

enable

data_in data

fb



Implicit Synthesis Result: Excluding “else” implies latch

• Implied memory (latch) will occur if future value of signal cannot be determined

• if-else statement

always @(a or b) begin

if (a)

begin

step = b;

end

end

• The signal will keep the previous value in this case

• A latch may also be created by using case statement;

Specify all conditions to avoid implied latch

astep

b



Verilog Exercise 4

• The following Verilog Design is a 4-bit counter with Asynchronous Reset, Synchronous Preset and Synchronous Load. Please fill in the blank section of the Verilog source code to complete the design.



Verilog Exercise 4module counter(clock,asy_reset,syn_preset,syn_load,data_in,count);

input clock, asy_reset, syn_preset, syn_load;

input [0:3] data_in;

output [0:3] count;

reg [0:3] count;

always @ ( )

begin

if ( )

count = 4’b0000;

else begin

if (clock) begin

if ( )

count = 4’b1111;

else if ( )

count = data_in;

else


end

end

end

endmodule



Verilog Exercise 4 - Answermodule counter(clock,asy_reset,syn_preset,syn_load,data_in,count);

input clock, asy_reset, syn_preset, syn_load;

input [0:3] data_in;

output [0:3] count;

reg [0:3] count;

always @(posedge clock or posedge asy_reset)

begin

if (asy_reset == 1’b1)

count = 4’b0000;

else begin

if (clock) begin

if ( syn_preset )

count = 4’b1111;

else if ( syn_load )

count = data_in;

else


end

end

end

endmodule



Verilog Hierarchical Design



Hierarchy Designs

• Advantages:

Allows duplication of common building blocks Components (Verilog modules) can be created,

tested and held for use later Smaller components can be more easily integrated

with other blocks Designs become more readable Designs become more portable The design task can be split among several members

of a team



Hierarchy Designs (cont.)

• Design examplemodule addmult(op1, op2, result);

input[2:0] op1, op2;output[3:0] result;wire[3:0] s_add; component declaration

add adder(op1, op2, s_add); name of lower level component

assign result = s_add - 2’b10;endmodule

module add(in1, in2, out1); // lower level component addinput[2:0] in1, in2;output[3:0] out1;

assign out1 = in1 + in2;

endmodule

add

in1

in2out1 s_add

2’b10

op1

op2result

addmult




• Lower level design can be in the same file as the top-level design (above example) or in a separate file with a user defined file name`include add.v // include File add.v.

// This Format is not needed for Synplicity.

module addmult(op1, op2, result);input[2:0] op1, op2;output[3:0] result;wire[3:0] s_add;

add adder(op1, op2, s_add);

assign result = s_add - 2;

endmodule

• Important!!! A ` is NOT the same as a ‘. See include above!

NOTE: Same as 2’b10 in previous example




• Two files (top level and lower level) also can be compiled separately

• Low level module saved in “add.v” for previous example

// For Synplicity, Just include the file add.v in the // synthesizing list. No Verilog Directive `include needed.

module add(in1, in2, out1); input[2:0] in1, in2;output[3:0] out1;

assign out1 = in1 + in2;

endmodule



Lab Two - T-FF, Ripple Carry Counter & Hierarchical Design

Please Turn to your Verilog Lab Book for the Verilog Design Lab No. Two



Contact: Jeffery, Hawking , Nick

Telephone:0755-3273333

0755-3273550/8/3/4

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E-mail:[email protected]

© lattice semiconductor corporation verilog training feb. 1998 0 lattice verilog training part i...

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