單元一 工作站環境設定及常用指令.pdf
Post on 16-Nov-2015
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()
Unix/Linux
SpectreRF
()
Unix/Linux Cadence
SpectreRF
()
Unix/Linux
()
PC PC
Windows
Unix Linux
Unix/Linux PC DOS
SpectreRF Cadence
Schematic Layout
()
A. Unix/Linux
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Tools Terminal ( 1-1 )
1-1 Terminal
1-2
Unix/Linux
mkdir( 1-2 work )
cd( DOS )
dir ls
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1-2Terminal
cp( copy )
rm( delete )
mv
chmod
ps
man
kill
Unix/Linux
Unix vi
PC Unix/Linux
Tools Text Editor
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1-3 Text Editor
1-3Text Editor
B. Cadence SpectreRF
mkdir
( work)
Cadence PDK
work user
.cshrc
source /usr/cadence/IC/CIC/ic.csh
source /usr/cadence/IC/CIC/license.csh
source /usr/mentor/cic_setup/calibre.csh
() Cadence Cadence
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Layout
Cadence work
display.drf cds.lib display.drf layout
layout cds.lib
Library
PDK
Cadence work
Cadence
icfb &( 1-4)
1-4
Whats New in 5.xx.xx
1-5 icfb Whats New in 5.xx.xx icfb
FileToolsOptions
Cadence
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Command Interpreter Window (CIW)
1-5icfb
C. Library
1-5 icfb ToolsLibrary
Manager Library Manager ( 1-6)
1-6Library Manager
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1-6 tsmc18rf
LibraryLibrary ManagerFileNewLibrary(
1-7 )
1-7 Library
1-8 New Library
TestLibrary(Unix/Linux
) Name Test
OK( Library LNA_abc
) 1-9 Technology File for New
Library Compile a new techfile OK
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1-8New Library
1-9Technology File for New Library
1-10 Load Technology File
ASCII Technology File techfile (
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) OK
1-10Load Technology File
techfile 1-11 Close
1-11Load Technology File
Library Test Cell
techfile tsmc18rf
Library Cell
SpectreRF
library Layout Library
techfile
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D. Cell View
Test Library Cell View
FileNewCell View( 1-12)
1-12 Cell View
Create New File ( 1-13)
Cell Name 1 OK Cell
LibraryTest
1 Cell View Name schematic Tool
Composer-Schematic Cell Name
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1-13Create New Cell View
1-14 Virtuoso Schematic Editing
Schematic
Save & CheckParametersInstanceLineWire Name
Pin
ToolsDesignWindowEditAddCheck
(Hot-key)
E. Schematic
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1-14Virtuoso Schematic Editing
(
) Pin
Pin Save only
Save & Check Save & Check
Cell Symbol View Save & Check
DesignCreate CellviewFrom Cellview ( 1-15)
Cellview From Cellview ( 1-16)
OK
Pin
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Schematic
Symbol view
1-15 Symbol View
1-16Cellview From Cellview
Symbol Generation Options ( 1-17)
Pin Symbol OK
input output VDDGND
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1-17Symbol Generation Options
1-18 Virtuoso Symbol Editing
Symbol view Pin
Save & Check
Schematic Pin
1-18Virtuoso Symbol Editing
RFIN
Vdd I2 I1
Gnd
RFOut [@partName]
[@instanceName]
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Symbol view schematic instance
Layout Schematic Symbol
Schematic (Test bench) Layout
F. SpectreRF ( DC )
Test bench ( 1-19) I0
Symbol view schematic
1-19Test Bench
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schematic save & check
Virtuoso Schematic Editing
ToolsAnalog Environment ( 1-20)
1-20
SpectreRF
( 1-21)
1-21Analog Design Environment
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SetupModel Libraries Model
1-22 Model Library Setup
Section Model OK
1-22Model Library Setup
1-22 model Model Library Setup
Schematic tsmc18rf
model
Model Library Setup
Analog Design Environment Analyses
Choose ( 1-23)AC, TRAN, DC
Choosing Analyses (
1-24) Choosing Analyses ( DC
) Save DC Operating Point OK
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1-23
1-24Choosing Analyses
Analog Design Environment Netlist and Run
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( 1-25 )
1-25 netlist
1-26
.log
DC Analog Design Environment Results
AnnotateDC Node Voltages ResultsAnnotateDC operating
Points( 1-27)Annotate/DC Node Voltages Schematic
Annotate/DC operating Points
MOS
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1-26
1-27
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G. Layout
CIC Laker Virtuoso-XL
Layout Schematic Tools
Design SynthesisLayout XL( 1-28)
1-28 Layout
1-29 Startup Option Create New
OK Open Existing Layout
1-29Layout Startup Option
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1-30 OK ()
1-30Layout Create New File
1-31 Virtuoso@XL Layout Editing
schematic Layout
ConnectivityUpdateComponents And Nets
1-31Virtuoso XL Layout Editing
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1-32 Layout
1-32Layout Generation Options
Layout GenerationBoundary I/O PinsLayer/Master
(dg) Apply OK
Layout shift + F Layout( 1-33)
Schematic Editing LayoutXL
Schematic Layout
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1-33Virtuoso XL Layout Editing / Schematic Editing
Virtuoso XL Layout Editing Layout
DRC LVS
()