time division multiplexing developed in 1960s for digital transmission of voice calls the audio...
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PLESIOCHRONOUS DIGITAL
HIERARCHY (PDH)EXPLAINED BY
MOHAMED YAMMAN FATTALUNDER THE SUPERVISION OF :ENG.NADA ALKATEEB
Time Division Multiplexing developed in 1960s for
digital transmission of voice calls The audio signals were sampled and converted to
digital signals at 64kbps Each 64 kbps channel is allocated a time slot in a
high speed transmission system capable of carrying multiple 64 kbps streams simultaneously
The early TDM system was called PDH
(Plesiochronous Digital Hierarchy) and was
replaced by a more advanced version called SDH (Synchronous Digital Hierarchy) in late 1980’s
In US–24 voice channels (64 k) gives a DS-1 (1544
kbps)
–4 DS-1 gives a DS-2 (6312 kbps)
–7 DS-2 gives a DS-3 (44736 kbps)
Europe and other countries
–30 -32 voice channels (64 kbps) plus two channels
for framing and signaling gives an E-1 (2048kbps)
–4 x E-1 gives an E-2 (8448 kbps)
–4 x E-2 gives an E-3 (34368 kbps)
–4 x E-3 gives a E-4 (139264 kbps)
PDH (Plesiochronous Digital Hierarchy)European Standards: E1, E2, E3, …
E1:
E1 E2 E3
Rate 2.048Mbps 8.448Mbps 139.264Mbps
If it is necessary to transmit more than 24 channels, the system is build-up as in the “Plesiochronous Digital Hierarchy” as shown
274.176
Mbits/s
TI MUX
T2 MUX
T3 MUX
T4 MUX
64kb/s
1
24 1.544 Mb/s
Four 1.544Mbits/s Inputs
1
4 6.312 Mbits/s
Seven 6.312inputs
1
7
Six 44.736 Mbits/s inputs
1
6
DIGITAL MUX LEVELS IN North America, Europe, Japan
Digital MUX Level
No.of 64Kb/s Channels
North America Mbits/s
Europe Mbits/s
Japan Mbits/s
0 1 0.064 0.064 0.064
1 24 1.544 1.544
30 -32 2.048
48 3.152 3.152
2 96 6.312 6.312
120 8.448
3 480 34.368 32.064
672 44.376
1344 91.053
1440 97.728
4 1920 139.264
4032 274.176
5760 397.200
The 6.312-Mb/s output of a second order (DS2) Multiplexer is created by multiplexing four first order (DS1) multiplexing outputs. This is done by interleaving the bit stream of the four primary systems.
Each individual bit stream is called the “tributary”. The main problem to overcome in this process is the organization
of the four incoming tributaries. Synchronous Digital have tributaries with the same clock
frequency, and they are all synchronized to a master clock. Plesiochronous Digital Multiplexers are have tributaries that
have the same nominal frequency (that means there can be small difference from one to another), but they are not synchronized to each other.
For synchronous case, the pulses in each tributary all rise and fall during the same time interval.
For the PDH, the rise and fall time of the pulses in each tributaries do not coincide with each other.
30 ch2.048 Mb/s
120 ch8.44Mb/s
480 ch34.368
Mb/s
1920 ch139.264
Mb/s
7680 ch564.992Mbit/s
64 kbits/s
x30
x4
x4x4
x4
Europe
PDH Europe
Interleaving There are four bit streams to be multiplexed. One bit is
sequentially taken from each tributary so that the resulting multiplexed bit stream has every fifth bit coming from the same tributary. A specific no. of bits (usually 8), forming a word, are taken from each tributary in turn.
Byte interleaving sets some restraints on the frame structure of the tributaries and require great amount of memory capacity.
Bit interleaving is much simpler because it is independent of frame structure and also requires less memory capacity.
BIT INTERLEAVING
BYTE INTERLEAVING
Positive Pulse stuffing or justification
Pulse stuffing involves intentionally making the output bit rate of a channel higher than the input rate. The output channel therefore contains all the input data plus a variable number of “stuffed bits’ that are not part of the incoming subscriber information.
The stuffed bits are inserted at the specific locations, to pad the input bit stream to the higher output bit rate. This stuffed bits must be identified at the receiving end so that “de-stuffing” can be done to recover the original bit stream.
Pulse stuffing is used for higher order multiplexing when each of the incoming lower order tributary signal is unsynchronized, and therefore bears no prefix phase relationship to any of the other.
The situation is vividly depicted in fig.
Simplified PDH bit interleaving (Stuffing Needed)
- -Higher Order
Multiplexer
1
Frame no.1 Frame no: 2
Lower Bit Rate
Higher Bit Rate
Stuffing Control bit Stuffing
bit is a data bit
Stuffing bit is a stuff bit
•At the receiving end the writing clock has the same characteristics as those of the transmit reading clock. That is, it has a frequency that is on average the same as that of the tributary, but it presents periodic spaces for the frame structure and random spaces for the stuffing process. A phase lock loop (PLL) circuit is used to reduce,•Jitter caused by the frame structure •Higher frequency jitter components (waiting time) caused by stuffing Tributary signal jitterJitter introduced by the 6.312 Mb/s link.
De-stuffing at Receive side
LIMITATIONS IN PDH•Different Standards •Systems operates in its own Clock•Proprietary Coding Mechanisms Making Inter-Operas Ability of System Between Different Vendors•Not Transparent•Protection Schemes are not available•Ring, Hub Configuration not possible•Inability to identify individual channels in a higher-order bit stream•Insufficient capacity for network management•Most PDH network management is proprietary;•There is no standardised definition of PDH bit rates greater than 140 Mbit/s•There are different hierarchies in use around the world. Specialized interface equipment is required to interwork between two hierarchies.
WHY SDH? High Transmission Rates Simplified Add & Drop Function High Availability and Capacity Matching Reliability Future Proof Platform for New Services Interconnection
Reference : Synchronous digital hierarchy By N. Moss page 19 Next generation network services: technologies and
strategies By Neill Wilkinson page 27 Mesh-based survivable networks: options and strategies
for optical, MPLS ... By Wayne D. Grover page 28 Understanding telecommunications networks By A. R.
Valdar, page 78 Microwave radio transmission design guide By Trevor
Manning page 72