© v. angelovikp uni-köln 05.08.2013 1 physikalisches institut uni-heidelberg venelin angelov...

© V. Angelov IKP Uni-Köln 05.08.2013 1

Physikalisches InstitutUNI-Heidelberg

Venelin AngelovElektronikwerkstatt


Digital system design with FPGA

• Logic Box• SUbmodules available• Some Designs

• 7x100 MHz ADC• Dual MALU• TDC

• The new DL711 Logic Box• The new ADC SUBmodule


Logic Box

• Block Diagram

• USB Interface

• User Design

• Top & Contraints Generator

• Design Flow


Block Diagram of DL701/6/9

bytes

ProgramFlash

CWR

4 or 8 SU7xx

DMA_req

CRdy

i/o

16

DMA_Ainc

USBInterface

32

CRD

USBconnector

CDin

CReset

32

CWR

32

Optional

Optional

CReset

FTDI or Cypress

2

. . .

CRdy

CLK

o

Caddr

SU 1

SU 0

JTAG

o

+

+

CDout

CLK

o

CDin

100 MHz

Activity

SU 3|7

o

32

FPGA

DMA_Nwords

RES_n32

o

Top oftheuserdesign DMA_Addr

i

SerProg

USB Controller

DMA_dsize

32

i

RESET

QuartzOscillator

LED_back

DMA_ena

i/o

CDout 32

Caddr

Digital ClockManager (DCM)

i/o

JTAGconnector

CRD

DMA_ack

DL701/6: xc3s400DL709/10: xc3s4000DL711: xc6slx150t


User Design

MS bits of CAddrwrite port

read port

CDin

CDout CWR

MS bits of CAddr

User I/Os


Generate Top and UCF files

gen_lb DL709 -s2 SU704 -s3 SU736 -t ../../SRC/TOP/DL709.vhd -o top.vhd -u top.ucf

specifiy the DL7xx type

specifiy the SU7xx cards

specifiy the template file

specifiy the VHDL output file

specifiy the UCF output file

This program supports now:

DL701, 706, 709, 710, 711

SU701, 702, 703, 704, 706, 707, 709, 710, 711, 712, 713, 714, 715, 717, 720, 721, 722, 724, 725, 726, 727, 728, 730, 731, 733, 734, 736, 737


SUbmodules overviewSU701 TTL I/O 16 channels in two groupsSU702 8 channel 14-bit ADC (MAX1149)SU703 4 channel fast dicriminator with 2xMAX9601 (dual PECL comparator) +

2xMAX537 (4x serial DAC)SU704 5 channel TTL or NIM I/OSU705 4M x 16-bit RAMSU706 100 MS/s 14-bit ADC (ADS5500)SU707 8 channel LVDS I/OSU709 8 temperature sensors SMT160-30 / HY-LINE #16092SU710 2 channel 14-bit DACSU711 DelaySU712 Dual 8 channel 14-bit ADC (MAX1149), like SU720 but without isolationSU713 Dual 8 channel 14-bit DACSU714 ADC ADS5500SU715 2 channel audio preamplifierSU716 16M x 32-bit RAMSU717 Gated integrator with ADS5500SU720 Dual 8 channel 14-bit ADC (MAX1149), like SU712 but with isolation


SUbmodules overviewSU721 Dual 8 channel 14-bit DAC, like SU713 but with isolationSU722 5 channel TTL I/O, like SU700 but with isolationSU724 Toslink interfaceSU725 8 channel ECL inputSU726 32 LEDsSU727 Toslink interfaceSU728 16-bit ADC and DACSU730 PSRAM 8M x 16 bitSU731 4 x H-Bridge, 36V 2ASU733 Optical In/OutSU734 DDS Modul with AD9910SU735 100 MS/s 14-bit ADCSU736 2 channel fast dicriminator with programmable threshold & hysteresis and direct NIM outputs (1xMAX9600 dual ECL comparator + AD5624 4x serial DAC)SU737 Optical Gigabit Ethernet with TLK2201 (SerDes) and SFP Module


7x100 MHz ADC Design7 x 100 MHz 14-bit ADC SUbmodules

1 x 5 TTL/NIM IO Submodule

Multievent buffering:

4 events @ 2048 samples …512 events @ 16 samples

Programmable presample length

USB2.0 InterfaceC, C++ or LabView


TOP BLOCK DIAGRAM

INVTS

3

DIS/INV

BUSY_OUT

1

DISTRG

14

4

EVENT BUFFER

2

ADC SPI

3

TIMESYNC_IN

INVBUSY

7x

TRIGG_IN

SU706

ADC CLK

INVTRG

ADC_CLK_IN

CONTROL

INTERFACETO USB CHIP

USB CHIPFX2 (CYPRESS)

5

ADC_DATA_OUT

0

CONFIGURATION_REGISTER at 0x1000C

SPI

INV

DIS/INV

CBUS

ADCITP

DISTS

ANALOG_IN


ADC CLOCK

0

CLK

Enable

CLK 100 MHz

1

div ratio

7xSYNC

Output DDR

DR

CLK

QDF

CLKn

ENA

ADC CLK 50 MHz

do one DCM phase step when no reset

Discrete phase of theSYNC signal relative tothe ADCCLK

SYNC dPhase=1

2

dPhaseDCM reset when 1

Rst

SYNC dPhase=0

CLK 100 MHz

11..10DCM Phase-255..+255

ADCCLK14

State machine

SU706ADS5500

2

100 MHz

set ratio/dphase when 1

15

dPhase

Note: Set the ratio anddphase again after changingthe DCM phase even if ratioand dphase remainedunchanged!!!

Ratio Freq [MHz] dPhase0 100 01 50 0..12 33 0..23 25 0..3

Ratio

7

Input DFF

D

CLK

Q

ENA

DCMCLK

9..8

14

DCM CLK

7

ADC DATA

ADC Data

UP/DN one step when bit7=1

DCM

RST

CLK

Q

QINC/DEC

CLK


ADC SPI INTERFACE

10..9

15..12

1101

SPI DATA

0 - normal1 - all 02 - all 13 - test pattern

Write to ADC_SPI+8 anything to reset all ADCs.Recommended before setting the ADCs.

1

PD

15..12

0

0

15..12

0..0

11

0..0 DLL

0

0

0 - DLL on (for 100 MHz)1 - DLL off (for < 60 MHz)

0..0

TP1110

1111

Write to ADC_SPI+Channel the 16-bit SPIData word for the corresponding function inADC[Channel]

0

In test pattern mode the ADCs send1010...100101...01(the bits toggle after each ADC clock)

This is useful for adjusting thetiming in the data transfer.

0 - normal1 - power down


ADC CLOCK ADJUST 100 MHz

0

100000

200000

300000

400000

500000

600000

700000

800000

900000

1e+006

-200 -100 0 100 200 300

Bit e

rro

rs f

or

40

96

syste

m c

locks

DCM delay

100 MHz, dphase 0, dll 1

0123456


ADC DATA PATHAIN

clear &start

00

AIN

9..2 bits

DUAL PORT RAM

4..11 bits

ch=0..6

err counter 0

sample+1

Addr (relative to the BA_EV_BUFFER)

err counter 2

sample

test patternchecker

even

EVENT_SIZE_REGISTER at 0x1000D

00

0

odd

1

Address Counter AIN, AOUT

err counter 3

even/odd memoryselect

err counter 1

WE_e

2

busy

REG

32

0

WE_o

Data

31

31

Counter

13..4

REGAOUT_e

0

Bit 3 inCOMMAND_REGISTER at0x1000B

MUX

AOUT_o

EVENT

14

TestPatternGenerator

SAMPLE

327x14

ADC[ch]

ch2..0

Addr=0x10 (relative to theBA_EV_BUFFER)

Addr

Bit 5 inCONFIGURATION_REGISTERat 0x1000C

SIM_MODE

13 bits

SWAP

. . .


EVENT DATA FORMAT

r0

sample 1

00

30

r1

Event Id

00

r6

20

ch=r3

r5

00

adc6..0

. . .

The unused ADCs are automatically turned off,the active ADCs can be read back

sample 3

0

ch=r1

00

4

24

sample 0

31

00

ch=r0

RDCLR

sample 0

sample 2

sample 0

READ_ORDER_REGISTERat 0x1000F

sample 1

1. i=02. Send r[i]3. i=i+14. if r[i]=7 or i=7 exit else goto 2

2

sample 0

r2

sample 0

Event Buffer Clear

Readout order

sample 1

evsize

Software Trigger

sample 1

0

. . .

ch=r0

r3

Test Pattern Check(toggle bits)

SFTTRG

31

Ev. in Buffer

EVENT_SIZE_REGISTERat 0x1000D

Read StateMachine Clear

00

adc_maskread-only

00

Timestamp with 10 ns resolution

sample 10

3

r4

EBCLR

ch=r<n-1>

00

00

1. Clear the event buffer at the beginningand after setting the event size! Allevents stored are lost!2. Clear the read state machine in case ofunexpected data from the event buffer - noevents are lost!

ch=r2

TPCHK

Time Stamp Clear

0 161 322 643 1284 2565 5126 10247 2048

00

00

00

TSCLR

COMMAND_REGISTER at 0x1000B


OPERATION

Presamples: 10 bit register at 0x1000E,automatically wrapped to ensure thetrigger is inside the event.Start value 8

Presamples

0 16 5121 32 2562 64 1283 128 644 256 325 512 166 1024 87 2048 4

ADC

Event size

event stored

Busy

Trigger

EventSize Number of Number of EventsRegister Samples in the Buffer


Dual MALU• 32 inputs, NIM or TTL (selectable at each input)• Two logical groups consisting of user programmable subset of the 32 inputs• In each group:

• Delay gate generators at each input (100 MHz)• Four outputs

• 3 of them just discriminators with programmable thresholds• one implemented as pattern checker

• Counters at each input and output for debugging


Block Diagram

TTLDIS3R

EDGE_C

SOFT_P

DIS1..4L

DELAYS

NIMDIS4R

32

0

DIS1..4R

5

DOWNSCALE

INP_DIS_R

DIS3L

32

31

4

32

WIDTH

INP_DIS_L

DIS4L

32

CNT_CTRL

DIS1..4L

32

OR_MASK

DIS1L

32

31

4

DATA

THRESHOLDS

DIS2L

32

TMAX

INPUTS

DATA

DISCR1

DISCR3

INP_NIM

TTL

x

OUTPUTS

USB Controller

DISCR2

DISCR4

CT

ADDR

Configuration

32 counters

DISCR2

CC

ADDR

Count

DISCR1

DISCR3

E

3Count

DOWNSCALE DISCR4

CT - clear timer, CC - clear counters, E - enableNote: clear commands are automaticallydeactivated after 1 clock period

IN

WIDTHDELAYS

max time for counting in 10 ns steps, write 0 for continuous

8 x SU704 IN

OR_MASK

8 counters

0

EDGE_R

INP_SHAPER

THRESHOLDS

4

ICNT0..31

EDGE_L

DIS1R

MALU

4

DCNT 1..4R, 1..4L

INP_INV

DIS2R

INP_DIS_CMALU

DIS1..4R

NIM


Input edge detection and mask32 channels, i=0..31

Disable the channel in the left group when 1

EDGE_C[i]

INP_NIM

AND2

EDGE_R[i]

1Input DFF

D

CLK

Q

Send a pulse by software (writing 1 to the corresponding bit(s) in this register)

0

0

SOFT_P

31

AND2

MUXTTL[i]

31

NIM[i]

INP_DIS_R

D

CLK

Q

Note: this is not exactly the real design

0

D

CLK

Q

0

SOFT_P[i]

Disable the channel in the counter group when 1

EDGE_I[i]

Input DFF

D

CLK

Q

31

INP_NIM[i]

used for the fron LEDs

INP_DIS_L

D

CLK

Q

right group

0

INP_INV[i]

left group

31

AND2

INP_DIS_R[i]

counters

INP_DIS_C

INP_DIS_L[i]

AND2

0

INP_DIS_C[i]

Note the bits in SOFT_P are automatically cleared 1 clock period after activating

XOR2

0

Invert input when 1INP_INV

OR2

EDGE_L[i]

Select the NIM input when 1

31

Disable the channel in the right group when 1

31

D

CLK

Q


DGG, Discriminator & Pattern Cheker

DISCR1

DOWNSC2

DELAY[4*n+3]

WIDTH[7..0]

WIDTH_R

THRESH2[4..0]

DWNSC3T_L/RDELAY[4*n+2]

DG3

32 x

31

COMPARATOR 2

0

DELAY[4*n+1]

DISCR2

IN2

modulo

0

THRESH3[4..0]

15

DELAY[4*n]

DG2

modulo

WIDTH_L

COMPARATOR 3

PATT_TRGn=0..7

Pattern Checker

DISCR3

modulo

ORMASKL

DOWN COUNTER 1

DOWNSC3

PULSER_R/L

MUX

DELAY

RESERVED

AND2

=0

16

1

WIDTH

IN[31..0] =0

31

0

AND2

SUM

DOWN COUNTER 2

THRESH3

OR_MASK2

uses ch0..24 only,see p.4

AND2

IN1

DOWNSC2[15..0]

THRESH2

OR_MASK1

DWNSC12_L/R

DG

=0

THRESH1

DISCR3

DISCR1

0

16

DG1

DOWN COUNTER 3

PATT_TRG

OR_MASK4

DISCR2

15

DELAY4*n..4n+3

IN3

DOWNSC3[15..0]

ORMASKR

AND2

6

OR_MASK3

16

15

SUM

32

DISCR4

16

THRESH1[4..0]

31

31

Delay-GateGenerators

PWIDTH

DOWNSC1[15..0]

DOWNSC1

0

OR4

DELAY[7..0]

15

COMPARATOR 1


Pattern Cheker

10

15

20

9

14

19

AND any of

24

25 Terms

then OR all togetherPattern Checker

0 1 32 4

5


TDC

Based on DL709 + 2 x SU704 (5xNIM/TTL)- 7 channels (start 0..6) and stop, TTL/NIM- 2.5 ns resolution- Event builder with timestamp- Multievent buffering- USB2.0 readout, C, C++ or LabView (Windows)


DL711

As DL709 +- Spartan 6 FPGA XC6SLX150t with SerDes- Two SFPs- DRAM- SDCARD slot- Interface (now USB2.0) as mezzanine card- 8 slots for SUbmodule Cards


SU735

Clock In

LatticeXO2 FPGAwith bootflash

SE/DIff IN toDiff OUT

very cleanclock

Data Out

I2C

A

SPI

LVDS orLVCMOS

LTC2261 orcompatible

D

LVDS orLVCMOS

diff CLK

I2C

ClockCleanerSi5338


SU735 Prototype


SU735 Ver1


EW @ PI UNI-HD (2009)


EW @ PI UNI-HD (2013)


Thank You

© v. angelovikp uni-köln 05.08.2013 1 physikalisches institut uni-heidelberg venelin angelov...

Documents

angelovikp unikln

adc clock slide

adc design

isolation slide

adc submodules

adc spi interface slide

new adc submodule slide

xc6slx150t slide