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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
LEARNER NAME ASSESSOR NAME
N. Hodgson
DATE ISSUED HAND IN DATE SUBMITTED ON
Criteria Achieved
Feedback
P2 (part) - Explain the operation of two different types of transistor, one in an analogue and one in a digital circuitP5 - Build and test a combinational logic circuit that has three input variablesP6 - build and test a sequential circuit using integrated circuit(s)P8 - use a computer software package to simulate the construction and testing of a digital logic circuit with three gates.M2 - modify a digital circuit to achieve a given revised specification by selecting and changing up to two logic gatesM3 - Evaluate and minimise a three input combinational logic circuit containing three gates.
This brief has been verified as fit for purpose
Internal Verifier ANTHONY SPICER
Signature A J Spicer Date
27/07/2012
Our Lady & St John Catholic College Engineering 1
UNIT 35 – Principles and Applications of Electronic Devices and Circuits (K/600/0300)
ASSIGNMENT FIVE – ROCKET LAUNCHER
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
Assessor's commentsQualification Edexcel Lev 3 National Diploma in
EngineeringAssessor name N. Hodgson
Unit number and titleUnit 35 – Principles and Applications of Electronic Devices and Circuits (K/600/0300)
Learner name
Assignment title ASSIGNMENT FIVE – ROCKET LAUNCHER
Grading criteria Achieved?
P2 (part) - Explain the operation of two different types of transistor, one in an analogue and one in a digital circuitP5 - Build and test a combinational logic circuit that has three input variables
P6 - build and test a sequential circuit using integrated circuit(s)
P8 - use a computer software package to simulate the construction and testing of a digital logic circuit with three gates.M2 - modify a digital circuit to achieve a given revised specification by selecting and changing up to two logic gatesM3 - Evaluate and minimise a three input combinational logic circuit containing three gates.
Learner feedback
Assessor feedback
Action plan
Assessor signature Date
Learner signature Date
Our Lady & St John Catholic College Engineering 2
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
Our Lady & St John Catholic College Engineering 3
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
Our Lady & St John Catholic College Engineering 4
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
Our Lady & St John Catholic College Engineering 5
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
Our Lady & St John Catholic College Engineering 6
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
Our Lady & St John Catholic College Engineering 7
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
Our Lady & St John Catholic College Engineering 8
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
Our Lady & St John Catholic College Engineering 9
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
Our Lady & St John Catholic College Engineering 10
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
Our Lady & St John Catholic College Engineering 12
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
Our Lady & St John Catholic College Engineering 16
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
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BTEC NATIONAL EXT DIPLOMA IN ENGINEERING
M3 Evaluate and minimise a three input combinational logic circuit containing three gates.
A Petrol Station has three tanks for fuel storage. A level sensor in each tank produces a HIGH voltage when the level of the fuel in the tank drops below a specified point. The circuit drawn in fig 1 below helps to monitor the fuel level in each tank and indicates when the level in any two of the tanks drops below the specified point.
Tank Level Sensor Logic Circuit
(a) Evaluate all stages of this circuit using appropriate logic statements and logic equations to give full Boolean expressions for all output states.
(b) Develop a truth table to verify the results obtained in (a) above.
(c) Translate the truth table into a Karnaugh Map and use this to show how each of the output states was minimised
Our Lady & St John Catholic College Engineering 20