0.025 mj/image fast-scan and snr enhanced electrical … · 2017-12-18 · 922 jaehyuk lee et al :...

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.6, DECEMBER, 2017 ISSN(Print) 1598-1657 https://doi.org/10.5573/JSTS.2017.17.6.920 ISSN(Online) 2233-4866

Manuscript received Nov. 12, 2017; accepted Nov. 20, 2017 Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST) E-mail : [email protected]

0.025 mJ/image Fast-scan and SNR Enhanced Electrical Impedance Tomography IC for Lung Ventilation

Monitoring

Jaehyuk Lee, Unsoo Ha, and Hoi-Jun Yoo

Abstract—Energy efficient lung monitoring electrical impedance tomography (EIT) IC is simulated in 180-nm CMOS process. To increase the speed of impedance sensing, fast settling high pass filter (FS-HPF) and fast settling low pass filter (FS-LPF) is proposed to reduce the settling time which takes over 90% of entire EIT data measurement latency. In FS-LPF, voltage-controlled pseudo-resistor is proposed to realize time-varying resistance. To reconstruct the accurate images, adaptive current control (ACC) scheme is implemented for SNR enhancement. Additional SNR improvements are accomplished by averaging the multiple measurements. As a result, image scanning speed of 30-fps is achieved with 0.025 mJ/Image energy efficiency. The simulation results show that ACC can reduce the image FOM error over 80% rather than conventional constant current injection method. Index Terms—Electrical impedance tomography, fast settling filter, voltage-controlled pseudo-resistor, adaptive current control

I. INTRODUCTION

Annually, over 50 million patients are mechanically ventilated. Among them, 5.7 million patients develop acute lung injury (ALI) which has over 38.5% high

mortality [1]. Mechanical ventilation can initiate the lung injury and contribute to patient morbidity and mortality [2]. It has been shown that inappropriate ventilator settings which do not suit the individual patients can lead the injury of lung tissues. Furthermore, it is still controversial and challenging to find the optimal ventilator parameters such as PEEP (Positive End-Expiratory Period) and tidal volume settings for individual patient [3]. Therefore, the lung ventilation monitoring (LVM) technology is highly required which can facilitate the optimal ventilation treatment.

Among the several LVM technologies, Electrical Impedance Tomography (EIT) is spotlighted as the emerging lung monitoring system since it is the only imaging technology available in the bedside with real-time images. Rather than existing imaging technologies (CT, MRI, X-ray, etc.), it has high temporal resolution with low power consumption, less hardware complexity and dependency on the measurement environment.

Fig. 1 shows the concept of LVM EIT system and its requirements. EIT can generate the internal conductivity map using the surface measurement. By injecting current and sensing voltage, several impedance data pattern is gathered. For the LVM application, EIT system should satisfy two requirements, 30-fps real-time operation [6] and 30-40 dB SNR [7] which is proven to detect the lung impedance changes.

Previously, two EIT SoCs [4, 5] were proposed for LVM. The main contribution of [4] is minimized form-factor rather than previous commercial EIT system [6]. However, it represents the limited scan speed up to 3.3-fps for a single channel receiver. In [5], the proposed

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.6, DECEMBER, 2017 921

receiver architecture can measure the different frequency component information simultaneously. However, since the digital domain performs the demodulation process directly, high ADC sampling rates, complex digital multipliers and filters are required to achieve 30-fps real-time impedance data. Furthermore, in the in-vivo situation, [4, 5] shows 28.5-dB SNR degradation due to the large size of human thorax in the worst case.

In this paper, we present a fast-scan SNR enhanced EIT IC [8] which can effectively increase the speed of data measurement and adaptively compensate the SNR. The fast-scan voltage sensor architecture is proposed. It has fast settling high pass filter (FS-HPF) and low pass filter (FS-LPF) which can reduce settling time by 93.2% and 91.8% compared to conventional passive HPF and LPF. Adaptive current control (ACC) scheme is employed to enhance the SNR. It has the current controllability for each individual electrode pairs.

The rest of this paper is organized as follows. In Section II, the architecture of the proposed EIT IC is described. Section III discusses the detailed implementation of the key building blocks, 1) fast-scan voltage sensor and 2) SNR enhanced current injector. Section IV shows the implementation and image simulation results using the EIDORS software [9] with GREIT algorithm [10]. Finally, Section V concludes the paper.

II. BACKGROUND AND ARCHITECTURE OF

PROPOSED IC

1. Characteristics of EIT Measurement System In Fig. 2(a), the conventional down conversion

receiver of EIT is shown. The purpose of this architecture is the demodulation of modulated voltage. Through the medium, the current is converted to the voltage containing the impedance information. Since the electrode-tissue interface generates the DC offset voltage, the receiver should contain the high pass filter (HPF). After amplification and demodulation, the low pass filter (LPF) rejects the harmonic ripple components.

Because both HPF and LPF require the large time constant, low scanning speed is an unavoidable problem due to its long settling time. These large time constant filters occupy 99.8% of entire data measurement duration in the condition of 1% settling error for 1st order passive HPF and -80-dB rejection for 2nd order passive LPF. In other words, filters are the most time-consuming blocks in the EIT system and it should be mainly focused to improve the scanning speed.

Fig. 2(b) shows the in-vivo measurement results of previous EIT system [4, 5]. Nearby electrodes from the current injector show high current density rather than the far-sensing electrodes. Thus, the worst-case SNR at the

Fig. 1. A concept diagram of proposed LVM EIT system and its requirement.

(a)

(b)

Fig. 2. Characteristics of conventional EIT measurement system (a) Down conversion receiver structure and timing diagram of single impedance data measurement, (b) In-vivo measurement results of previous EIT system.

922 JAEHYUK LEE et al : 0.025 mJ/IMAGE FAST-SCAN AND SNR ENHANCED ELECTRICAL IMPEDANCE TOMOGRAPHY IC …

far-sensing electrodes degrade the image quality. In this measurement, the worst-case SNR was 28.5-dB, and it is required to have about 10-dB SNR improvement.

2. Overall Architecture of Proposed EIT IC

Fig. 3 shows the overall block diagram including

current injector, voltage sensor and digital controller. For the voltage sensor, fast settling high-pass filter (FS-HPF) and fast settling low-pass filter (FS-LPF) are employed to increase the measurement speed. For the current injector, adaptive current control (ACC) scheme is utilized for the SNR enhancement. RISC controller manages the entire operation of EIT IC. Using the UART serial interface, the measured impedance data is transferred to the host imaging device which performs the image reconstruction.

III. KEY BUILDING BLOCKS

1. Fast-scan Voltage Sensor with FS-HPF and FS-LPF FS-HPF and FS-LPF are key building blocks in the

fast-scan voltage sensor. They effectively reduces the settling time using the time-varying components in the transition period. The basic principle of filters is represented as Fig. 4. When the electrodes are switched, the abrupt DC offset voltage differences (∆VDC) are generated in front of HPF. Therefore, the huge settling time is necessarily required for avoiding the saturation of IA. FS-HPF is composed of 1st order passive HPF and a

switch (Φ1). In the transition period, the switch turns on for 0.5T. Since the phase information of current is known, the switch is turned off at the zero-crossing point of injection sinusoidal for minimizing the settling time. FS-HPF needs only 0.5T of current sinusoidal for settlement. When the 10-kHz carrier frequency is used, 50-µs settling time is required. The settling time of FS-HPF is reduced by 93.2% rather than the one of conventional HPF.

FS-LPF consists of variable resistor and capacitor. In the transition period, variable resistor changes the cut-off frequency from the high to low. The output signal follows the input signal with reduced settling time at first (fast settlement phase), and the ripple is reduced due to exponentially increasing resistance (ripple attenuation phase).

The schematic of FS-LPF is represented in Fig. 5. The 2nd order passive low pass filter structure is utilized for the sufficient ripple rejection. We proposed the voltage-controlled pseudo-resistor (VCPR) for implementing the large variable resistance with high area efficiency. By changing the gate-drain voltage (VGD), the VCPR resistance value varies as exponential function. Ensuring the resistance value is independent to the input signal, V-

GD generation circuit is implemented with switched-capacitor circuit. The clock Φ1 and Φ2 is non-overlapping clock which has 100-times larger frequency than that of the carrier signal. Drain voltage is sampled to the CP, and VGD=Vlin-Vref can be applied without affecting the signal path. Vlin is generated by current source and the charging capacitor. The slope of linear

SNR Enhanced Current Injector Digital Ctrlr.

Data Acq.Control

DataBuffer

ElectrodeSwitching

Control

UART/SPIInterface

8'b CurrentSteering DAC

ReferenceCurrent

Generator

10'bSARADC

IA

IA

FS-HPF FS-LPF

Fast-scan Voltage Sensor

15-42dB

ICLK

QCLK

~200kSPS

ACC Current &Averaging

Control

Pull-UP

Stage

Pull-DN

Stage

Switching N

etwork

32

31

2

1

Fig. 3. An overall block diagram of proposed EIT IC.

HPF

HPF

IA

ɸ1 ΔVDC

Generation

ɸ1

VIN

VIN VOUT

0.5T(Period)

Body

VDC1=100mV

VDC2=200mV

VDC3=100mV

HPF

HPF

IA

At Swithcing

ΔVDC1

ΔVDC2

RVCPR

VIN VOUT

Increasing RVCPR

Filter Transient Waveform

② Ripple Attenuation

① Fast Settlement

② ① Frequency

Fast Settling High-Pass Filter (FS-HPF)

Fast Settling Low-Pass Filter (FS-LPF)

Fig. 4. Operation principles of fast settling filters.


increasing voltage depends on the SLOPE [1:0]. The duty control switch is also inserted for covering the 10-kHz to 100-kHz operation carrier frequency range.

As shown in Fig. 5, the VCPR resistance value can be fluctuated due to the process variation. In FS-LPF, SLOPE [1:0] and CBANK [3:0] can be utilized for the PVT compensation. Since the pseudo-resistor has the weak properties for PVT variation, we find the optimal parameter minimizing the variation before the measurement. In the voltage sensor architecture, the auxiliary calibration circuit is employed as Fig. 6. With the on-chip test resistor and current injection, the test input sinusoidal can be applied to the mixer and FS-LPF. By sweeping the SLOPE [1:0] and CBANK [3:0] parameters, the optimal parameters are determined to minimize the error. Since we know the input amplitude and ideal relationship of mixer and FS-LPF, the error can be calculated in the parameter decision FSM.

In Fig. 6, the compensation result of calibration process is described. By changing the input amplitude (0 ~ 1Vpp) and 3 process corners (SS, TT, FF), we calculated the DC error and 2f ripple components (f is the carrier frequency). Since the purpose of FS-LPF is finding the average value and rejecting the harmonic components, the DC error is derived by differencing the ideal value and simulated value, and 2f ripple components are calculated by performing FFT of output signal. After finding the optimal SLOPE [1:0], and CBANK [3:0] for each process corners, the total error is less than the half of LSB of 10’b ADC (0.679-mV). The total error is assumed as the sum of DC error and 2f

ripple components. In this simulation, we only covered 3 corners since VCPR is only composed of PMOS.

Simulation results of FS-LPF are represented in Fig. 7. In the transient waveform, the filter needs only 3 period of current sinusoidal for convergence. When the longest measurement case (10-kHz carrier frequency), the FS-LPF only requires 300-µs, which is reduced by 91.8% rather than conventional 2nd order LPF satisfying the error requirements (< LSB/2). Compare to the ideal input and output relationship (π/2) of down conversion mixer and LPF, the proposed FS-LPF represents high linearity until the input amplitude is less than the 1Vpp.

Huge settling time reduction is achieved by utilizing time-varying components such as zero-crossing switch and VCPR. In the EIT system, since we always know the exact time of electrode switching, this prior knowledge utilized to control these time-varying components properly. In the 10-kHz carrier frequency, total

Fig. 5. A schematic of FS-LPF with simulation results.

Fig. 6. An on-chip calibration circuit and a compensation result of FS-LPF.

(a) (b)

Fig. 7. Simulation results of FS-LPF (a) a transient waveform,(b) a input output relationship of down conversion mixer with FS-LPF.


measurement time is reduced by 91.9% using the fast settling filters.

2. SNR Enhanced Current Injector with ACC

The worst-case SNR degrades the entire image since

the image reconstruction is performed by solving the inverse problem that has the limited constraints. To overcome this problem, we primarily increase the injection current level and perform the multiple measurement for averaging the data samples for enhancing the worst-case SNR.

In Fig. 8, the concept of ACC is described. The first step is increasing the current level when we sense the far electrodes. Since the current level should be limited by safety issue, the maximum allowable current level is decided to 4-mA. The 3.3-V high supply voltage is used for the output stage of current injector, and the current capability is improved rather than previous works [4, 5]. The second step is averaging the multiple measurements. When we consider the SNR of the impedance data, the main noise source is the random noise of amplifier. Thus, the averaging method can improve the SNR √N times when N is the number of repeated measurements.

Every current injection and voltage sensing are processed by two adjacent electrode pair. In the 32 electrode EIT system, there are 29 voltage measurements (1 sub-frame) when the current injection pair is fixed. One frame of image consists of 928 (32 sub-frames) impedance data. For the one sub-frame, the current level and the oversampled number are decided by the FSM of ACC. After deciding the measurement settings, full-frame measurement is performed. Because of each sub-frame has the similar voltage distributions, the same

measurement settings are applied for every sub-frames.

IV. SIMULATION RESULTS & LAYOUT

1. Image Reconstruction Simulation and Image FOM Comparison

The proposed ACC scheme is verified with the

simulation. Except the analog circuits, ACC algorithm is only verified with EIDORS software [9]. In Fig. 9, the image reconstruction results are represented. Using GREIT algorithm [10], the input conductivity distribution model is converted to the voltage measurement at surface electrode using forward problem. After adding the random noise to the surface voltage, the image reconstruction is performed by solving the inverse problem. In the presence of same noise level (80-µVRMS, 40-µVRMS, 20-µVRMS), ACC can improves the minimum SNR larger than 30-dB and image artifacts are clearly rejected.

To clarify the improvements of ACC, the image FOM simulation is performed in Fig. 10. We defined two different image FOM for comparison the conventional current injection and ACC. Center of mass (COM) error is calculated by the difference of input model COM radius and output image COM radius. It should be small

(a) (b)

Fig. 8. A two-step SNR enhancement (a) operation principle,(b) ACC FSM flow chart.

Con

vent

iona

lPr

opos

ed

Fig. 9. A test input model and result images from EIDORS software.

Fig. 10. Image FOM simulation results.


as possible for accurate position detection. The second FOM is blur radius. After thresholding each pixels by 25% maximum impedance value, the area fraction of the entire model could be derived. From this fraction, we performed square root calculation for converting to the length dimension, blur radius. It should be good result, if the blur radius is close to the model radius.

Compare to the conventional constant current injection method, COM mean error is reduced by 86.4% and the standard deviation is reduced by 56.3%. Blur radius mean error is reduced by 96.9%. Since ACC improves the worst-case SNR, high improvements are achieved in the FOM simulation.

2. Chip Simulation Results

In Fig. 11, chip layout photography and summary is

represented. Proposed EIT IC is implemented with 0.18-µm CMOS process. 3.3-V supply domain is only utilized for the output stage of current injector, and 1.5-V for remain sub-blocks. The power consumption depends on the injection current level. When we consider the voltage sensor and RISC controller, the power consumption is less than 1-mW. The operation carrier frequency is 10-kHz to 200-kHz.

In Fig. 12, the comparison table is described. Among them, proposed work shows the fastest scanning speed achieving 30-fps operation with only single sensor channel at 100-kHz carrier frequency. Rather than other works, the current injection level can be manipulated, and the function of averaging multiple impedance data is supported for improving the SNR. SNR enhancement

functionality and performance improvement is verified using the FOM simulation. The proposed EIT IC accomplished 0.025-mJ/Image energy efficiency due to the increased scanning speed. By minimizing the settling time of large time constant filters, the wasting power of current injector can be hugely relieved.

V. CONCLUSIONS

In this paper, lung monitoring EIT IC with settling time reduction and SNR improvement is proposed. Using the FS-HPF, FS-LPF, the time consumption of single measurement is reduced by 91.9% which can be available single-channel 30-fps operation. Thanks to the fast measurement speed, 0.025-mJ/Image energy efficiency is accomplished. ACC can recognize the voltage distributions, and adaptively decide the current level and oversampling number for enhancing the SNR of far-sensing electrodes. From the image simulation, SNR is compensated over 30-dB. It shows 86.4% COM mean error and 96.9% blur radius mean error reduction compare to conventional constant current method.

ACKNOWLEDGMENTS

This work was supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIT) (No.2016-0-00207, Intelligent Processor Architectures and Application Softwares for CNN (Convolutional Neural Network)-RNN (Recurrent Neural Network))

Fig. 11. Layout photography and summary.

Fig. 12. Performance comparison table.


REFERENCES

[1] Tremblay, Lorraine N., and Arthur S. Slutsky, "Ventilator-induced lung injury: from the bench to the bedside," Intensive care medicine, vol. 32, no. 1, pp. 24-33, Jan. 2006

[2] Rubenfeld, Gordon D., et al., "Incidence and outcomes of acute lung injury," N. Engl. J. Med., vol. 353, no. 16, pp. 1685-1693, Oct. 2005

[3] Gentile MA, Cheifetz IM., “Optimal positive end-expiratory pressure: The search for the Holy Grail continues,” Crit. Care Med., vol. 32, no. 12, pp. 2553-2554, Dec. 2004

[4] S. Hong, et al., “A 10.4 mW Electrical Impedance Tomography SoC for Portable Real-Time Lung Ventilation Monitoring System,” IEEE J. Solid-State Circuits, vol. 50, no. 11, Nov. 2015

[5] Y. Lee, et al., "A 4.84mW 30fps dual frequency division multiplexing electrical impedance tomography SoC for lung ventilation monitoring system," in Proc. of VLSI Circuits, Kyoto, 2015, pp. C204-C205.

[6] G. K. Wolf et al., “Mechanical ventilation guided by electrical impedance tomography in experi- mental acute lung injury,” Crit. Care Med., vol. 41, pp. 1296–1304, May 2013.

[7] J. Lee, et al., "30-fps SNR equalized electrical impedance tomography IC with fast-settle filter and adaptive current control for lung monitoring," in proc. of ISCAS, Montreal, 2016, pp. 109-112.

[8] Andy Adler, William R B Lionheart, "Uses and abuses of EIDORS: An extensible software base for EIT," Physiol. Meas., vol. 27, no. 5, pp. S25-S42, Apr. 2006

[9] Andy Adler, et al., "GREIT: a unified approach to 2D linear EIT reconstruction of lung images," Physiol. Meas., vol. 30, no. 6, pp. S35-S55, Jun. 2009

[10] H. Wi, et al., "Multi-Frequency Electrical Impedance Tomography System With Automatic Self-Calibration for Long-Term Monitoring," in IEEE Trans. Biomed. Circuits and Systems, vol. 8, no. 1, pp. 119-128, Feb. 2014.

Jaehyuk Lee received the B.S. and M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2014 and 2016, where he is currently working toward the Ph.D. degree. His current

research interests include biomedical system design and

verification, especially focused on electrical impedance tomography and biosignal sensor. He is also interested in body-channel communication for low-power wireless body area network (WBAN).

Unsoo Ha received the B.S. (summa cumlaude) degree from the School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 2012, where he is currently pursuing the Ph.D. degree. His

current research interests include biomedical system-on-chip design especially with a focus on multimodal brain monitoring system and designing bio-signal sensor front end for low-power application.

Hoi-Jun Yoo graduated from the Electronic Department of Seoul National University, Seoul, Korea, in 1983 and received the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST),

Daejeon, in 1985 and 1988, respectively. Since 1998, he has been the faculty of the Department of Electrical Engineering at KAIST and now is a full professor. From 2001 to 2005, he was the director of Korean System Integration and IP Authoring Research Center (SIPAC). From 2003 to 2005, he was the full time Advisor to Minister of Korea Ministry of Information and Communication and National Project Manager for SoC and Computer. In 2007, he founded System Design Innovation & Application Research Center (SDIA) at KAIST. Since 2010, he has served the general chair of Korean Institute of Next Generation Computing. His current interests are computer vision SoC, body area networks, biomedical devices and circuits. He is a co-author of DRAM Design (Korea: Hongrung, 1996), High Performance DRAM (Korea: Sigma, 1999), Future Memory: FRAM (Korea: Sigma, 2000), Networks on Chips (Morgan Kaufmann, 2006), Low-Power NoC for High-Performance SoC Design (CRC Press, 2008), Circuits at the Nanoscale (CRC Press, 2009), Embedded Memories for Nano-Scale VLSIs (Springer, 2009), Mobile 3D Graphics SoC from Algorithm to Chip (Wiley, 2010), Bio-Medical CMOS ICs (Springer, 2011), Embedded Systems (Wiley, 2012), and Ultra-Low-Power Short-Range Radios (Springer, 2015).

0.025 mj/image fast-scan and snr enhanced electrical … · 2017-12-18 · 922 jaehyuk lee et al :...

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