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A Single Clock Cycle MIPS RISC Processor Design usingVHDLMamun Bin Ibne Reaz, MEEE,Md. Shabiul Islam,MEEE, Mohd. S. Sulaiman, MEEE

Faculty of Engineering, M ultimedia University, 63 100Cy be jay a, Selangor, Malaysia

Abstract This paper describes a designmethodology of a single clock cycle MIPSRISC Processor using VHDL to ease thedescription, verification, simulation andhardwa re realization. Th e RISC processor hasfixed-length of 32-hit instructions based onthre e different form at R-format, I-format andJ-format, a nd 32-bit general-purpose registerswith memory word of 32-hit. Th e MIPSprocessor is separated into five stages:instruction fetch, instruction decode,execution, data memory and write back. Thecontrol unit controls th e operations performedin these stages. Al l the modules in the designar e coded in VHDL, as it is very useful toolwith its concept of concurrency to cope withthe parallelism of digital hardware. The top-level module connects all the stages into ahigher level. Once detecting the particularapproaches for input, output, main block Pnddifferent modules, the VHDL descriptions arerun through a VHDL simulator, followed bythe timing analysis for the validation,functionali ty and performance of th edesignated design t ha t dem onstrate theeffectiveness of the design.

1. INTRODUCTIONIncreasing performance and gate capacity ofrecent FPGA devices permits complex logicsystems to be implemented on a singleprogrammable device. Such a growingcomplexity demands design approaches, whichcan cope with designs containing hundreds ofthousands of logic gates, memories, high-speedinterfaces, and other high-performancecomponents. One category of such designapproaches are design methodologies based onlanguage VHDL. It allow designers to develophardware systems at high level [l].RISC or Reduced Instruction Set Computer isa design philosophy that become mainstream inthe last few years, as the qu est for raw speed hasdominated the highly competitive computerindustry. There is a desire to enhance theprocessor's speed and simplify the hardware for

reasons of cost. RISC design resulted incomputers that execute instructions faster thanother computers built of the same technology [2].In a RISC machine, the instruction set is basedupon a loadlstore approach. Only load and storeinstructions access memory. No arithmetic, logicor U 0 instruction operates directly on memorycontents. This is the key to single-cycleexecution of instructions. The simplificationresults in an instruction decoder that is small, fastand relatively easy to design [2]. Due to therobust performance, simple instruction formats,breadth of products and depth of support, theMIPS RISC processor architecture becomes themarket leader in high performance em bedded 32-bit and @-bit RlSC processors [3].In this paper we present a design study of asingle clock cycle MIPS RISC processor usingVHDL. The goal of this work was to evaluate thefeasibility of using VHDL for rapid design andprototyping of microprocessors. The use ofVHDL for modeling is especially a ppealin g sinceit provides a formal descrip tion of the system andallows the use of specific description styles tocover the different abstraction levels(architectural, register transfer and logic level)employed in the design [4].

11. MATERIALS NDMETHODSThe architecture of the MIPS RISC processoris designed based on three MIPS 32-bitinstruction formats R-format, I-format and J-format illustrated in Tab. I. The design of thisproject consists of 32-bit instructions and 32-bitdatapath.

Tab. I MIPS 32-bit Instruction Formats.The implementation of RlSC performs fetch,decode, and execute in one clock cycle. Thesingle clock cycle MIPS RISC architecture isseparated into five stages: instruction fetch,instruction decode, execute, data memory andwrite back.0-7803-7578-S/02/S17.00 02002 IEEE

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the input Addresult from the ALU unit fed intothe PC as the next target address else the normalincremented PC replace the current.

Instruction Fetch StageTh e first stage of a MIPS RISC is instructionfetch (IF) stage. The IF stage obtain therequested instruction from memory. Theoperation of the IF stage s ta r t s when the programcounter (PC) a 32-bit register is sent out to fetchthe instruction from memory into the instructionregister (IR) and the PC is incremente d hy 4through an adder to address the next sequentialinstruction. The IR is used to hold the instructionneeded on subsequent clock cycles. A blockdiagram of IF stage is shown in Fig. 1.

I I

I .LO .6 n l p l !nsi"-danF a I 3 5 o r 4 3 l n In Inddr.r8 i t . d - 1~1.16 Isn Imi6 I SO

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To compute the branch target address, thebranch datapath in the execution stage includes asign extension unit and an adder. To perform thecomparison, two register operands are fed intothe ALU unit with a control set to do asubtraction operation. A block diagram ofexecution stage shown in Fig. 3. Tab. 5 Truth table of AL U control bits as functionofALUOp and function code field.

The Karnaugh maps (K-maps) are used tofurther simply the truth table in designing thelogic. A partial VHDL code that generate theALU control bits are shown below:

IC"..24ALUDFig. 3 Architecture of Execution StageTheALU ControlThe ALU control unit has 5-bit instructionfunction field and a 2-bit control field as inputALUO p. The output of the ALU control unit is a3-bit signal that directly controls the ALU bygenerating one of the five 3-bit combinations asshown in Tab. 3.

010 add

Tab. 3 The values of three ALU ontrol lines andcorresponding ALU operationsTab. 4 shows the setup of the ALU controlinputs based on the 2-bit ALUOp control and the6-bit function co de for the R-type instruction andTa b. 5 shows the partial truth table for the threeALU control bits.

Tab. 4 Setup of ALU onuol inputs

To compute the branch target address, the signextend bits are shifted left two bits. This processis done by concatenating the lower 6 bits of thesign extend bits with O02.Then, these shifted bitsare added with the PC+4 from the InstructionFetch stage.Data Memory Stage

The data memory stage stores and loads valuesto and from memory. This stage is active duringthe branch instruction. Data Memory takes twoinputs for the address and the write data, and oneoutput for the read. Tw o separate read and writecontrols either MemWnte or MemRead assertedon any given clock.Memory ReadTo load an instruction the read mem ory controlMemRead is asserted to enable the data to beread from the data memory. The data memorytakes an address from one of the inputs. The datais then sent out 6om the data memory to registerfile through its output Read Da ta.While developing the VHDL codes for DataMemory stage, the memory is initialized to somevalue to ease the simu lation process and errorchecking. A partial code is shown be lowa i d r a i L- =d ad d o d w n l o 0);n m . 0 ~ 1 ~ -4 HEN ~ d r s = - l o _ r U ~ ~ ~ ~ ' ~ ~ ) E W i E

d HEN ad d rs rPTo.s ld lo~Lor@V310' ] ELSET o . d ~ - r O T ' F F ' I ;"I HEN addr-To_s!db@~mrb'101. ) ELSE

Memory WrileTo store an insmction the write memorycontrol MemWrite is asserted to enable the datato be written into the data memory. The datamemory takes an address from one of the inputs.

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The data to be written into the data memory issent into it through the input Write Data.In VHDL coding, the write control signal ofthe corresponding memory asserted in order tobegin the Writing process into the memory. Thisis done by inserting an AND gate between thememWrite control signal and the address that'indicates the memory is to be written. Then, thedata on the write data bus is written into thecorresponding memory location.Write Back Stage

The Write Back Stage writes the res;lt of a Tab. 7 Effect of each of the seven control signals-calculation, memory access or input into theregister file. The component multiplexordetermines whether the data 60m data memoryor the ALU result from the ALU to be writtenback into the register file. The operation of thismultiplexor is controlled by signal MemtoReg.

The operations involved in this stage arehandled by instructions Register-Register ALUinstruction and Load instruction. For Register-Register ALU instruction, the MemtoReg isdeasserted. For Load instruction, the MemtoRegis asserted. When it is asserted, the value, whichcomes out from the Read Data of data memory isselected that becomes the input to the write dataof the register file. The block diagram of writeback stage is show n in Fig. 5 .

Fig. 5 Arclutectweof the Write Back StageControl Unit

In e v e v stage of M IPS RISC, there are somecontrol signals that controls the operations ofeach of the stages that illustrated in Tab. 6 . Tab.7 shows the effect of each of the'seven controlsignals. The control unit is able to take inputsand generate a write signal for each state element,the selector control for each multiplexor. and the

The different stages of MIPS RISC arecombined to m ake a datapath for .MI PSarchitecture. Fig. 6shows the datapath obtainedby composing the separate stages.Since the setting of the control lines dependsonly on the opcode, each control signal is either0, 1 or don't care (X), for each of the opcodevalues. Tab. 8defines the control signals that setfor each opcode. ._

Fig. 6 The Simple Datapathwith the Control Unit

Tab. 8 Sett ing of the control linesWhile developing the codes for control unit,the LCELL function is used to isolate logicblocks in the MIPS design. The LCELL

component is a buffer that allocates a logic cellfor all the files that are associated with the RISCdesign. The LCE LL buffer produces the true andcomplement of a logic function.

111. SIMULATIONNDDISCUSSIONLU control.In this project the compilation and simulation

of the model is run using MAX+PLUS II version9.23. Simulation of design is done in a bottom-upfashion to verify the correctness of design. SmallTab. 6 Control Signals in each RISC stage

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modules are simulated in separate testbencbesbefore they are integrated. There is one testbenchfor each small module and a testbench for thecomplete device. Simulated waveforms for eachstages are shown below. The simulated results ofthe top-level module are tabulated in Tab. 9thatshows the correcmess of the model.Simulation of instruction fetch stage:

Simulation waveform of execution stage:

Simulation of data memory and wr i te backstage:

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Simulation waveform of control unit:

Simulation waveform of top-level module:

Tab. 9 Results of the Top-Level M odule simulation.N. ONCLUSION

By simulating with various test vectors asingle clock cycle 32-bit MIPS RISC processorusing VHDL is successfully designed,implemented and tested. An 8-bit datapath isused with the intention of hardware realizationonto Altera FLEX 10K FPGA chip. Currently,-we are conducting further research that considersfurther reductions in the hardware complexity interms of synthesis and fmally download the codeinto Altera FLEXIOK: EPFlOKlOLC84 FPGAchip on LC84 package for hardware realization.

REFERENCES[IID. Sulik, M. Vasilko, D. Dmckova, P. .Fuchs,"Design o f a RISC Muo contro ller Corein 48 Hours",hnp:l/ulxw.itpapers.com/cgilPSu"aryIT.pl?papd=12747&scid=108 (currentSep 30,2002).[2]Charles E. Gimarc, Veljko M. Mhtinovic, "RISCPrinciples, Architecture, and Design", ComputerScience Press Inc., 1989.[3]Whte paper, "Wide range of comprehensive toolsspeed, Development of high-pafomance embeddedsystem", MIPS Technologies Inc.,hnp:/lwww.mips.com/whitepapers/030399Wl hm l(current Sep. 30,2002).[4]S. Chen, B. Mulgrew , and P. M. Gran< "A clusteringtechnique for digital communications channelequalization using radial basis function networks,"

EEE Trans. Neuml Nerworkr, vol. 4, pp. 570-578,July 1993.

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