
HanyangUniversity

Overview of Hardware Platform

8‐bit micro‐controller devices

Zigbee/802.15.4 radios

TinyOS, SOS, Contiki

8‐bit micro‐controller devices

Zigbee/802.15.4 radios

TinyOS, SOS, Contiki

32‐bit embedded processors

Zigbee/802.15.4 + 802.11 radios

Linux

32‐bit embedded processors

Zigbee/802.15.4 + 802.11 radios

Linux

Tmote Invent

MicaZ OEM

GumStix

Stargate


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Architecture and Application

1. Architecture has limited physical parallelism or a controller hierarchy

Peripherals have a very primitive interface to the processor

Unlike PC architectures where the graphics accelerator has more MIPS than

micro‐processor !

Processor performs computation, resource management and IO

2. Sensor network applications are concurrency intensive

Forward radio packets while sampling sensor data

3. How does one handle all this on a 8 MHz microcontroller ?

Make use of the interrupts and on‐chip peripherals

Exploit the parallelism of the microcontroller to the extent possible

Sensor Node Architecture and Application Characteristics


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Typical Node Hardware

Low PowerEmbeddedProcessor

Radio Transceiver

Memory

Sensors

Battery

8‐bit, 10 MHzSlow Computations

1Kbps ‐ 1Mbps, 3‐100 Meters,

Lossy Transmissions128KB‐1MB

Limited Storage

Expensive ‐‐Requires Supervision

Limited Lifetime


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MICA2 (Berkeley)

Control Board (USU)

AVR ATmega128 (CPU)

CC1000 (Comm.)

2 Encoders2 Encoders

Paper Detector(Optional)(QRB1134)

Paper Detector(Optional)(QRB1134)

3 IR (Sharp GP2D12)

3 IR (Sharp GP2D12)

Photo ResistorPhoto Resistor

2 Servos2 Servos

Sensors

3V Power3V Power

6V Power6V Power

2 PW

2 PWM

2 ADC

3 ADC

2 ADC

Hardware Configuration

Hardware Configuration of the Mobility Platform


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Components of a sensor node

Location Finding System Mobilizer

Processor

StorageTransceiverADCSensor

Sensor Unit

Processing Unit

Powergenerator

Power Unit

A more detailed view


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Architecture Components

Requirements:

1. Small physical size: 1 mm3

2. Low Power Consumption: ~50‐100 uW average power

3. Resource Constrained: 8 MHz, 4 Kb RAM

PROCESSINGSUB‐SYSTEM

COMMUNICATIONSUB‐SYSTEM

SENSINGSUB‐SYSTEM

POWER MGMT.SUB‐SYSTEM

ACTUATIONSUB‐SYSTEM


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Processing Sub‐System

Large number of8 ‐ bit registers

Multiple

PeripheralsHarvard Arch.

Atmel AVR ATMEGA128L

RISC Architecture

8 bit ALU/data‐path

128 Kb FLASH ‐ Code

4 Kb SRAM ‐ Data Details are available in the ATMEGA128L Datasheet


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Polling vs. Interrupts

POLLING

void main(){

while !(timer_overflow){};

read_sensor_value();

}

INTERRUPT DRIVEN

void main(){

call_on_timer_overflow(Timer_overflow_ISR);

Do some useful stuff …..

}

void Timer_overflow_ISR(){

read_sensor_value();

}

When is polling really useful ?

What is the CPU cost of an interrupt/context switch ?

What happens when interrupts are really frequent ?


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AVR Peripherals

BIT BANGED SERIAL IO

void main(){

for (i = 0; i < 8; i++)

out_pin = (dataout >> i) & 0x01;

}

UART SERIAL IO

void main(){

set_up_uart();

uart_put_byte(dataout);

// Do useful stuff

// UART HW working in parallel !

}

1. UART

Serial communication with the PC

2. SPI – Serial Peripheral Interface

Synchronous serial communication

Interface to Radio in the Mote

3. ADC

Analog – Digital Converter

Digitizing sensor readings

4. I/O Ports

General Purpose Input Output pins

(GPIO)

Used to light up LEDs in Mote


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Interrupt Handling

1. Micro‐controllers have a single stack memory model

2. Interrupt is any condition signaled by hardware e.g. Timer Timeout

3. Step‐by‐step Interrupt Handling

Interrupt condition signaled by hardware

Processor finishes execution of current instruction

Processor pushes address of next instruction into the stack

Processor fetches instruction from Interrupt Vector Table

1) Table is stored in program memory

2) Usually filled by C compiler (Can also be done manually !)

3) Instruction in table is “jmp <service_routine>”

Processor jumps into interrupt service routine (ISR) and executes

1) Current context is stored onto stack (i.e. Push all used registers)

Questions:

What happens if another interrupt appears within an ISR ?

Can we have a pre‐emptive multi‐tasking with single stack ? How ?


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AVR Timers

Timer2

Timer08 ‐ bit

Timer1

Timer3

16 ‐ bit

1. Multiple Timers

2. Multiple Clock Sources

CPU Clk

Real Time Clk – 32 KHz

Pre‐scaled Clk from above sources

3. Multiple Interrupts

Timer Overflow

Output Compare

4. Functions

Periodic sampling pulses

Waveform generation


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AVR Power Management

1. Low Power operation – 15 mW @ 4 MHz

2. Multiple Sleep Modes

Sleep Modes: Shutdown unused components

Idle Mode – 6 mW

1) CPU OFF, all peripherals ON

2) CPU “woken up” by interrupts

Power Down Mode – 75 uW

1) CPU and most peripherals OFF

2) External Interrupts, 2 Wire Interface, Watchdog ON

Power Save Mode – 120 uW

1) Similar to Power Down

2) Timer0 continues to run “asynchronously”


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Protocol Stack Implementation

1. Protocol Stack Layers

Modulation – Demodulation

Base‐band Processing

Medium Access Control

2. Protocol stack implementation depends upon radio technology

3. RFM Radio

Modulation ‐ Demodulation only

Processor handles bit‐level synchronization and rest

4. Chipcon CC1000

Modulation ‐ Demodulation and bit‐level synchronization

Processor handles start‐symbol detection and rest

5. Chipcon CC2420

Performs complete packet reception and raises interrupt

Processor handles MAC


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Mica ‐ RFM AVR Interface

Data Interface

1. Periodic waveform generated by Timer0

2. Waveform fed as clk to SPI unit

3. SPI samples Data I/O line periodically during Rx

4. SPI shifts out data during Tx

5. Radio only performs modulation‐demodulation

Control Interface

GPIO Pins of AVR

Two Control lines decide Radio state

SPI

Timer0

SPI CLK

RFMRADIO

Data I/O

CTL0

CTL1


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Mica2 – CC1000 AVR Interface

Control Interface

GPIO Pins of AVR

Simulate SPI in S/W

PCLK: Program Clock

PDATA: Program Data

PALE: R/W Select

Radio state written to registers in radio

Data Interface

1. SPI CLK generated by radio

2. Radio Rx data available as a bit‐stream

3. Radio performs channel encoding‐decoding and bit‐synchronization

SPI

CHIPCONCC1000RADIO

Data I/O

DCLK

PCLKPDATAPALE


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MicaZ – CC2420 Interface

SPI

CHIPCONCC2420RADIO

MISOSCLK

GIO0FIFO

SSD

MOSI

CSn

FIFOPCCA

GIO1

Interrupt

Timer Capture

GIO2

Data Interface

1. SPI CLK generated by uC

2. Radio Rx data available as a byte‐stream of packets

3. Radio performs channel encoding‐decoding, bit‐synchronization,

encryption and packetization

Control Interface

SPI access to radio internal registers


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Radio Power Management

1. Radio has very high power consumption

Tx power is range dependant – 52.2 mW (0 dBm)

Rx power is also very high – 59.1 mW (more than Tx !!)

Power‐down VReg Off ‐ 3 uW

Above data for CC2420, 2.4 GHz

1) Check out CC1000, CC2420 data‐sheets

2. Radio power management critical

Idle state channel monitoring power = Rx Power

Put radio to sleep when not in use

How do we know when somebody is trying to contact us ?

1) Low Power Listening

2) STEM Protocol


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Sensor Node H/W‐S/W Platforms (1/2)

Event detectionWireless communication with neighboring nodes

In-node processing

sensors CPU radio

battery

Acoustic, seismic, image, magnetic,

etc. interface

Electro-magnetic interface

Limited battery supply

Energy efficiency is the crucial H/W and S/W design criterion


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Actuating Sensing Communication

Application (User Components)

Main (includes Scheduler)

Hardware Abstractions

Sensor Node H/W‐S/W Platforms (2/2)

1. Architecture demonstrated by functionality

2. Application = Component + Scheduler


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Component Architecture in Mote (1/2)

1. Note:

Low‐level feedback control is implemented in robot component.

Command interpreter/executer are implemented in the main application

myMotor myADC Server Led Timer Xnp

Robot Component Communication

Main application


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1. What is a component ?

Similar to a object in C++

Provide programming interface

(command / event )

Implementation encapsulated

2. Main components in mote

ADC server (ADCServer)

Led (Led), Timer (Timer)

Motor (myMotor)

Communication (myComm)

Xnp (for wireless download)

Robot component

Main component

COMPONENT

event command

COMPONENT

COMPONENT

Task

signal

Component Architecture in Mote (2/2)


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Software

Hardware

Mote Application

Clock

ADC ServerPWM

Active Message

RFM UART Motor ADC

Sensor

Mote Input‐Output Structure


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Sensor Network Platform (1/2)

1. Atmel ATmega128L

32 kHz crystal

10 bit ADC

UART

SPI bus

2. Radio (Chipcon CC1000)

3. External serial flash

memory(512kbyte)

4. Connectors for interfacing to sensor

and programming boards

5. 3 programmable LEDS

6. JTAG port

ATmega 128L

Serial F

lash

LEDS

Radio

Extern

al Connecto

rs


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Sensor Network Platform (2/2)

1. Inverted‐F Microstrip Antenna and SMA Connector

2. Inverted‐F

Pseudo Omni‐directional

50m range indoors

125m range outdoors

Optimum at 2400‐2460MHz

3. SMA Connector

Enabled by moving a capacitor

> 125m range

Optimum at 2430‐2483MHz


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Sensor

1. Integrated SensorsSensirion SHT111) Humidity (3.5%)

2) Temperature (0.5oC)

3) Digital sensor

Hamamatsu S10871) Photosynthetically active light

2) Silicon diode

Hamamatsu S1337‐BQ1) Total solar light

2) Silicon diode

2. Expansion6 ADC channels

4 digital I/O

Existing sensor boards1) Magnetometer, Ultrasound

2) Accelerometer, 4 PIR sensors

3) Microphone, Buzzer

dot

mag ultrasound

acoustic


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Low Power Operation

1. Efficient Hardware

Integration and Isolation

1) Complementary functionality (DMA, USART, etc)

Selectable Power States (Off, Sleep, Standby)

Operate at low voltages and low current

1) Run to cut‐off voltage of power source

2. Efficient Software

Fine grained control of hardware

Utilize wireless broadcast medium

Aggregate


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Typical WSN Application

1. Periodic

Data Collection

Network Maintenance

Majority of operation

2. Triggered Events

Detection/Notification

Infrequently occurs

1) But… must be reported quickly

and reliably

3. Long Lifetime

Months to Years without

changing batteries

Power management is the key to

WSN success

sleep

wak

eup

processingdata acquisitioncommunication

Po

wer

Time


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Design Principles

1. Key to Low Duty Cycle Operation:

Sleep – majority of the time

Wakeup – quickly start processing

Active – minimize work & return to sleep


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Sleep

1. Majority of time, node is asleep

>99%

2. Minimize sleep current through

Isolating and shutting down individual circuits

Using low power hardware

1) Need RAM retention

3. Run auxiliary hardware components from low speed oscillators

(typically 32kHz)

Perform ADC conversions, DMA transfers, and bus operations while

microcontroller core is stopped


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Overhead of switching from Sleep to Active Mode

Wakeup

Microcontroller Radio (FSK)

10ns – 4ms typical 1– 10 ms typical

2.5 ms292 ns


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Active

1. Microcontroller

Fast processing, low active power

Avoid external oscillators

2. Radio

High data rate, low power tradeoffs

Narrowband radios Low power, lower data rate, simple channel encoding, faster startup

Wideband radios More robust to noise, higher power, high data rates

3. External Flash (stable storage)

Data logging, network code reprogramming, aggregation

High power consumption

Long writes

4. Radio vs. Flash

250kbps radio sending 1 byte Energy : 1.5mJ, Duration : 32ms

Atmel flash writing 1 byte Energy : 3mJ, Duration : 78ms


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Minimize Power Consumption

1. Compare to MicaZ:

a Mica2 mote with AVR mcu and 802.15.4 radio

2. Sleep

Majority of the time

Telos: 2.4mA

MicaZ: 30mA

3. Wakeup

As quickly as possible to process and return to sleep

Telos: 290ns typical, 6ms max

MicaZ: 60ms max internal oscillator, 4ms external

4. Active

Get your work done and get back to sleep

Telos: 4‐8MHz 16‐bit

MicaZ: 8MHz 8‐bit


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CC2420 Radio

1. Fast data rate, robust signal

250kbps : 2Mchip/s : DSSS

2.4GHz : Offset QPSK : 5MHz

16 channels in 802.15.4

‐94dBm sensitivity

2. Low Voltage Operation

1.8V minimum supply

3. Software Assistance for Low Power Microcontrollers

128byte TX/RX buffers for full packet support

Automatic address decoding and automatic acknowledgements

Hardware encryption/authentication

Link quality indicator (assist software link estimation)

1) samples error rate of first 8 chips of packet (8 chips/bit)

CC2420 ‐ IEEE 802.15.4 Compliant


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1. Mica2 (AVR)

0.2 ms wakeup

30 mW sleep

33 mW active

21 mW radio

19 kbps

2.5V min

1) 2/3 of AA capacity

Power Calculation Comparison

2. MicaZ (AVR)

0.2 ms wakeup

30 mW sleep

33 mW active

45 mW radio

250 kbps

2.5V min


3. Telos (TI MSP)

0.006 ms wakeup

2 mW sleep

3 mW active

45 mW radio

250 kbps

1.8V min


Supporting mesh networking with a pair of AA batteries reporting data once every 3 minutes using synchronization (<1% duty cycle)

328 days 945 days453 days

Power Calculation Comparison ‐ Design for low power


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CASP Lab. Platform소개

CASP Lab. Hardware & Software Platform


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1. Anchor NodeCell에 고정된 Node로서, 주기적으로 Cell ID를 송신

환경 센서를 이용하여 주변 환경 정보 수집

2. Mobile Node개인 휴대용 Node, Anchor Node로부터 위치 정보(Cell ID)를 수신

수신된 위치정보를 Wall Node에 전송

가속도 센서 또는 생체 신호 센서를 이용해 긴급 상황 감지

3. Wall Node벽에 고정된 Node로서 라우팅 기능 담당

Mobile Node, Anchor Node로부터 전달 받은 정보를 Sink Node에 전송

4. Sink NodeWall Node로부터 전달 받은 정보를 Ez‐gate에 Serial Cable을 이용하여 전송

5. Ez‐gateSink Node에서 전달받은 정보를 Ethernet을 통해 Task Manager에 전송

6. Tast ManagerEz‐gate를 통해 전달받은 정보를 가공하여, 화면에 출력

특정 Node에 명령 가능.

System organization (1/2)


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System organization (2/2)

분산처리, 통합전송센서 센싱, OTA, Downlink, 알람

위치정보, 환경, OTA, Downlink

Uplink, OTA, Downlink,역할

512KB4KBBoot ROM

32MB4KBSRAM

64MB128KBFlash

400MHz8MHzMCU Speed

Hardware

Linux Kernel 2.6Tiny OS Version 1.1.14OS

3축 가속도빛, 온도, 습도, 동작,

휘어짐 등Sensor

CC2420 + 802.11, 802.3

Chipcon CC2420(2.4GHz)RF

Intel PXA255Atmel ATmega 128LMCU

Sink NodeMobile NodeAnchor NodeWall Node


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Wall Node

ATMEL128L

Interrupt Timer

ADC

Flash

JTAG

SerialPort

CC2420

Oscillator PCB Antenna

SMA Antenna


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Anchor & Mobile Node

ATMEL128L

Interrupt Timer

ADC

Flash

JTAG CC2420

Oscillator

PCB Antenna

Sensor module

SMA Antenna


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PXA255(Intel ARM Processor)

Linux 2.4 Flash ROM

SDRAM& Buffer

JTAG Wall Node

Oscillator & 전원

Serial Interface

Board Debugging

LAN Controller

RS232 & USB

컴퓨터와통신용

Ez‐Gate


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Up link & Down link (1/2)

1. 알고리즘의 핵심

Up link와 down link를 sink노드(down link)와 주변 노드(up link)로 분리하여

적용

기본적인 down link 알고리즘 connected source routing

2. Sink node:

센서노드에 비해서 에너지와 메모리의 사용량이 거의 제한이 없음

Up link되어 들어오는 토플로지 정보 저장 및 down link pass결정에 유리함

3. Sensor node:

실제 필드에서 활동을 하므로 주변 상황에 따라서 up link 라우팅 패스의 결정

에 유리함


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Up link & Down link (2/2)

1. Uplink (Reverse Link)

주변 센서 Node들이 Data를 Sink

Node로 전송 하기 위한 라우팅 방법

2. Downlink (Forward Link)

Sink Node에서 특정 센서 Node로

전송하기 위한 라우팅 방법


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Message format

Up link message

Sensing data

Sequence number

Origin address

Source address

Parent address

Direction flag

Mac header

Down link message

Parent address3

Parent address2

Parent address1

Dest. address

Origin address

Direction flag

Mac header

Command message

Command or dataSequence number

Dest. address

Origin address

Direction flag

Mac header

Direction flag

0= up link1=down link2=down link lock3=down link free5=peer to peer6=reply message

특정 Node에 명령


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Up Link


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Downlink Sequence (1/4)

1211

1110

105

53

32

21

1Sink

11105

321

Direction flag

0= up link

1=down link

2=down link lock

3=down link free

5=peer to peer

6=reply messageSink

4

6 987

parent

source

parent

source

parent

source

12

parent

source

parent

source

parent

source

origin

Mac

header

Parent

address

Source

address

Direction

flag = 0

Origin

address

Multihop message


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1 2 3

1 2 3

5 10 11

5 10 11

Sink

4

6 987

parent

source

parent

source

parent

source

origin

source

12

Mac

header

Direction

flag = 1

Source message

Origin

address

Parent

address 1

Parent

address 2

Parent

address 3

Dest.

address

Mac

header

Direction

flag = 2base

Dest. address

12

Sequence

Direction flag

0 = up link

1 = down link

2 = down link lock

3 = down link free

5 = peer to peer

6 = reply message

Mac

headerbase

Dest. address

12

Direction

flag = 2


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11105

321

Sink

4

6 987

parent

source

parent

source

parent

source

origin

source

12

Mac headerDirection flag =6

Reply origin address 12

Sequence

Direction flag

0= up link1=down link2=down link lock3= down link free5= peer to peer6= reply message

Mac headerDirection flag=6

Source message

Originaddress


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1 2 3

5 10 11

Sink

4

6 987

parent

source

parent

source

parent

source

origin

source

12


base buzzer onDest. address

12

Sequence

Direction flag

0= forward1= inverse 2= inverse lock3= inverse free5=Bi‐direction


Source message

Originaddress

Command Dest. address

Sequence number

Sequence number


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Error Control

1. Down link connection error

센서 네트워크의 토플로지는 센서 노드의 주변 상황에 따라서 변하기 때문에

down link 시에 connection 에러

2. Peer to peer error

connection 이후에 통신 할 때 packet이 loss 되는 에러

3. 해결방법

센서 노드로부터 up link되어오는 우회 경로와 reply message, sequence

message이용

Down link connect error and sequence error

base

4

2

1

Up link

message

Up linkmessage

Replace

route p

assReplaceroute pass

×


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Software Updates by OTA

1. 왜 필요한가?

버그 수정, S/W 업그레이드

새로운 H/W 추가, 센서 Node 기능 변경

2. 전파를 이용한 센서 Node 프로그래밍 방법

3. In‐System programming 방식

One‐to‐One

선을 이용, 호스트에 직접 연결

=> 위험한 지역에 Node가 존재하면?

Node 수에 비례하여 시간이 소요

=> Node 수가 많다면?

4. OTA programming 방식

One‐to‐Many, 전파를 이용, 보다 효율적

MOTE

MOTE

MOTE

Bug Fix

S/W Upgrade

MOTE

MOTE

MOTE

MOTE

In‐Systemprogramming

OTA programming


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Incremental Updates

1. 두 개의 프로그램 이미지를

비교하여 서로 다른 부분만을

Updates하는 방법

2. Traditional Updates

프로그램 크기에 비례하여 전송

패킷 증가

3. Incremental Updates

라디오 전송 에너지 감소

보다 효율적


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Task Manager v0.8

1. 다수의 Ez‐gate에서 발생하는 데이터를 관리하기 위한 Application

관리자에게 각각의 Ez‐gate를 관리하기 용이하도록 통합 GUI 환경 제공

Task Manager v0.8

2. 개발 환경

OS: Windows XP

Compiler: Visual Studio .NET

3. 실행 환경

Windows NT/2000/XP/2003

4. 기능

센서 필드로부터 정보 수집

1) Mobile Node의 위치 및 상태 정보

2) Mobile Node 주변의 환경 정보

GUI를 이용한 센서 필드의 현재 상태 표시

센서 필드의 특정 Node로 메시지 전달

1) 위급 상황 발생 시 구급요원 Node에 메시지 전달

다수의 Ez Gate 관리를 위한 Task Manager

Ez Gate

Ez GateEz Gate

Task Manager v0.8


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Data Aggregation Algorithm

1. 다수의 패킷을 하나로 통합

전체 트래픽 감소 및 패킷 사용 효율 증가

패킷 통합을 위한 알고리즘 작성 및 구현

2. Mobile 및 wall Node에 적용

Node A

Node B

Node C

Node D

A

C

BSink Node

ABC

Node A

Node B

Node C

노드D

A

C

BSink 노드

A

C

B

새로운 알고리즘 적용 전 새로운 알고리즘 적용 후


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History Buffer Algorithm

1. History Buffer를 이용한 패킷 중복 전송 방지

중복된 패킷 검출 시 폐기

트래픽 감소 및 Sink Node의 데이터 처리 부하 감소

2. Mobile 및 wall Node에 적용

새로운 알고리즘 적용 전 새로운 알고리즘 적용 후Node A

Node B

Node C

Node D

A

ASink Node

A

Drop

A

A

Node A

Node B

Node C

Node D

A

ASink Node

A

A

A


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다양한 Platform 소개

다양한 Hardware & Software Platform 소개


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Variety of Sensor Node Platforms

1. Hanback ZigbeX

2. RSC (Rockwell Science Center) WINS & Hidra

3. Sensoria WINS

4. Berkeley’s Motes

5. UCLA’s iBadge

6. UCLA’s Medusa MK‐II

7. Berkeley Piconodes

8. Telos Platform

9. MIT’s μAMPs

10. Intel iMote


HanyangUniversity

Hanback ZigbeX

1. Computing

Atmel 8‐bit RISC microcontroller (CPU 7.3728Mhz)

128KB Flash program memory

4KB SRAM

2. Radio Transceiver

Chipcon CC2420

Radio range: (130m)

Data rate: 240 Kbits/sec

Frequency range: 2.4 GHz (ISM)

3. TinyOS, Nano‐Qplus(ETRI 한국형 OS)

4. Base sensor + Multi‐modal Sensor Board


HanyangUniversity

RSC WINS & Hidra Nodes

3.3v3.3v5 v

3.3v

RS232

5 v

5 v

1. Consists of 2”x2” boards in a

3.5”x3.5”x3” enclosure

StrongARM 1100 processor @ 133

MHz

1) 4MB Flash, 1MB SRAM

Various sensors

1) Seismic (geophone), Acoustic

2) magnetometer, accelerometer,

temperature, pressure

RF communications

1) Connexant’s RDSSS9M Radio @ 100

kbps, 1‐100 mW, 40 channels

eCos RTOS

2. Commercial version: Hidra

μC/OS‐II

TDMA MAC with multihop routing

3. http://wins.rsc.rockwell.com/


HanyangUniversity

1. WINS NG 2.0Development platform used in DARPA SensIT

SH‐4 processor @ 167 MHz

DSP with 4‐channel 16‐bit ADC

GPS

imaging

dual 2.4 GHz FH radios

Linux 2.4 + Sensoria APIs

Commercial version: sGate

2. WINS Tactical Sensor Nodegeo‐location by acoustic ranging and angle

time synchronization to 5 μscooperative distributed event processing

Ref: based on material from Sensoria slides

Sensoria WINS NG 2.0, sGate,

and WINS Tactical Sensor

Sensoria WINS (1/3)


HanyangUniversity

Sensoria WINS (2/3)

ProcessorRAMFlash

GPS

Address/Data Bus

DSPPreprocessor

Multi-ChannelSensor

Interface

AnalogFrontEnd

PreprocessorInterface

ImagerInterface

ImagerModule

ModularWireless and Digital Interfaces

RFModem

1

RFModem

2

DigitalI/O

10/100Ethernet

Ref: based on material from Sensoria slides

Sensoria Node Hardware Architecture


HanyangUniversity

Sensoria WINS (3/3)

Sensoria Node Software Architecture

DS P/

AD CRF

1 RF

2 GP S Du al Co

de c uC

RF

M

odem

1In

terf

ace

RF

M

odem

2In

terf

ace

DS

PIn

terf

ace

Sen

sor

Inte

rfac

e

GP

S

Inte

rfac

e

Aco

ustic

Ran

ging

Inte

rfac

e

Pla

tform

Inte

rfac

e

GP

IO

Ser

ial

Linux 2.4 Kernel

RF

Mod

em

Con

trol

Dis

cove

ry/

Sel

f-A

ssem

bly

Rou

ting

Mes

sagi

ng

Geo

loca

tion

Sen

sing

Sig

nal

Pro

cess

ing

Inte

r-N

ode

Ran

ging

Pro

cess

M

anag

emen

t

Pla

tform

M

anag

emen

t

WINS Node API

GeneralPurposeApp 1

GeneralPurposeApp 2

GeneralPurposeApp 3

GeneralPurposeApp 4

32 Bit RISC Processor Hitachi SH-4, DSP Preprocessor

Linux 2.4 OS- Native Kernel with support for PCMCIA, RPM

Sensoria APIs for RF Modem, Analog Sampling, File System, PSMISC, GAWK etc.


HanyangUniversity

Berkeley Motes (1/4)

Rene2, Dot, Mica, WeC Hardware, 2 AA Batteries, RFM TR1000

Tiny OS – Preemptive, FIFO scheduler,Command & Event Interface

Mate’ Virtual Machine

Programming API


HanyangUniversity


1. Devices that incorporate

communications, processing,

sensors, and batteries into a

small package

2. Atmel microcontroller with

sensors and a communication

unit

RF transceiver, laser module,

or a corner cube reflector

temperature, light, humidity,

pressure, 3 axis

magnetometers, 3 axis

accelerometers

3. TinyOS

light, temperature, 10 kbps @ 20m


HanyangUniversity

1. Atmel ATMEGA103

4 Mhz 8‐bit CPU

128KB Instruction Memory

4KB RAM

2. 4 Mbit flash (AT45DB041B)

SPI interface

Two 264‐byte SRAM Data Buffers

3. RFM TR1000 radio

50 kb/s – ASK

4. Network programming

5. 51‐pin connector

Analog compare + interrupts

RFM : Radio Frequency Module

SPI : Serial to Parallel Interface

Atmega128 Microcontroller

TR 1000 Radio Transceiver4Mbit External Flash

51‐Pin I/O Expansion Connector

Power Regulation MAX1678 (3V)

8 Analog I/O8 Programming

Lines

SPI Bus

CoprocessorTransmissionPower Control

Hardware Accelerators

Digital I/O

DS2401 Unique ID

Berkeley MICA Architecture



HanyangUniversity

J.Hill at al. “System Architecture Directions for Networked Sensors” [online]. Available: http://www.cs.virginia.edu/~qc9b/cs851/SADofNS_2.ppt



HanyangUniversity

UCLA iBadge (1/2)

1. Wearable Sensor Badge

acoustic in/out + DSP

temperature, pressure,

humidity, magnetometer,

accelerometer

ultrasound localization

orientation via magnetometer

and accelerometer

bluetooth radio

2. Sylph Middleware


HanyangUniversity

StorageService

SensorConfigurationManager

BrowsersSpeechRecogn.Service

BayesianFusionService

SensorApps

Sylph Middleware

UCLA iBadge (2/2)


HanyangUniversity

1. 40MHz ARM THUMB

1MB FLASH, 136KB RAM

0.9MIPS/MHz 480MIPS/W (ATmega 242MIPS/W)

2. RS‐485 bus

Out of band data collection, formation of arrays

3. 3 current monitors (Radio, Thumb, rest of the system)

4. 540mAh Rechargeable Li‐Ion battery

UCLA’s Medusa MK‐II

UCLA Medusa MK‐II Localizer Nodes

Mega128L

AT91FR4081

ADXL202

RS‐485

PButton

PButton

PMTU

RFM

UART,JTAG,GPS

UART &JTAG

SPI

SPI

ADC/SPI/GPIO

Connector 1

Connector 2

Ultasnd RX/TXAccessory Board

Light &Temp


HanyangUniversity

Components and batterymounted on back

5 cm

7.6 mm

3 cm

Solar Cell(0.5 mm) Battery

(3.6 mm)

PCB (1 mm)

Chip encapsulation(1.5 mm)

Version 1: Light Powered

Version 2: Vibration Powered

Size determined by powerSize determined by powerdissipation (1 mW dissipation (1 mW avgavg))

Ref: from Jan Rabaey, PAC/C Slides

BWRC’s PicoNode TripWire Sensor Node

Berkeley Piconodes (1/3)


HanyangUniversity

LocalHW

MAC

DW8051

256DATA

Interconnect network

ADC

4kBXDATA

16kBCODE

PHY

ChipSupervisor

SIF

SIFADC

Serial

GPIO

FlashIF

Serial

• Reactive inter‐ and intra‐chip signaling•Modules in power‐down (low‐leakage) mode by default• Events at interface cause wake‐up• Hw Modules selected to meet flexibility needs while optimizing energy efficiency (e.g. 8051 microcontroller)

DLL (MAC)

App/UI

Network

Transport

Baseband

RF (TX/RX)

Sensor/actuatorinterface

Locationing

Aggregation/forwarding

User interface

Sensor/actuators

Antenna

ChipSupervisor

Reactiveradio

Energy train

1 mW on< 10 mW sleepSize: 6 mm2

Ref: from Jan Rabaey, PAC/C Slides

Berkeley Piconodes (2/3)


HanyangUniversity

Berkeley PicoNode (3/3)

1. Defined Goals ‐ Single chip, ultra‐low power PicoNode. Custom low power

application, protocol, network, MAC, and physical layers implemented on flexible

low‐power computation fabrics

2. Applications – Consumer Use.


HanyangUniversity

Telos Platform

1. A new platform for low power research

Monitoring applications:

1) Environmental, Building, Tracking

2. Long lifetime, low power, low cost

3. Built from application experiences and low duty cycle design principles

4. Robustness

Integrated antenna , Integrated sensors, Soldered connections

5. Standards Based

IEEE 802.15.4, USB

6. IEEE 802.15.4

CC2420 radio, 250kbps, 2.4GHz ISM band

7. TI MSP430

Ultra low power

1) 1.6μA sleep, 460μA active, 1.8V operation

Open embedded platform with open source tools, operating system (TinyOS), and designs.


HanyangUniversity

MIT µAMPS (1/2)


HanyangUniversity

MIT µAMPS (2/2)

1. ‘highly integrated, yet flexible sensor node based on two dedicated

chips’ (off‐the‐shelf ‐> systems on chip)

2. StrongARM SA1110 32‐bit, 206MHz, RISC processor

3. 3 acoustic sensors attached to each

node, for estimation of direction of

target (µAMPS I)

[9]


HanyangUniversity

Intel iMote

1. Designed to be a high‐bandwidth sensor platform비디오나 마이크와 같은 멀티미디어 센서를 제어하기 위한 센서

2. Computing

Strong ARM 32‐bit RISC processor

512KB Flash, 64 KB SRAM

3. Radio Transceiver

Bluetooth

Data rate: 500 Kbps ~ 1 Mbps

Frequency : 2.4 GHz (ISM)

4. TinyOS

Multi Sensing

Vibration sensing


HanyangUniversity

Q & A

1. 경청해 주셔서 감사합니다.

2. Q & A

02-architecture of sensor network

Documents

sensoria wins

hanyang university

dsp preprocessor

mobile wallnode

radio

nodec

linux 2

amp