03 broderick qsts_sand2016-4697 c
TRANSCRIPT
Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin
Corporation, for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.
Accelerating Solar Deployment on the
Distribution Grid: Rapid QSTS
Simulations for comprehensive
assessment of distributed PV
Robert Broderick
Sandia National Laboratories
May 10th, 2016
SAND2016-4697 C
Outline
Overview of Sandia’s DOE funded project to radically speed up Quasi-Static Time-Series (QSTS) Simulations
1. Why do we need QSTS?
2. Goals of the Project
3. Technical Path Forward
4. Results to date
Time Series Simulations What is QSTS?
Quasi-static time series (QSTS) analysis captures time-dependent aspects of power flow, including the interaction between the daily changes in load and PV output and control actions by feeder devices and advanced inverters.
QSTS is not directly a PV screening or hosting capacity calculation, but a detailed tool to directly simulate grid impacts for a variety of future scenarios.
Why do we need QSTS?
PV output is temporally variable and the potential interaction with control systems may not be adequately analyzed with traditional snapshot tools
Many potential impacts, like the duration of voltage violations and the increase in voltage regulator operations, cannot be accurately analyzed without it.
What is the problem with today’s methods?
Snapshot analyses that only investigates specific time periods can be overly pessimistic about PV impacts because it does not include the geographic and temporal diversity in PV production and load
QSTS simulation in existing software is too slow for the needed simulations (year-long) at the high time resolution needed to capture solar variability (time steps less than 15 seconds)
3
Time Series Simulations
What is the next step?
Utilities and developers need high speed modeling tools and access to high resolution data to accurately determine the impact of high penetrations of PV and other DER on the distribution system
4
Impact Analysis
High penetrations of PV can affect the distribution feeder equipment and the operation of the system 1. Designed for radial flow in one direction from the substation
2. Designed for aggregated loads with little short-term variability
Distribution system impacts Voltage Regulation Device Operations
Steady State Voltage
Voltage Flicker
5
Impact Analysis
6
Time Series Results
QSTS simulates the number of tap changes on voltage regulators
Results depend the input data and seasonal variations
QSTS simulations present a significant computational burden
7
Goals of QSTS Project
Existing QSTS algorithms can take anywhere from 10 to 120 hours to perform a high resolution 1-year simulation at 1-second resolution.
During the course of the project, algorithms will be developed to dramatically reduce the computational time to less than 5 minutes for a year-long high-resolution time-series simulation, allowing QSTS to be incorporated into the utility interconnection process and decision support tools.
We are going to transform how the industry performs impact analyses by replacing old fashion static tools with new fast and accurate tools that are focused on solving the time dependent problems of PV in the modern distribution system.
8
9
Project Team
Robert Broderick (Sandia Lead)
Barry Mather (NREL co-lead),
Matthew Reno (Sandia)
Matthew Lave (Sandia)
Santiago Grijalva (Georgia Tech)
Tom McDermott (UPITT)
Roger Dugan ( EPRI)
Jean-Sebastien Lacroix (CYME)
DOE Funds: $4,000,000 for 36 months
Cost-Share Funding (CYME & EPRI): $810,000
Proposed Solution – Technical Approach
Task 1 – Fast Time-Series Approximations
Task 2 – Improved Power Flow Solution Algorithms
Task 3 – Circuit Reduction
Task 4 – Parallelization of QSTS Analysis
Task 5 – Implementation of Accelerated QSTS
Task 6 – High-Resolution Input Data.
10
Year-long high-resolution (1 Sec) time-series solutions that can be run in less than 5 minutes for utility decision support systems.
The ratio of relative speed improvements between algorithm improvements and parallelism is part of the R&D question, but hypothetically we could do it using:
Target Performance Level
11
Simulation Duration
1 Day 1 Month 1 Year
Existing Methods 1.6 – 20
minutes 0.8 - 10 hours 10 - 120 hours
Proposed Algorithm
Target 3 minutes 4 minutes 5 minutes
Computation times for 1-second resolution QSTS
𝟏𝟐𝟎 𝐡𝐨𝐮𝐫𝐬
𝟏𝟎 × 𝟐 × 𝟏𝟎 × 𝟕 = 𝟓 𝐦𝐢𝐧𝐮𝐭𝐞𝐬
Fast
Time-Series
Approximation
Improved
Power Flow
Solution
Circuit
Reduction Parallelization
Project began December 1st 2015. Project status meeting completed 5/4/16 at IEEE T&D.
Preliminary Results
12
Preliminary Results
Task 1 Fast Time-Series
Approximations
~6 different approaches are being investigated
Task 2 Improved Power Flow Solution
Algorithms
~60% reduction in power flow solve time using methods
that reuse solution from previous time step
Task 3 Circuit Reduction
Circuit Reduction methods showing great promise to
achieve at least a 90% reduction in complexity
Task 4 Parallelization of QSTS
Diakoptics Methodology under development
Task 5 Implementation
Begins in Year 2
Task 6 High-Resolution Input Data
Solar irradiance algorithm is being evaluated
Circuit Reduction on Range of Feeders Feeder UT11
96% Reduction
<0.01% Error
Feeder Ckt 7
98% Reduction
<0.02% Error
Feeder UQ11
97% Reduction
<0.02% Error
Fu
ll
Re
du
ce
d
0 2 4 6 8 10 12 14 16 18116
117
118
119
120
121
122
123
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 1: Lines:454, Xfmrs:126, Loads:128, Buses:581
Auto Selected
Capacitor
Transformer
Topology
Metered
Full Circuit with BOI Markers
Metered
Auto Selected
Capacitor
Transformer
Topology
Reduced Circuit with BOI Markers
Metered
Auto Selected
Capacitor
Transformer
Topology
0 2 4 6 8 10 12 14 16 18116
117
118
119
120
121
122
123
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 2: Lines:360, Xfmrs:126, Loads:128, Buses:487
Auto Selected
Capacitor
Transformer
Topology
Metered
0 2 4 6 8 10 12 14 16 18116
117
118
119
120
121
122
123
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 3: Lines:68, Xfmrs:5, Loads:119, Buses:74
Auto Selected
Capacitor
Transformer
Topology
Metered
0 2 4 6 8 10 12 14 16 18116
117
118
119
120
121
122
123
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 4: Lines:18, Xfmrs:5, Loads:38, Buses:24
Auto Selected
Capacitor
Transformer
Topology
Metered
0 2 4 6 8 10 12 14 16 18116
117
118
119
120
121
122
123
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 1: Lines:454, Xfmrs:126, Loads:128, Buses:581
Auto Selected
Capacitor
Transformer
Topology
Metered
Full Circuit with BOI Markers
Metered
Auto Selected
Capacitor
Transformer
Topology
Reduced Circuit with BOI Markers
Metered
Auto Selected
Capacitor
Transformer
Topology
0 2 4 6 8 10 12 14 16 18116
117
118
119
120
121
122
123
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 2: Lines:360, Xfmrs:126, Loads:128, Buses:487
Auto Selected
Capacitor
Transformer
Topology
Metered
0 2 4 6 8 10 12 14 16 18116
117
118
119
120
121
122
123
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 3: Lines:68, Xfmrs:5, Loads:119, Buses:74
Auto Selected
Capacitor
Transformer
Topology
Metered
0 2 4 6 8 10 12 14 16 18116
117
118
119
120
121
122
123
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 4: Lines:18, Xfmrs:5, Loads:38, Buses:24
Auto Selected
Capacitor
Transformer
Topology
Metered
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5115
116
117
118
119
120
121
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 1: Lines:1148, Xfmrs:161, Loads:906, Buses:1246
Auto Selected
Capacitor
Transformer
Topology
Metered
Full Circuit with BOI Markers
Metered
Auto Selected
Capacitor
Transformer
Topology
Reduced Circuit with BOI Markers
Metered
Auto Selected
Capacitor
Transformer
Topology
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5115
116
117
118
119
120
121
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 2: Lines:1056, Xfmrs:161, Loads:906, Buses:1154
Auto Selected
Capacitor
Transformer
Topology
Metered
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5115
116
117
118
119
120
121
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 3: Lines:63, Xfmrs:5, Loads:135, Buses:67
Auto Selected
Capacitor
Transformer
Topology
Metered
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5115
116
117
118
119
120
121
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 4: Lines:16, Xfmrs:5, Loads:44, Buses:20
Auto Selected
Capacitor
Transformer
Topology
Metered
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5115
116
117
118
119
120
121
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 1: Lines:1148, Xfmrs:161, Loads:906, Buses:1246
Auto Selected
Capacitor
Transformer
Topology
Metered
Full Circuit with BOI Markers
Metered
Auto Selected
Capacitor
Transformer
Topology
Reduced Circuit with BOI Markers
Metered
Auto Selected
Capacitor
Transformer
Topology
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5115
116
117
118
119
120
121
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 2: Lines:1056, Xfmrs:161, Loads:906, Buses:1154
Auto Selected
Capacitor
Transformer
Topology
Metered
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5115
116
117
118
119
120
121
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 3: Lines:63, Xfmrs:5, Loads:135, Buses:67
Auto Selected
Capacitor
Transformer
Topology
Metered
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5115
116
117
118
119
120
121
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 4: Lines:16, Xfmrs:5, Loads:44, Buses:20
Auto Selected
Capacitor
Transformer
Topology
Metered
0 1 2 3 4 5 6117
118
119
120
121
122
123
124
125
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 1: Lines:529, Xfmrs:216, Loads:218, Buses:732
Auto Selected
Capacitor
Transformer
Topology
Metered
Full Circuit with BOI Markers
Metered
Auto Selected
Capacitor
Transformer
Topology
Reduced Circuit with BOI Markers
Metered
Auto Selected
Capacitor
Transformer
Topology
0 1 2 3 4 5 6117
118
119
120
121
122
123
124
125
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 2: Lines:499, Xfmrs:216, Loads:218, Buses:702
Auto Selected
Capacitor
Transformer
Topology
Metered
0 1 2 3 4 5 6117
118
119
120
121
122
123
124
125
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 3: Lines:92, Xfmrs:6, Loads:115, Buses:99
Auto Selected
Capacitor
Transformer
Topology
Metered
0 1 2 3 4 5 6117
118
119
120
121
122
123
124
125
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 4: Lines:18, Xfmrs:6, Loads:27, Buses:25
Auto Selected
Capacitor
Transformer
Topology
Metered
0 1 2 3 4 5 6117
118
119
120
121
122
123
124
125
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 1: Lines:529, Xfmrs:216, Loads:218, Buses:732
Auto Selected
Capacitor
Transformer
Topology
Metered
Full Circuit with BOI Markers
Metered
Auto Selected
Capacitor
Transformer
Topology
Reduced Circuit with BOI Markers
Metered
Auto Selected
Capacitor
Transformer
Topology
0 1 2 3 4 5 6117
118
119
120
121
122
123
124
125
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 2: Lines:499, Xfmrs:216, Loads:218, Buses:702
Auto Selected
Capacitor
Transformer
Topology
Metered
0 1 2 3 4 5 6117
118
119
120
121
122
123
124
125
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 3: Lines:92, Xfmrs:6, Loads:115, Buses:99
Auto Selected
Capacitor
Transformer
Topology
Metered
0 1 2 3 4 5 6117
118
119
120
121
122
123
124
125
Distance from Substation (km)
Bu
s V
olt
ag
e (
12
0 V
Ba
se
)
Step 4: Lines:18, Xfmrs:6, Loads:27, Buses:25
Auto Selected
Capacitor
Transformer
Topology
Metered
13
QUESTIONS?
Sandia National Laboratories
Robert J. Broderick
Matthew J. Reno
Matthew Lave
14