03 cmos dc characteristics.pdf

7/23/2019 03 CMOS DC characteristics.pdf

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Static CMOS Inverter


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DC Characteristics

Relate the output voltage to the input voltage

Assume input changes slowly enough that capacitances

have plenty of time to charge or discharge


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Static CMOS inverter

Vout vs Vin When Vin= 0 ,Vout= VDD

When Vin= VDD, Vout= 0

In between, Vout depends on

transistor current

Regions of operation given intable below

Vtn threshold voltage of n-

channel device Vtp threshold voltage of p-

channel device (-ve)


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Nmos and Pmos operation


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Graphical derivation of the inverter DC

response: I-V Characteristics Make pMOS wider than nMOS such that n=p

For simplicity lets assume Vtn=-Vtp


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Graphical derivation of the inverter DC

response: Voltage Transfer Characteristics

Can be deduced from the load-line plots, which

superimpose the current characteristics of nmos and pmos

devices Combining the V-I characteristics of nmos and pmos


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Pmos load lines


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CMOS inverter load characteristics


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CMOS inverter VTC


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CMOS inverter VTC


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REGION A & B


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Switching threshold region : REGION C


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REGION E


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Input threshold

In region C, both transistors are in saturation

Ideal transistors are in this region for only Vin = VDD/2 and

the DC curve slope in C is -

The cross-over point where Vinv =Vin = Vout is called theinput threshold


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DC transfer curve-operating regions


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Beta ratio effects

For p = n, Vinv is VDD/2

This maximises the noise margins and allows a capacitive

load to charge and discharge in equal times

Inverters with different beta ratios r = p/n are skewed

inverters If r>1, the inverter is HI-skewed

If r


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Transfer characteristics of skewed inverters

As beta ratio is changed,

the switching threshold

moves

The output voltagetransition remains sharp

Gates are usually skewed

by adjusting widths of

Xtors while maintainingminimum length for

speed


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Inverter threshold(analytical) For saturation

Then

Setting currents to be equal and opposite, Vin as a function of r:

If Vtn = -Vtp and r = 1,then Vinv = VDD/2


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Noise Noise in Digital Integrated Circuits

A digital gate should perform the digital function it is designed for evensubject to noisy conditions.

Noise - unwanted variations of voltages and currents at the logicnodes

measure how robust the structure is with respect to variations in themanufacturing and noise disturbances.

digital circuit operates on logic variables x {0,1}.

Mapping electrical voltage into a discrete variable to represent logicalvalues, associating a nominal voltage level with each logic state:

1 VOH, 0 VOL where VOH and VOL represent the high/lowlogic levels

VOL = VOH and VOH = VOL

Logic swing : VOH VOL (Equal to VDD for best case)


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Immunity against noise

There are many noise sources

The noise can affect the level of the signals at the input of

the gate and can cause faulty switching.

A robust gate: Fluctuations of the voltage at the input of the gate would not cause faulty

transitions

We need to analyze the robustness of the gate against

variations of the input voltage.


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Mapping between analog and digital signals


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Noise Margin

Allows to determine the allowable noise voltage on input of a

gate so that the output will not be corrupted

measure of how stable inputs are with respect to signal

interference

The noise margins represent the level of noise that can besustained when gate are cascaded.

The margins should be larger than 0 for a digital circuit to be

functional (and by preference as large as possible).

Uses 2 parameters: LOW noise margin, NML

HIGH noise margin, NMH


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Noise Margin


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Contd..

NML - the difference in maximum LOW input voltage

recognized by receiving gate and the maximum LOW

output voltage produced by the driving gate

NML = VIL - VOL

NMH - the difference in the minimum HIGH output

voltage of the driving gate and the minimum HIGH input

voltage recognized by receiving gateNM

H

= VOH

- VIH


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Contd..

To maximize noise margins, select logic levels at unity

gain point of DC transfer characteristic


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Pass Transistor

We have assumed source is grounded

What if source > 0?

e.g. pass transistor passing VDD

Vg = VDD If Vs > VDD-Vt => Vgs < Vt

Hence transistor would turn itself off

nMOS pass transistors pull no higher than VDD-Vtn Called a degraded 1

Approach degraded value slowly (low Ids)

pMOS pass transistors pull no lower than Vtp

VDD

VDD


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Pass Transistor logic

Threshold voltage drop at the output of thepass-transistor gate

Voltage drop does not exceed Vth when thereare multiple transistors in the path


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Pass Transistor Ckts

As the source can rise to within a threshold voltage of the gate, the

output of several transistors in series is no more degraded than that

of a single transistor. If a degraded output drives the gate of another transistor, the 2nd xtor can

produce an even further degraded output

03 cmos dc characteristics.pdf

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