0.3v tunable ota and gm-c filter in 0.13 m...

Noname manuscript No.(will be inserted by the editor)

0.3V Tunable OTA and Gm-C Filter in 0.13µmCMOS

Farzan Rezaei

Received: date / Accepted: date

Abstract This paper presents an ultra-low-voltage operational transconduc-tance amplifier (OTA) and Gm-C filter, both working with 0.3V single supplyvoltage. Using pseudo-differential structure, the common mode rejection is themain challenge in low voltage condition which is overcome by a new commonmode feedback circuit. The OTA can be tuned through the gate terminal ofbody-driven PMOS input transistors. Post-layout simulation shows 23.4 dBdifferential gain and 47.4 dB CMRR at low frequencies. By changing the tunevoltage from 50mV to 0V, the OTA’s transconductance can be tuned from 7.9to 17.4 µA/V . By applying input voltages up to 0.36 Vpp, the THD of outputcurrent remains less than -60 dB. The proposed OTA is employed to imple-ment a tunable low-pass Gm-C filter. The cutoff frequency of Gm-C filter canbe tuned from 1.13 to 1.9 MHz that makes it applicable in the multi-standarddirect conversion receivers as channel selection filter. The power consumptionof filter is 111.3 µW and its input referred voltage noise is 168.7 nV/

√Hz, as

results of post-layout simulations. The post-layout simulation shows the IIP3of 8.5 dBm for the cutoff frequency of 1.9 MHz.

Keywords Ultra-low-voltage design · Operational transconductance ampli-fier · Gm-C filter · layout · tunable

1 Introduction

Using low-voltage small batteries with longer charge-discharge cycle is essentialin todays portable equipements like cell phones, laptops, medical devices andetc [1–5]. Moreover, modern systems fabricated in deep sub-micron CMOS

Farzan RezaeiElectrical and Computer Engineering Department, University of Kashan, Kashan, Iran.Tel.: +989183655145Fax: +983155511121E-mail: [email protected]

2 Farzan Rezaei

technologies must be designed to work with low supply voltage due to thereliability issues regarding the thinner gate oxide layer of transistors [3,6,7].Operational transconductance amplifier (OTA) is a key building block of theanalog parts of many circuits and systems [8–10]. The performance of OTAdirectly determines the overall performance of receivers’ analog front-end partssuch as voltage controlled oscillators, Gm-C filters, variable gain amplifiers andmixers [11].

Using weakly inverted devices, body biased transistors, charge pump meth-ods, floating gate transistors and pseudo-differential non-cascode structure arethe main low-voltage design techniques [6,12]. However, the mentioned tech-niques either degrade the performance of circuit or constrain the designersto employ special technologies. While subthreshold operation of devices slowsdown circuit and increases the area usage on chip, the body driven devicessuffer from poor transconductance and large input capacitance [3,13–15]. Thecharge pump technique may lead to reliability problems in some cases andlow-voltage design using floating gate transistors is only feasible in double-poly technologies [6,16].

The channel selection filter is an important building block of multi-standarddirect conversion receivers which is responsible for rejecting unwanted signalsfrom the desired channel. The Gm-C structure is frequently used to imple-ment the channel selection filter as it makes low-power and high frequencyoperation. However compared to their active-RC counterparts, the Gm-C fil-ters suffer from poor linearity due to the open-loop operation of Gm cells[17,18]. Thus, the OTAs which are used in Gm-C filters should be designedto have high linearity and wide tunability, which both are hardly achievableunder low-voltage condition.

In this paper a 0.3V single supply voltage OTA is designed, benefits low-power highly linear operation and tuning capability. The OTA composed ofbody-driven pseudo-differential based transconductor core and a novel com-mon mode feedback (CMFB) circuit. Using body-driven technique, the CMFBcircuit senses the common mode voltage of output nodes and returns two feed-back voltages to the bias network of transconductor to effectively stabilize thecommon mode voltage of output nodes. The OTA is employed to implementa tunable linear Gm-C filter. The cutoff frequency of proposed Gm-C filter istunable from 1.13 to 1.9 MHz, thus can be utilized in the multi-standard di-rect conversion receivers. Monte Carlo simulation results show the robustnessof proposed circuits against the fabrication errors and the post-layout simula-tion results show the good performance after appearing parasitic effects.

The rest of paper is organized as follows. In section 2 the subthresholdoperation of body-driven MOS transistor is investigated. In section 3 the pro-posed OTA and its physical layout are given. The low-pass Gm-C filter designis presented in section 4. The simulation results are shown in section 5 andthe section 6 concludes the paper.

0.3V Tunable OTA and Gm-C Filter in 0.13µm CMOS 3

2 Subthreshold operation of body-driven MOS transistor

When the gate-source voltage of MOS transistor drops below its thresholdvoltage, the channel becomes weakly inverted and diffusion current flows fromdrain to source. In low voltage designs where the supply voltage is less thanthe threshold voltage of transistors, the transistors inevitably works in the“subthreshold region”. The I/V characteristic of subthreshold-mode transistoris given by [19]

iDS = IS

(W

L

)exp

(qvGS − vTH

nkT

)[1− exp(−q vDS

kT)

](1)

in which IS is the characteristic current dependent on the technological param-eters, n is the weak inversion slope, k is Boltzmann constant, q is the chargeof electron, T is temperature and other parameters have their usual meanings.The gate and body transconductance gm and gmb are obtained as [19]

gm =∂iDS

∂vGS=IDS

nvt(2)

and

gmb =∂iDS

∂vBS=

γ

2√

2φF + VSBNMOS

gm, (3)

respectively, where IDS is the dc operating point current, vt is the thermalvoltage of 26mV at room temperature, γ is the body effect coefficient, φF isthe Fermi potential and VSB is the dc value of source-body voltage. The laterrelation shows that the gmb increases at higher currents and lower values ofVSB . The drain-source small-signal resistance is directly proportional to thelength and inversely to the current (rds ∝ L/IDS), thus the intrinsic gain oftransistor is proportional to L/

√IDS .

As the proposed 0.3V OTA is based on body-driven transistors, the transcon-ductance gmb, drain-source resistance rds and the intrinsic gain (gmb×rds) areevaluated in 0.13 µm CMOS technology for constant aspect ratio of 100 anddifferent transistor lengths. Using test circuits in Fig. 1, the gmb and rds aresimulated in four transistor lengths 0.13, 0.5, 1 and 2 µm and the results in-cluding the intrinsic gain are shown in Fig. 2. According to relation (1), thecurrent is only dependent on the aspect ratio, however, according to the sim-ulation results it significantly reduces at length values close to the minimumfeature size due to the second-order effects. Hence, the gmb in L=0.13µm caseis much less than that in other lengths. With the exception of rds in L=0.13µmwhich is higher than that of L=0.5µm due to the lower current in former one,the drain-source resistance increases when the transistor length increases. Theintrinsic gain gmb × rds accordingly is higher for larger values of transistorlength.

4 Farzan Rezaei

0.3V

0.15V+

-

0.15V

vds

0.3V

vbs

0.15V

+

-

0.15V

ids

gmb=ids/vbs

ids

rds=vds/ids(a) (b)

Fig. 1 Test circuits for simulation of (a) gmb and (b) rds

Fig. 2 gmb, rds and intrinsic gain (gmb× rds) for PMOS transistor operating at 0.3 V withfour length values.

3 Proposed 0.3 V OTA

3.1 OTA schematic

The proposed low-voltage OTA is shown in Fig. 3. The transconductor core iscomposed of transistors M1 to M4 and the CMFB circuit is composed of M5 toM14. Using NWell technology, the input voltages are applied to the body ter-minals of PMOS transistors M1 and M2. In such a low-voltage condition, thebody-driven technique seems to be the only solution for achieving rail-to-raillinear operation. The output nodes are connected to the body terminals of M5and M6, where their common drain node senses the common mode (CM) volt-age of output nodes. To effectively suppress the output CM voltage variations,the CM feedback is applied through two paths. First feedback voltage at node“cf1” is applied to the body terminals of M13 and M14. Using a body-drivensource follower stage, the second feedback voltage is created at node “cf2” andis applied to the gates of M3 and M4. By this way, the output CM voltage


would be stabilized at 0.15 V which is half of the supply voltage. The variationof output CM voltage that can be occurred either by the input CM voltagevariation or by the fabrication errors will be compensated by the CMFB circuitaction. For example when the output CM voltage becomes larger than 0.15V,the voltages of nodes “cf1” and “cf2” increase proportionally. Consequentlythe currents of M13 and M14 decrease and those of M3 and M4 increase suchthat to return the output CM voltage to 0.15V.

inp inn

tune

cf1 cf1

cf2cf1

cf2

outn outp

M1 M2M13 M14

M3 M4

M5 M6

M7 M8 M9

M10

M11

M12

VDD

Gnd

Transconductor

Core

CMFB

Fig. 3 Proposed OTA.

3.2 Differential and common mode gains

The differential gain can be obtained as

Ad = −gmb1,2Rout, (4)

where, Rout = rds1||rds3||rds13. To achieve higher differential gain, the channellength of transistors M1 to M4 is set to 2µm. Regarding two CM feedbackpaths, the CM gain can be obtained as

Ac =−gmb1,2Rout

1 +(gmb13,14Acf1 + gm3,4Acf2

)Rout

. (5)

Acf1 and Acf2 are the voltage gains from the output CM voltage to the feed-back nodes “cf1” and “cf2” which are given by

Acf1 =vcf1vocm

=2gmb5,6

gds7 + gm8

gm9

gds9 + gds10(6)

Acf2 =vcf2vocm

= Acf1 ×gmb11

gmb11 + gm11 + gds11 + gds12(7)

To reduce the CM gain, the transistor M7 is added to the CMFB circuit todecrease the current of M8 and consequently decrease gm8. Also, the length oftransistors M9 and M10 is adopted to be 2µm to reduce the gds9 and gds10.Theaspect ratio of proposed OTA’s transistors are given in table 1.

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Table 1 Aspect ratio of transistors.

Transistor W/L (µm/µm)

M1,2 80/2M3,4 200/2M5,6 50/1M7 60/0.5M8 10/0.5M9 90/2M10 70/2M11,12 30/0.5M13,14 24/2

3.3 Linearity and tunability performance

As an essential requirement, the proposed OTA should have tunable transcon-ductance to be applicable in tunable Gm-C filters. The tuning mechanism isaccomplished by applying the tune voltage to the gate node of input transis-tors M1 and M2. Referring to equations (2) and (3), the tune voltage changesthe current of M1 and M2 and therefore changes the gm1,2 and gmb1,2.

The first- to third-order coefficients of the power series that gives the cur-rent of body-driven subthreshold transistor as function of its source-body volt-age can be obtained by partial differentiating of relation (1). From which theoutput current flowing into the load from “outp” to “outn” is

iout =1

2

n− 1

n

IDvtvin +

1

8

IDv3t

(n− 1)3

6n3v3in (8)

The third-order harmonic distortion can be approximated to

HD3 =A2

96v2t

(γ

γ +√

2φF + VBS

)2

(9)

Equation (9) shows that at larger values of VBS the HD3 is lower and theoutput current is more linear.

3.4 Noise performance

The thermal and flicker components of input referred voltage noise can beobtained as

v2nth,in =8kTγ

g2mb1,2

(gm1,2 + gm3,4 + gm13,14

)(10)

v2nf,in =2K

Coxg2mb1,2f

( g2m1,2

W1,2L1,2+

g2m13,14

W13,14L13,14+

g2m3,4

W3,4L3,4

)(11)

In relation (10) γ is the excess noise factor which is about n/2 in sub-threshold region. In relation (11) K is a process-dependent constant and f is


frequency. According to relation (10) the thermal noise can be decreased byincreasing the body-transconductance of M1,2. There is a trade-off betweenthe differential gain/noise and the common mode gain. The higher current ofM1,2 and lower one for M13,14 results in higher gmb1,2 which leads to higherdifferential gain and lower thermal noise. However this also results in lowergmb13,14 and therefore higher common mode gain regarding relation (5). As acompromise between differential gain, noise and common mode gain the ratioof M1,2 current to that of M13,14 is considered to be about 10 to 3. In thecase of flicker noise however, according to relation (11) it can be minimized byenlarging transistors. For differential gain requirements, the transistors’ sizesare sufficiently large and therefore the flicker noise is negligible.

3.5 Phisical layout of proposed OTA

The layout of proposed OTA, prepared with 1P8M 0.13µm CMOS technologyis shown in Fig. 4. The area usage is about 46µm×78.5µm and two layersmetal is used for interconnections.

Fig. 4 Layout of proposed OTA.

4 Gm-C Filter Design

The main features of proposed OTA are ultra-low-voltage, high linearity, tun-ing capability and high CMRR. However, as an important building block, its

8 Farzan Rezaei

applicability to larger circuits should be investigated. For this purpose, theproposed OTA is employed to implement a third-order low-pass Gm-C filter.The filter is shown in Fig. 5, in which Gm3 to Gm6 implement two floatinginductors with the value of Ci/g

2m. The capacitors C1 and C2 are set to 0.5pF

and C3 and Ci are adopted to be 0.2 and 0.6pF, respectively. Simulation re-sults show that the cutoff frequency of filter can be tuned from 1.13 to 1.9MHz by changing the tune voltage from 0 to 50 mV. The layout of filter isshown in Fig. 6 in which the MIMCAP is used for all capacitors. The areausage of filter is 247µm×155µm.

+

_

+

_

+

_

+

_

+

_

+

_

+

_

_

+

_

+

_

+

_

+

_

+

_

+

_

+

Gm1 Gm2 Gm3 Gm4 Gm5 Gm6 Gm7vin+vin-

Vo+

Vo-

C3

C3

CiC1 C2

Fig. 5 Third-order low-pass Gm-C filter.

Fig. 6 Filter layout.


Fig. 7 Post-layout simulation of transconductance versus differential input voltage.

5 Simulation results

5.1 OTA simulation results

The proposed OTA is post-layout simulated in 0.13µm CMOS technology.Under 0.3 V single supply voltage, the power consumption of OTA is 17.9µW. The OTA’s transconductance is simulated versus the differential inputvoltage at six tuning conditions and the results are shown in Fig. 7. Accordingto these results, by changing the tune voltage from 50 mV to 0 V, the Gm canbe tuned from 7.9 to 17.4 µA/V. The flat curves up to about 0.3 Vpp inputvoltage show the high linearity of proposed OTA for rail-to-rail input voltage.

By connecting 5pF capacitance load between output terminals, the mag-nitude of differential output voltage is simulated and shown in Fig. 8. Theresults show 23.4 dB dc gain, and 1.04 MHz unity gain bandwidth (UGBW).As shown in Fig. 9, the input referred voltage noise is 35.3 nV/

√(Hz) at 100

kHz.The THD of OTA’s output current is simulated for various input voltage

amplitudes and the result is shown in Fig. 10. The THD values are less than-58 dB for input voltages up to 0.4 Vpp. The post-layout simulation resultsare summarized in table 2.

To evaluate the performance of proposed OTA against the fabrication er-rors, the Monte Carlo simulations are performed for the main features of OTAunder standard process and mismatch errors. By applying a 0.2Vpp inputvoltage at 100 kHz to the OTA which is tuned at highest transconductance,the THD of output current is simulated 100 times and the histogram plot ofresults is shown in Fig. 11. The mean and the standard deviation of samplesare -68 and 2.4 dB, respectively, that show the robustness of circuit against the

10 Farzan Rezaei

Fig. 8 Post-layout simulation of magnitude of differential output voltage.

Fig. 9 Post-layout simulation of input referred voltage noise.

fabrication errors. The Monte Carlo simulation results of DC gain, UGBW,common mode gain and CMRR are given in table 3.

5.2 Gm-C filter simulation results

The post-layout simulation result of magnitude response of Gm-C filter isshown in Fig. 12. The tune voltage is changed from 0 to 30 mV throughwhich the cutoff frequency is tuned from 1.13 to 1.9 MHz. Because of parasiticresistances effects, the pass-band gain is decreased in post-layout simulation.The main properties of proposed filter are summarized in table 4. The post-layout IIP3 simulation result is shown in Fig. 13. The IIP3 is simulated by


Fig. 10 Post-layout simulation of THD of OTA’s output current.

Fig. 11 Monte Carlo simulation results of OTA’s THD.

applying 100 kHz two-tone input voltage. For the cutoff frequency of 1.9MHz,the IIP3 is as high as 8.5dBm that shows the high linearity of filter.

5.3 Comparison with similar works

In table 5, the post-layout simulation results of proposed OTA are comparedwith some previously presented low-voltage designs. Under 0.3V supply volt-age, the proposed OTA achieves tuning capability which makes it applicable intunable circuits. Other advantages of proposed OTA are low-power operation,

12 Farzan Rezaei

Table 2 Simulation results of proposed OTA.

Characteristic Post-layout simulation results

Supply voltage (V) 0.3Power consumption (µW ) 17.9Transconductance (µA/V ) 7.9-17.4DC gain (dB) 23.4Unity gain bandwidth (MHz) 1.04Phase margin (degree) 97.4Load capacitance (pF) 5CMRR (dB) 47.4

Input referred voltage noise (nV/√

(Hz)) @100kHz 35.3

THD (dB) for 0.2Vpp input voltage @ 100kHz -70.1

Table 3 Monte Carlo simulation results for 100 runs.

Characteristic Mean Standard deviation

DC differential gain 19.8 dB 5.7 dBUnity gain bandwidth 1.04 MHz 173 kHzDC common mode gain -23.9 dB 4.47 dBCMRR 40.7 dB 7.68 dB

Fig. 12 Post-layout simulation of magnitude response of Gm-C filter.

Table 4 Main properties of proposed Gm-C filter.

Characteristic Post-layout simulation results

Supply voltage (V) 0.3Power consumption (µW ) 111.3Cutoff frequency (MHz) 1.13-1.9

Input referred voltage noise (nV/√

(Hz)) @100kHz 168.7

IIP3 (dBm) @ 100 kHz 8.5, Vtune=0 V, fC=1.9 MHz-7.4, Vtune=30 mV, fC=1.1 MHz


Fig. 13 Post-layout simulation of filter’s IIP3.

high linearity, low noise performance and high phase margin. As a compromisebetween the DC gain and linearity, DC gain is lowered to make OTA suitablefor Gm-C filter application. To consider the main features for comparison, afigure of merit (FOM) is defined which is composed of the dc gain, unity gainbandwidth and capacitance load at the numerator and the square of supplyvoltage, power consumption, distortion, noise and area usage in the denomi-nator. The FOM values computed in table 5 demonstrate that the proposedOTA exhibits state-of-the-art performance.

FOM =DCgain× UGBW × CL

V 2Supply × Power ×%distortion× noise× area

(12)

6 Conclusion

In this paper a novel ultra-low-voltage OTA was proposed in 0.13µm CMOStechnology. The OTA works with 0.3 V supply voltage and consumes 17.9µW according to post-layout simulation results. The transconductor’s core isbased on body-driven pseudo-differential structure in which the transconduc-tance can be tuned through the gate terminal of input PMOS transistors.Although the common mode rejection is a challenging task in such a low volt-age condition, the common mode feedback is efficiently applied through twopaths such that the dc CMRR is increased to 47.4 dB. By changing the tunevoltage from 0 to 50 mV, the OTA’s transconductance varies from 17.4 to 7.9µA/V . By applying the input voltages up to 0.36 Vpp, the THD still remainsbelow -60 dB. A third-order low-pass Gm-C filter is designed using the pro-posed OTA, which consumes 111.3 µW under 0.3 V supply voltage. The cutofffrequency of filter is tunable from 1.13 to 1.9 MHz that makes it suitable formulti-standard direct conversion receivers. The IIP3 of filter is simulated tobe 8.5 dBm at 1.9 MHz cutoff frequency.

14 Farzan Rezaei

Table 5 Proposed OTA post-layout simulation results, compared with similar works inliteratures.

Characteristic This work [12] [12] [14] [6] [3]CMOS technology 0.13µm 65 nm 65 nm 0.13µm 0.18µm 0.18µm

Supply voltage(V)

0.3 0.35 0.5 0.25 0.5 0.5

Powerconsumption

(µW )17.9 17 182 0.018 110 60

Transconductance(µA/V )

7.9-17.4 - - - Not Tunable -

DC gain (dB) 23.4 43 46 60 52 47.7Unity gain

bandwidth (MHz)1.04 3.6 38 1.88kHz 2.5 17.8

Phase margin(degree)

97.4 56 57 53 - 60

Load capacitance(pF)

5 (betweenoutput nodes)

3 3 15 20 20

CMRR (dB) 47.4 - - - 78 138

Input referredvoltage noise

(nV/√

(Hz))@100kHz

35.3 926 938 3.3µV/√

(Hz) 80 @ 1MHz 80 @ 1 MHz

THD

-70.1dB for0.2Vpp input

voltage @100kHz

0.6% 0.4% 0.2%1% at 0.4Vppoutput voltage

HD3=-42.4 dBfor 820 mVppdiff. outputvoltage @ 2

MHzArea usage

(mm2)0.0036 0.005 0.005 0.083 0.026 -

FOM 24 0.26 0.27 0.46 0.35 26.4*

* Area considered to be 0.0036 mm2


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1. Khateb, F. “Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques forlow-voltage low-power analog circuits design”, Int. J. Electron. Commun. (AEU), 68(1),pp. 64-72 (2014).

2. Kulej, T. and Khateb, F. “Bulk-driven adaptively biased OTA in 0.18 µm CMOS”,Electron. Lett., 51(6), pp. 458-460 (2015).

3. Rezaei, F. and Azhari, S. J. “Ultra low voltage, high performance operational transcon-ductance amplifier and its application in a tunable Gm-C filter”, Microelectronics Journal,42, pp. 827-836 (2011).

4. Khateb, F., Khatib, N., Koton, J., et al. “Quadrature oscillator based on novel low-voltageultra-low-power quasi-floating-gate DVCC”, Scientia Iranica, doi: 10.24200/SCI.2017.4377(2017)

5. Grasso, A. D., Pennisi, S., Scotti, G., et al. “0.9-V Class-AB Miller OTA in 0.35-mCMOS With Threshold-Lowered Non-Tailed Differential Pair”, IEEE Trans. Circuits Syst.I, 64(7), pp. 1740-1747 (2017).

6. Chatterjee, S., Tsividis, Y. and Kinget, P. “0.5-V Analog Circuit Techniques and TheirApplication in OTA and Filter Design”, IEEE J. Solid-State Circuits, 40(12), pp. 2373-2387 (2005).

7. Kulej, T. “0.5-V bulk-driven CMOS operational amplifier”, IET Circuits Devices Syst.,7(6), pp. 352-360 (2013).

8. Rezaei, F. and Azhari, S. J. “Transconductor Linearization Based On Adaptive Biasingof Source-Degenerative MOS Transistors”, Circuits Syst Signal Process, 34, pp. 1149-1165(2015).

9. Rezaei, F. and Azhari, S. J. “A new controllable adaptive biasing linearization techniquefor a CMOS OTA and its application to tunable Gm-C filter design”, MicroelectronicsJournal, 46, pp. 810-818 (2015).

10. Meghdadi, M. and Sharif Bakhtiar, M. “Minimum power Miller-compensated CMOSoperational amplifiers”, Scientia Iranica, 21(6), pp. 2243-2249 (2014).

11. Azcona, C., Calvo, B., Celma, S., et al. “Low-Voltage Low-Power CMOS Rail-to-RailVoltage-to-Current Converters”, IEEE Trans. Circuits Syst. I, 60(9), pp. 2333-2342 (2013).

12. Abdelfattah, O., Roberts, G. W., Shih, I., et al. “An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range”, IEEE Trans. Circuits Syst.I, 62(10), pp. 2380-2390 (2015).

13. Ferreira, L. H. C., Pimenta, T. C. and Moreno, R. L. “An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail Input/Output Swing”, IEEE Trans. CircuitsSyst. II, 54(10), pp. 843-847 (2007).

14. Ferreira, L. H. C. and Sonkusale, S. R. “A 60-dB Gain OTA Operating at 0.25-V PowerSupply in 130-nm Digital CMOS Process”, IEEE Trans. Circuits Syst. I, 61(6), pp. 1609-1617 (2014).

15. Khateb, F., Kulej, T. and Vlassis, S. “Extremely Low-Voltage Bulk-Driven TunableTransconductor”, Circuits Syst Signal Process, 36(2), pp. 511-524 (2017).

16. Kumngern, M. and Khateb, F. “0.5 V fully differential current conveyor using bulk-driven quasi-floating-gate technique”, IET Circuits Devices Syst., 10(1), pp. 78-86 (2016).

17. Mobarak, M., Onabajo, M., Martinez, J. S., et al. “Attenuation-Predistortion Lineariza-tion of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Ap-plications”, IEEE J. Solid-State Circuits, 45(2), pp. 351-367 (2010).

18. Rezaei, F. and Azhari, S. J. “Ultra Low-voltage, Rail-to-Rail Input/output Stage Oper-ational Transconductance Amplifier (OTA) With High Linearity and Its Application in aGm-C Filter”, 11th Int’l Symposium on Quality Electronic Design (ISQED), pp. 231-236(2010).

19. Tsividis, Y. and Mcandrew, C. “Operation and Modeling of the MOS Transistor”, 3thEdn., Oxford University Press, New York, USA (2011).

Fig. 1 Test circuits for simulation of (a) gmb and (b) rdsFig. 2 gmb, rds and intrinsic gain (gmb × rds) for PMOS transistor operatingat 0.3 V with four length values.

16 Farzan Rezaei

Fig. 3 Proposed OTA.Fig. 4 Layout of proposed OTA.Fig. 5 Third-order low-pass Gm-C filter.Fig. 6 Filter layout.Fig. 7 Post-layout simulation of transconductance versus differential inputvoltage.Fig. 8 Post-layout simulation of magnitude of differential output voltage.Fig. 9 Post-layout simulation of input referred voltage noise.Fig. 10 Post-layout simulation of THD of OTA’s output current. Fig. 11 MonteCarlo simulation results of OTA’s THD. Fig. 12 Post-layout simulation of mag-nitude response of Gm-C filter. Fig. 13 Post-layout simulation of filter’s IIP3.Table 1 Aspect ratio of transistors.Table 2 Simulation results of proposed OTA.Table 3 Monte Carlo simulation results for 100 runs.Table 4 Main properties of proposed Gm-C filter.Table 5 Proposed OTA post-layout simulation results, compared with similarworks in literatures.

Biography

Farzan Rezaei received M.Sc. and Ph.D. degrees from Iran University of Science and

Technology, Tehran, Iran, respectively in 2009 and 2015. He is currently with the Department of

Electrical and Computer Engineering, University of Kashan, Iran, where he holds the position of

Assistant Professor. His research interest is the design of integrated circuits for communication

and biomedical applications.

0.3v tunable ota and gm-c filter in 0.13 m...

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