060216 icworkshop synthesis

8/3/2019 060216 ICworkshop Synthesis

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Graduate Institute of Electronics Engineering, NTU

SynopsysSynopsys Synthesis OverviewSynthesis Overview

Ben

2006.02.16


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pp. 2

OutlineOutlineIntroduction

Setting Design EnvironmentSetting Design Constraints

Synthesis Report and Analysis


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pp. 3

What is SynthesisWhat is SynthesisSynthesis = translation + optimization


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Logic Synthesis OverviewLogic Synthesis Overview

no timing info.

timing info.


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pp. 5

SynopsysSynopsys Related FilesRelated Files

Note

These 3 files are always read in the same order.

Any repeated command can overridethe previous one.

Set path and environment variables and license check.cshrc

Three distinct files are read and executed when DC is

invoked1. system-wide (do not modify):

(e.g. $SYNOPSYS/admin/setup/)

2. Users home directory (e.g. ~think/)

3. Users current working directory (e.g. ~think/dv/)

.synopsys_dc.setup

Set X terminal display variables.Xdefault

PurposeFiles


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pp. 6

Synthesis Design FlowSynthesis Design Flow

Specification

RTL Coding Prepare

Setting Design Environment

Setting Design Constraint

Compile Design

Analysis

CellLibrary

Gate-level Netlist

Develop the HDL design descriptionand simulate the design description to

verify that it is correct. Set up the .synopsys_dc.setup file.

Set the appropriate technology,synthetic, and symbol libraries, targetlibraries, and link libraries.

Set the necessary compilation options,

including options to read in the inputfiles and specify the output formats.

Read the HDL design description.

Define the design. Set design attributes

Define environmental conditions

Set design rules

Set realistic constraints (timing andarea goals)

Determine a compile methodology


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Setting Design EnvironmentSetting Design Environment


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Setting Design EnvironmentSetting Design Environment Setting Operating Environment

Setting Input Driving Strength

Setting Output Loading

Setting Input/Output Delay

Setting Wire Load Model


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Setting Operating EnvironmentSetting Operating Environment Attributes/Operating Environment


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pp. 10

Setting Operating ConditionSetting Operating Condition Attributes/Operating Environment/Operating Condition

dc_shell> set_operating_conditions slow


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Setting Input Drive ImpedanceSetting Input Drive Impedance Attribute/Operating Environment/Drive Strength


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Setting Input Drive ImpedanceSetting Input Drive Impedance Also can be set using

drive_of command

Example: (P2A cell output)


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Setting Output LoadingSetting Output Loading Attribute/Operating Environment/Load


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Setting Output LoadingSetting Output Loading Also can be set using load_of:

Example: (bufferd1 cell input)


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Setting Input DelaySetting Input Delay Select input ports

Attributes/Operating Environment/Input Delay


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Setting Output DelaySetting Output Delay Select output ports

Attributes/Operating Environment/Output Delay


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pp. 17

Setting Wire Load ModelSetting Wire Load Model Wire load model estimates wire capacitance based on chip area & cell

fanout

Setting this information during compile in order to model the designmore accurately

Attributes/Operating Environment/Wire Load


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Setting Design ConstraintsSetting Design Constraints


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pp. 20

Setting Design ConstraintsSetting Design ConstraintsOptimization Constraints

Basic clock constraints concept

Constraints & STA for Special Circuit

Constraints for Area

Design Rule Constraints

Final check constraints before compile


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pp. 21

Define Clock SpecificationDefine Clock SpecificationWhat should be defined?

Period

Waveform

Uncertainty

Skew

Latency

Source latency (option)

Network latency

Transition Input transition

Clock transition


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Specify Clock ConstrainsSpecify Clock Constrains Select clock port

Attributes/Clocks/Specify creat_clock: define your clocks

waveform & respect the set-up timerequirements of all clocked flip-flops

creat_clock clk-period 50 -waveform {0 25}

set_fix_hold: respect the hold timerequirement of all clocked flip-flops

set_fix_hold clk

set_dont_touch_network: do not re-

buffer the clock network set_dont_touch_network clk


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Constraints & STA for Special CircuitConstraints & STA for Special CircuitWhat should be noticed?

Multicycle Path

Clock Gating Technique

Latch-Based & Timing Borrow Analysis

False Path

set_case_analysis

Multiple Clocks Overlapping


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MulticycleMulticycle PathPath

To define setup multiplier 2 for the path from FF1 to

FF2 but maintain a hold multiplier 0, use command:

set_multicycle_path 2 -from FF1 -to FF2


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pp. 25

False PathFalse Path A false path is a timing path that cannot propagate a signal, or a path

we wish to ignore timing constraints.

The set_false_pathcan be used to disable timing-based synthesis on a

path-by-path basis It is useful for:

Constraining asynchronous paths

Constraining logically false paths


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Setting Area ConstraintSetting Area Constraint Attributes/OptimizationConstraints/Design Constraints

Area Unit : gates


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Design Rule ConstraintsDesign Rule ConstraintsDesign rules cant be violated at any cost,

even if it will violate the timing and area goal.

Three kinds of design rule constraint are set:

set_max_transition

set_max_fanoutset_max_capacitance


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Check DesignCheck Design After you set up the deign attributes & design

constraints, we recommend the next step is to check

design Analysis/Check Design

The warning message is called multiple design

instance, it results from that you use the same HDLdescription to represent more that one designinstance

How to handle ?

dont_touch

ungroup

uniquify


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Method 1:Method 1: dont_touchdont_touch Procedures

Constrain the block

Compile the block Select the multiple

design instances block

Attributes/Optimization

Directives/Design& setthe Dont Touch button

Compile the wholedesign using hierarchy

compile


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Method 2: UngroupMethod 2: Ungroup Procedures

Select the multiple designinstances block

Attributes/OptimizationDirectives/Design& set theUngroup button

Compile whole design usinghierarchy compile

Remove a single level ofhierarchy

Does not preserve thehierarchy

Take more memory Take more compile time

G d I i f El i E i i NTU


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pp. 33

Method 3:Method 3: UniquifyUniquify

Create a unique design file for

each instance May select one cell or entire

design hierarchy to be uniquify

Allow design to be customized to

its interface If the environment varies

significantly, use uniquifyratherthan compile+dont_touch

Uniquifyuses more memory andcause longer compile time thancompile+dont_touch

Select the most top design

of the hierarchy Edit/Uniquify/Hierarchy

G d t I tit t f El t i E i i NTU


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Multiple Design Instance (summary)Multiple Design Instance (summary) Use dont_touch, ungroup, uniquify to fix it

The easiest way is uniquify, but needs much memory

& compile time

If you want to preserve the hierarchy & sourcesharing, use dont_touch

If you want your design to have the BESTresult,recommend to use ungroup, but it needs the mostmemory and compile time

Graduate Institute of Electronics Engineering NTU


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Check Constraints & AttributesCheck Constraints & Attributes Use the following reports to check constraints & attributes

before compiling

Analysis/Report



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Save Constraints & AttributesSave Constraints & AttributesSave attributes & constraints setting as the

design setup file in dc_shell command format,use File/Save Info/Design Setup



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Execute Script FileExecute Script FileExecute dc_shell command script file, use

Setup/Execute Script


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Synthesis Report and AnalysisSynthesis Report and Analysis



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g g

pp. 40

ReportReport Analysis/Report

From report and analysis, you can find the set attributes and

the results after optimization

Attribute reports

All attributes, clock, port,

design, net

Analysis reports

Area, hierarchy, constraints,

timing, point timing



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pp. 41

Timing ReportTiming Report



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Analyze Circuit with SchematicAnalyze Circuit with Schematic To determine the time the signal arrived at pin which is selected

in the schematic

Analysis/Show Timing



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Analyze Circuit with SchematicAnalyze Circuit with Schematic To determine the net load which selected in the schematic

Analysis/Show Net Load



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Save DesignSave Design Save your design in verilog format, run Verilog gate-level simulation,

and we will use Verilog In interface to translate it into OPUS databasefor place & route

If you cant Verilog In, please check assign problem

if there is any assignment problem, choose the block & use thedc_shell command as follow to fix it

set_fix_multiple_port_nets -all -buffer_constants

compile -map_effort medium



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GateGate--Level Simulation (Verilog)Level Simulation (Verilog) Write out gate-level netlist

File/Save AsVerilog (for File format)

dc_shell> write -format verilog hierarchy -output chip.vg Get SDF

File/Save InfoDesign timingSelect chip.sdf

dc_shell> write_sdf version 1.0 -context verilog chip.sdf

Modify your testbench file$sdf_annotate (the_SDF_file_name, top_module_instance_name);

Simulation using Verilog-XL

>> Verilog chip.vg testbench.v v cell_model.v

Grad ate Instit te of Electronics Engineering NTU


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Design ExampleDesign Example

Ben

2006.02.16



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pp. 47

SynopsysSynopsys Design Vision (GUI) /Design Vision (GUI) /

Design Compiler (text mode)Design Compiler (text mode)

Unix% dv dcsh_mode &

Unix% dc_shell



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ReadRead VerilogVerilog FileFile

read -format verilog {"Lab1_alu.v"}



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Schematic viewSchematic view Synopsys Design analyzer will translate verilog code into G-tech

model. Double click the icon ALU, and click the right buttonthen choose Schematic view. We can get the G-tech MAP



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pp. 50

Symbol viewSymbol view Or you can create a symbol view by click on the following symbol

view button. The symbol view is as the right window



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Set Clock (1/2)Set Clock (1/2) Attributes-Specify Clock



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Set Clock (2/2)Set Clock (2/2) Specify the clock as period 10ns. (100 MHz). Dont forget to

select dont touch network and fix hold

create_clock -name "clk" -period 10 -waveform {"0" "5"} {"clk"}set_dont_touch_network find( clock, "clk")set_fix_hold clk



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Operating ConditionOperating Condition set_operating_conditions "typical" -library "typical"



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WireloadWireload ModelModel set_wire_load_model -name "ForQA" -library

"typical"

set_wire_load_mode "segmented"



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Operating EnvironmentOperating Environment Select inputA in the Symbol View and click Attribute-

operating environment-input delay. Set 2.5ns input delay.

set_input_delay -clock clk 2.5 inputA[*]set_input_delay -clock clk 3.8 inputB[*]

set_input_delay -clock clk 4.5 instruction[*]set_input_delay -clock clk 5.2 reset

set_output_delay -clock clk 8 alu_out[*]



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Area &Area & FanoutFanout & Transition& Transition Click Attribute-

optimization Constraints-Design constraints. Set

max area is 0. Max fan-out is8. max transition is 1.

set_max_area 0set_max_fanout 8 find (design, ALU)set_max_transition 1 find (design, ALU)



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Compile DesignCompile Design Click Design-Compile Design. Click OK, start to optimize

ALU

compile -map_effort medium



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ReportReport

report_timing -path full -delay max -max_paths 1 -nworst 1report_power

report_area -nosplit



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Save FilesSave Files Save gate-level netlist. Select File->Save As Save your design. Select File-Save

Save the timing information. Select File-Save Info-Design

Timing, choose sdf format.

Save script file with the constraints you have made. Usewrite_script > script_file command or File-Save Info-Design Setup button.

Re-run all steps automatically. Use include script_filecommand or File-Execute Script button.

write -format verilog -hierarchy -output "ALU_s.v" find (design, ALU)write -format db -hierarchy -output "ALU_s.db" find (design, ALU)write_sdf ALU_s.sdf



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gate level simulationgate level simulation Before gate level simulation,

$sdf_annotate(top_design.sdf, top_design)

must be added after initial in testbench `timescale 1ns/10psmust be added in the 1st line of

testbench

//RTL simulation

Unix% verilog testfixture.v

//gate level simulation

Unix% verilog testfixture_vg.v v umc18.v


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060216 icworkshop synthesis

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