Optimization of Spanning Tree Adders

報告者曾俊雄  賴韋志  巫祈賢 

OverviewCompare designs of spanning tree adders in terms of delay complexity power consumption

Spanning tree adders is an existing category of adders, this paper does not focus on inventing new spanning tree adders but performing experiments on several possible configuration of spanning tree adders.

Introduction to several adders

Why spanning tree adders are needed?

Experimental result

Conclusion & future work

AgendaIntroduction to Adders & Problem Statement

Spanning Tree Adders

Result & Conclusion

Introduction to Adders & Problem Statement

Spanning Tree Adders

Result & Conclusion

Introduction to Adders & Problem Statement

source: http://en.wikipedia.org/wiki/Adder_(electronics)

Very brief introduction on several existing adders: ripple carry adders carry skip adders carry look ahead adders tree structured adders

Brent-Kung Spanning Tree Ling Han-Carlson Kogge-Stone

Very brief introduction on several existing adders: ripple carry adders carry skip adders carry look ahead adders tree structured adders

Brent-Kung Spanning Tree Ling Han-Carlson Kogge-Stone

Propagation DelayBasically, the performance of adders are evaluated with propagation delay (in this paper)

source: http://www.seas.upenn.edu/~ese201/lab/CarryLookAhead/CarryLookAheadF01.html

Propagation Delay: also called gate delay, the time difference between the change of input and output signals.

Ripple Carry AddersGoal: the adder should be able to compute

the sum of more than 1 bits Idea: just chain several adders together

source: http://en.wikipedia.org/wiki/Adder_(electronics)

Pros & ConsPros:straight forward, easy to implement low power consumption, low resource

source: D.J.Kinniment, J.D.Garside, B.Gao, A comparison ofPower Consumption in Some CMOS Adder Circuits. In:Proceedings of the Fifth International WorkshopPATMOS-‘95, Oldenburg, Germany, ISBN 3-8142-0526-X, pp. 106-118.

Cons:slow (high propagation delay)

a 32-bits adder requires 31 carry computations

source: http://en.wikipedia.org/wiki/Adder_(electronics)

Carry look ahead addersproposed by Weinberger and Smith in 1958

source: http://en.wikipedia.org/wiki/Carry_look-ahead_adder

carry look ahead adders work by creating “Propagate” and “Generate” signals for each bit

Propagate: controls whether a carry is propagated from lower bits to higher bits

Generate: controls whether a carry is generated

a 4-bits carry look ahead adder

source: http://www.seas.upenn.edu/~ese201/lab/CarryLookAhead/CarryLookAheadF01.html

Pros & ConsPros: faster than ripple-carry adders, since some

computation can be done in advance

for example, part of C4 can be pre-computed after C0, P0, G0 are known

Cons:much more complicated when > 4 bits (

http://www.seas.upenn.edu/~ese201/lab/CarryLookAhead/CarryLookAheadF01.html)

the carry look ahead block requires gates with more than 2 input, which may cause efficiency problems (according to Megha Ladha; Earl E. Swartzlander, Jr )

AlternativesAlternatives: improved carry look ahead adders: Ling

adders tree-style adders to decrease input numbers

for each level:Kogge-Stone AdderBrent-Kung AdderHan-Carlson AdderSpanning Tree Adder

Kogge-Stone Adder

Brent-Kung Adder

source: http://www.acsel-lab.com/Projects/fast_adder/adder_designs.htm

Introduction to Adders & Problem Statement

Spanning Tree Adders

Result & Conclusion

Spanning Tree Adder (STA)Spanning tree adder use minimum number of multi-input gates Hybrid adder

Manchester Carry Chain (MCC) use ripple carries Propagate rapidly Size of MCC

is a trade of# of inputs# of levels

MCC

32-bit STA

STA based on MCCGi:j=MCC2(Gi:k-1, Gk:j, Pi:k-1, Pk:j)

Gi:j=MCC3(Gi:k-1, Gk:m-1, Gm:j, Pi:k-1, Pk:m-1, Pk:j)

Ci=G0:i-1

Carry Select Adder (CSA)Two sum outputs: Assumed carry input as 0 Assumed carry input as 1

# of MCC level is decided by the size of final stage CSA m-bits wide CSA Require Cm, C2m, C3m…

carry select adder

Final stage adder: if m is large carry select adder takes more time if m is mall need more MCC levels

8-bits wide carry select adder4 sum outputs

Introduction to Adders & Problem Statement

Spanning Tree Adders

Result & Conclusion

Main Comparion16-bit vs. 32-bit adders

CLA vs. Spanning tree adders

4-bit, 8-bit, 16-bit RCA vs. CSA

Measure: Delay, complexity, power consumption

Delay and power consumption are performed with Synopsys and Cadence

16-bit vs. 32-bit Adders

32-bit spanning tree

16-bit spanning tree

Size of CSA ↑: Delay of MCC ↓, CSA ↑

4-bit, 8-bit, 16-bit RCA vs. CSA - Delay

16 and 32-bit spanning tree with CSA and RCA in final stage

Delay: Except 4-bit module, CSA is better

4-bit, 8-bit, 16-bit RCA vs. CSA - Complexity

16 and 32-bit spanning tree with CSA and RCA in final stage

Complexity: Almost the same

4-bit, 8-bit, 16-bit RCA vs. CSA - Power Consumption

16 and 32-bit spanning tree with CSA and RCA in final stage

Size of Final Adders ↑: Power Consumption ↓

CLA vs. Spanning tree adders - Delay

16 and 32-bit CLA and Optimum Spanning Tree(OST)

Ratio of Delay: 32bit decreases more

CLA vs. Spanning tree adders - Complexity

16 and 32-bit CLA and Optimum Spanning Tree(OST)

Ratio of Complexity: 32bit increases less

CLA vs. Spanning tree adders - Power Consumption

16 and 32-bit CLA and Optimum Spanning Tree(OST)

Ratio of Power Consumption: Almost the same

ConclusionPerformance: In 16-bit Spanning tree adder, 4-bit, RCA and

CSA are the same In 32-bit Spanning tree adder, 8-bit above,

RCA is betterSpanning tree is more ideal for larger size.

Future WorkUse transistor to design final adders and MCC blocks

Sized for optimum performance

Use transistor multiplexer instead of gate level multiplexer

Some Others – IC Design

Language level: Like C language

Gate level: Assembly language

Transistor level: Machine code