07 ff registers counters.pdf

School of Electrical Engineering and Informatics ITB, 2010, Arry Akhmad Arman 1

Chapter 7

Flip-Flops, Registers,

and Counters,

Arry Akhmad ArmanSchool of Electrical Engineering and Informatics

Institut Teknologi Bandung

Last Update : September 2010


Basic Understanding

7.07.0


Types of Digital Circuit

Digital Circuit

SeSequentialDigital Circuit

SeCombinationalDigital Circuit

SeAsynchronous

SeSynchronous


Combinational vs Sequential Circuit (1)

4

Combinational

Circuit

Fix output for

certain input

combination,

represented by

Truth Table

Sequential

Circuit

NO Fix output

for SAME input

combination.


Combinational vs Sequential Circuit (2)

5

Combinational

Circuit

No Memory!

No Feedback

line!

Sequential

Circuit

There is

Memory!

There is

Feedback line!

Dinamic

characteristic,

Represented by

STATE DIAGRAM!

Static

characteristic,

Represented by

TRUTH TABLE!


States in Sequential Circuits

Rangkaian

Sekuensial

Sinkron

A

B

C

A(H)

B(H)

C(H)

A B C0 1 00 1 11 0 01 0 11 1 01 1 10 0 00 0 1

waktu PRESENT STATE pada suatu saat

PREVIOUS STATE

NEXT STATE

Variabel-variabel STATE

Timing Diagram


Memory Element

in Sequential Circuit

Memory is an important element in Sequential Logic Circuit

Reset

Set On Off Sensor Memory

Element Alarm


Type of Memories[different input lines]

8

Memory

QMemory

QJ

K

Memory

QJK

ClockMemory

QJK

Clock

Preset

Clear


Memory Implementation

Simple,

Uncontrolled

Controlled

Memory


Basic Latch

7.1


Simple Controllable

NOR Memory

Q=0

if Reset=1

Q=1

if Set=1


NOR MemoryS R Qa Qb0 00 11 01 1

0/11/00 11 00 0

(a) Circuit (b) Truth table

Time

1

0

1

0

1

0

1

0

R

S

Qa

Qb

Qa

Qb

?

?

(c) Timing diagram

R

S

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

(no change)


Gated SR Latch,

Flip-Flop

7.27.2

7.7


Gated SR Latch

(a) Circuit

R

Clk

Q

Q

S

1

0

1

0

1

0

1

0

1

0

Time

(c) Timing diagram

?

?

S R

x x

0 0 0 1 1 0

Q(t ) (no change)

0 1

Clk

0 1 1 1

1 1 1

Q t 1 + ( ( ( ( ) ) ) )

Q(t ) (no change)

x

(b) Truth table

Q

Q

R

S

R

S

Clk Clock!

S or R active if

clock active

Previous

NOR Memory


Gated SR Latch with NAND Gates

Gated Latch is a basic latch that includes input gating and a control input signal.


Gated D Latch (D Flip-Flop)

While clock active,Q always follows D (D transparent to Q)

Clk D Q(t+1)

0 X Q(t)

1 0 0

1 1 1


Gated T Latch (T Flip-Flop)

Notes:Dalam CPLD MAX7000terdapat configurable FFyang dapat diset menjadiD-FF atau T-FF

Clk T Q(t+1)

0 X

1 0

1 1 )(tQ)(tQ)(tQ

When clock active and T

active for long duration,

there is an oscillation in Q

output!


Gated JK Latch (JK Flip-Flop)

QKQJD +=

Clk J-K Q(t+1)

0 X X

1 0 0

1 0 1 0

1 1 0 1

1 1 1 )(tQ

)(tQ)(tQ


Effects of Propagation Delays

tsu = setup timeth = hold time

Typical CMOS valuestsu = setup time = 3nsth = hold time = 2 ns

t sut h

Clk

D

Q

During tsu+th, D should be stable


Master Slave D Flip-Flop

Pada FF biasa, perubahan output Q

selalu dipengaruhi input selama

CLOCK aktif.

Pada Master Slave D-FF, digunakan

2 buah FF dengan clock yang saling

komplemen.

Pada saat Clock aktif, D

mempengaruhi Qmaster, tetapi tidak

mempengaruhi Qslave.

Pada saat clock tidak aktif, clock

untuk Ffslave menjadi aktif, sehingga

Qmaster diteruskan ke Qslave.


Edge-Triggered D Flip-Flop

Pada edge triggered FF,perubahan di sisi output hanya terjadi pada saatsisi naik/turun clock.

Pada negative edge triggered,perubahan terjadi pada saatclock berubah dari HV ke LV.

Pada positive edge triggered,perubahan terjadi pada saatclock berubah dari LV ke HV.


ComparisonPulse triggered

Risingedge triggered

Fallingedge triggered

Pulse trigger, ada

daerah transparan

Rising edge trigger

Falling edge trigger

Perhatikan standar

simbol untuk jenis

clock yang berbeda!


All Possibilities

23

Positive

Pulse

Trigger

Negative Pulse

Trigger

Rising Edge

Trigger

Falling Edge

Trigger

D-FFPositive Pulse

Trigger D-FF

Negative Pulse

Trigger D-FF

Rising Edge

Trigger D-FF

Falling Edge

Trigger D-FF

T-FFPositive Pulse

Trigger T-FF

Negative Pulse

Trigger T-FF

Rising Edge

Trigger T-FFFalling Edge

Trigger T-FF

JK-FFPositive Pulse

Trigger JK-FF

Negative Pulse

Trigger JK-FF

Rising Edge

Trigger JK-FFFalling Edge

Trigger JK-FF


FF with Clear and Preset(Master Slave D-FF)

Preset untuk memaksaQ menjadi aktif (logika 1)

Clear untuk memaksaQ menjadi tidak aktif (logika 0)

(a) Circuit

D Q

Q

(b) Graphical symbolClear

Preset

Q

Q

D

Clock

Preset

Clear


FF with Clear and Preset(Positive Edge Triggered D-FF)

Preset untuk memaksaQ menjadi aktif (logika 1)

Clear untuk memaksaQ menjadi tidak aktif (logika 0)


Registers

7.87.8


Shift (only) Register

Data bit dari saluran input

ditransfer bit per bit, secara

bertahap dari kiri ke kanan

sampai ke saluran output.

Data ditransfer (digeser)

setiap kali clock aktif.


Parallel-Access Shift Register

Choose

mode!


C o u n t e r s

7.97.9


Asynchronous Counter(case: a three-bit up-counter)

T Q

Q Clock

T Q

Q

T Q

Q

1

Q 0 Q 1 Q 2

Clock

Q 0

Q 1

Q 2

Count 0 1 2 3 4 5 6 7 0 000 001 010 011 100 101 110 111 000


Asynchronous Counter(case: a three-bit down-counter)

T Q

Q Clock

T Q

Q

T Q

Q

1

Q 0 Q 1 Q 2

Clock

Q 0

Q 1

Q 2

Count 0 7 6 5 4 3 2 1 0

000 111 110 101 100 011 010 001 000


Synchronous Counter(case: a three-bit synchronous up-counter)

0 0 1 1

0 1 0 1

0 1 2 3

0 0 1

0 1 0

4 5 6

1 1 7

0 0 0 0 1 1 1 1

Clock cycle

0 0 8 0

Q 2 Q1 Q0 Q 1 changes

Q 2 changes

110

210

10

0

...

321

10

=

=

=

=

=

nQQQTn

QQQTQQT

QTT

L


Synchronous Counter(case: a four-bit synchronous up-counter)

T Q

Q Clock

T Q

Q

T Q

Q

1 Q 0 Q 1 Q 2

(a) Circuit

T Q

Q Q 3

Clock

Q 0

Q 1

Q 2

Count 0 1 2 3 5 9 12 14 0

(b) Tim

ing diag

ram

Q 3

4 6 8 7 10 11 13 15 1

All clock lines

connected

together


Inclusion of

Enable and Clear Capability

T Q

Q Clock

T Q

Q

T Q

Q

1 Q 0 Q 1 Q 2

T Q

Q Q 3

T Q

Q Clock

T Q

Q

Enable

Clear

T Q

Q

T Q

Q

Without

Enable and Clear

With

Enable and Clear


Synchronous Counter

with D Flip-Flop

01233

0122

011

000 1

QQQQDQQQD

QQDQQD

===

==


Counter with Parallel-Load Capability


Reset Synchronization

7.10


EnableQ 0 Q 1 Q 2

D 0 D 1 D 2 LoadClock

1 0 0 0

Clock

0 1 2 3 4 5 0 1

Clock

Count

Q 0

Q 1

Q 2

(a) Circuit

(b) Timing diagram

A modulo-6counterwith synchronousreset


EnableQ 0 Q 1 Q 2

D 0 D 1 D 2 LoadClock

1 0 0 0

Clock

0 1 2 3 4 5 0 1

Clock

Count

Q 0

Q 1

Q 2

(a) Circuit

(b) Timing diagram

A modulo-6counterwith synchronousreset

When Q0=1

and Q2=1 ,

Data=000

loaded


T Q

Q Clock

T Q

Q

T Q

Q

1 Q 0 Q 1 Q 2

(a) Circuit

Clock

Q 0

Q 1

Q 2

Count

(b) Timing diagram0 1 2 3 4 5 0 1 2

A modulo-6counterwith asynchronousreset

Reset

line!

Reset

(Clear)

line!


Other Types of

Counters

7.11


BCD Counter

Reset after 9,

enable next digit

to count.

Reset

after 9


BCD Counter

BCD

to

7-Segment

Converter

BCD

to

7-Segment

Converter


Type of 7-Segments


Common Anode & Cathode


Ring Counter(n-bit Ring Counter)

feedback line

When started, all FF

will be reset, except

the most left. Initial

=1000

1000 0100 0010 0001


Ring Counter: Another Choice!(4-bit Ring Counter)

1000

00

0100

01

0010

10

0001

11


Johnson Counter

0000 1000 1100 1110 1111 0111 0011 0001 0000

Feedback line

is taken from

complement line

0 8 12 14 15 7 3 1 0

One bit change

between sequence!


Using Storage Elements

with CAD Tools

7.12


Three Type of Storage elements

in a schematic


Gated D Latch

generated by CAD Tools


Implementation of

Fig 7.31

in CPLD


Timing Simulation


Instantiating of D-FF

from a package

STD_LOGIC ) ;

LIBRARY ieee ;USE ieee.std_logic_1164.all ;LIBRARY altera ; USE altera.maxplus2.all ;

ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ;

Resetn, Presetn : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ;

END flipflop ;

ARCHITECTURE Structure OF flipflop IS BEGIN

dff_instance: dff PORT MAP ( D, Clock, Resetn, Presetn, Q ) ; END Structure ;


End of slides

07 ff registers counters.pdf

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