07/17/06 1 Preliminary Final Report: RapidIO Simulation Case Studies David Bueno July 17, 2006 HCS Research Laboratory, ECE Department University of Florida 07/17/06 2 Overview Set of case studies to study processor, network, and memory interfacing in a RapidIO-based system using realistic GMTI/SAR kernels with detailed modeling of processing and memory subsystems Models developed during Summer 05 internship serve as basis for improvements Models modified to change/cover sensitive information and calibrated to more closely resemble Chris testbed setup in some cases (e.g. 250 MHz RIO) Modeling environment allows us to change parameters, scale, and network architecture with a much greater degree of freedom than testbed Three main points of emphasis of case studies: Gain insight into tradeoffs in shared interface between processor/network/memory Greater understanding of SBR processing/network requirements and optimal system configuration Quantify RapidIO latency and examine methods of improving latency and jitter for critical data 07/17/06 3 Baseline System Architecture Architecture similar to previous GMTI/SAR experiments Large-scale system assumes fully radiation-hardened FPGAs or ASICs, or additional management software (not modeled) capable of handling SEUs in FPGAs (e.g. DM-like system, near future technology) 7 processor cards, 4 FPGAs (4 logical PEs) and 1 RapidIO switch per card, 28 physical and logical FPGAs total 4-switch network backplane card (9-port switches) Clos-like backplane with second stage only 3 additional ports available for redundant system controller or other external interfaces Key addition is System Controller which generates latency-sensitive data for each processing node at user-specified intervals Smaller-scale experiments also provided to show capabilities of current systems using TMRd FPGAs or a smaller number of rad-hardened ASICs 07/17/06 4 Major Improvements Several changes from previous SBR experiments: Computation time based on working preliminary RIO testbed implementation of GMTI kernels Detailed memory access model for SDRAM Models contention between processing elements and RIO interface SRAM access deterministic and considered part of measured computation time Support for measurement of latency-sensitive traffic with latency values based on Honeywell RapidIO implementation New scaling method allows GMTI simulation runtimes reduced from hours (overnight) to ~30 minutes Shrink data cube (and CPI) along pulses dimension for simulation, then scale reported results to full CPI size Verified accurate to