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1

Abstract— To regulate an output ac voltage in inverter systems

having wide input dc voltage variation, a buck-boost power

conditioning system is preferred. This paper proposes a novel

high efficiency quasi single-stage single-phase buck-boost

inverter. The proposed inverter can solve current shoot-through

problem and eliminate PWM dead-time, which leads to greatly

enhanced system reliability. It allows bidirectional power flow

and can use MOSFET as switching device without body diode

conducting. The reverse recovery issues and related loss of the

MOSFET body diode can be eliminated. The use of MOSFET

contributes to the reduction of switching and conduction losses.

Also, the proposed inverter can be operated with simple PWM

control and can be designed at higher switching frequency to

reduce the volume of passive components. The detailed

experimental results are provided to show the advantages of the

proposed inverter. Efficiency measurement shows that using

simple PWM control the proposed inverter can obtain peak

efficiency of 97.8 % for 1.1 kW output power at 30 kHz switching

frequency.

Index Terms— Buck-boost, dual-buck, efficiency, inverter,

MOSFET, reliability, switching cell, single-stage, Z-source.

I. INTRODUCTION

RADITIONALLY, for dc to ac power conversion, there

exist two converters: voltage source inverter (VSI) and

current source inverter (CSI) as shown in Fig. 1 [1-3], [5].

The VSI has only buck (or step-down) function and is

vulnerable to shoot-through (or arm short) problem caused by

electromagnetic interference (EMI) noise. Similarly, the CSI

has only boost (step-up) function and is vulnerable to

open-circuit (or arm open) problem caused by EMI. In order to

avoid the shoot-through problem, a finite dead-time in gate

signals is required for the VSI. Likewise, a finite overlap-time

is required for the CSI to prevent the open-circuit problem. The

dead-time or overlap-time causes output waveform distortion.

Output voltages of renewable energy sources change in a

wide range. To regulate an inverter output voltage in systems

having wide input dc voltage variation, a buck-boost power

This research was supported by the KEPCO under the project entitled by

“Demonstration Study for Low Voltage Direct Current Distribution Network in an Island” (D3080).

A. A. Khan, H. Cha, and H. F. Ahmed are with the School of Energy

Engineering, Kyungpook National University, 1370 Daegu, Korea (email: [email protected];[email protected];[email protected]

;).

J. Kim and and J. Cho are with the Korea Electric Power Corporation Research Institute, Daejeon, Korea (email:[email protected];[email protected]).

+_inV

or

dcI

or

(a) (b) Fig. 1. Traditional single-phase dc to ac inverters. (a) Voltage source inverter

(VSI). (b) Current source inverter (CSI).

conditioning system is preferred. The buck-boost inverters

(BBIs) are also used for plug-in hybrid electric vehicles,

uninterruptible power supplies, ac motor drives, and

bidirectional buck-boost rectifier. Fig. 2 shows a two-stage BBI

obtained by cascading a boost dc-dc converter with a VSI. It

requires a bulky intermediate power decoupling capacitor dcC ,

to decouple the power between the boost dc-dc converter and

VSI. Fig. 3 shows a two-stage BBI obtained by cascading a

buck dc-dc converter with a CSI. It requires a bulky input

inductor inL , which decreases the power density. Fig. 4 shows

qZ-source inverter (qZSI) [35] which can be viewed as quasi

single-stage BBI. It can obtain both the buck and boost

functions by placing impedance network between main power

source and inverter bridge [4-8]. It is immune to EMI noise and

has no shoot-through and dead-time problems. However,

during the boost operation it has high switch voltage and

current stresses (see Table I) which go against its efficiency,

and its attainable voltage gain is practically limited. In [9-10],

an active BBI is developed. It has the desired buck-boost

function by using more active switches in the output. However,

like the traditional VSI, it is not resistant to the shoot-through

problem at dc side and has commutation problem at ac side.

Therefore, finite dead-time has to be used at the dc side and

lossy snubber circuits have to be attached to switches at the ac

side in order to avoid the commutation problem. Alternatively,

as with conventional ac-ac converters, soft commutation

strategy has to be used for the switches at the ac side by sensing

output voltage polarity. The sensing technique increases

control complexity and decreases converter reliability and

quality of output waveforms.

For a power level at which the resistive conduction voltage

drop of MOSFET is lower than the nearly fixed voltage drop of

IGBT, the use of MOSFET is preferred because of its fast

switching and lower switching loss.

A Highly Reliable and High Efficiency Quasi

Single-Stage Buck-Boost Inverter Ashraf Ali Khan, Student Member, IEEE, Honnyong Cha, Member, IEEE, Hafiz Furqan Ahmed,

Juyong Kim, and Jintae Cho

T




2

inV

inL

5SinC

1S

2S

fL3S

4S

dcC

6S inD

Fig. 2. Boost type dc-dc converter followed by a VSI.

inV

6S

5S

inC

1S

2S

oC

3S

4S

dcC

inL

oL

inD

Fig. 3. Buck type dc-dc converter followed by a CSI.

2C

1S

2S

fL3S

4S

inV1C

1L 2L

inD

5S

Fig. 4. Quasi-Z-source inverter (qZSI).

The single-phase MOSFET based inverter called HERIC

inverter in [11-12] can reduce switching and conduction losses

with simple structure. However, it has the risk of MOSFET

failure due to reverse recovery of body diodes. The H5 and H6

inverters in [13] and [14], respectively, prevent the risk of

MOSFETs failure at the cost of more conduction losses. The

HERIC, H5 and H6 inverters have the risk of current

shoot-through in phase-legs. In [15], a reliable and MOSFET

based inverter called dual-buck inverter is proposed. The body

diodes of MOSFETs are prevented from conducting by use of

external diodes and reverse recovery problem of body diodes is

eliminated. The dual-buck inverter is immune from

shoot-through problem of voltage source, therefore eliminates

the dead-time.

However, all of the aforementioned inverters are buck type.

Therefore, in order to use these inverters in systems having

wide input voltage variation, an additional boost dc-dc

converter is cascaded with these inverters, as have been done

for the dual-buck inverter in [16]. In [17], a three-stage

buck-boost dc-ac inverter which can cover wide variation of

input dc voltage is proposed. It has three power stages

consisting of cascaded connection of a boost converter, buck

converter and line frequency inverter. In [18], a modified

three-stage MOSFET based BBI named ‘Aalborg inverter’

obtained by interchanging position of the buck and boost

converters in the BBI in [17] is proposed. It can save one

inductor and reduces the overall conduction loss of inductors.

In this paper, a new MOSFET based bidirectional quasi

single-stage single-phase BBI is proposed. It can provide a

regulated ac output voltage for wide input dc voltage variation

owing to its buck-boost capability, and can solve the limited

gain problem of the VSIs and CSIs. Unlike the conventional

two-stage BBI in Fig. 2, it does not require intermediate power

decoupling capacitor. The proposed inverter has no current

shoot-through problem and can eliminate the pulse width

modulation (PWM) dead-time, which lead to greatly enhanced

system reliability. The body diodes of MOSFETs do not

conduct in the proposed topology, which avoids the risk of

MOSFETs failure associated with the poor reverse recovery of

MOSFET body diode. By using power MOSFETs in

conjunction with externally selected fast recovery diodes, the

proposed inverter can realize high frequency and high

efficiency operation. The topology derivation, switching

strategies for buck and boost operations, operation principle,

and circuit analysis are given in the paper. A 1.1 kW hardware

prototype is tested and detailed experimental results are

provided to verify the advantages of the proposed inverter.

II. CIRCUIT TOPOLOGY OF THE PROPOSED BUCK-BOOST

INVERTER

MOSFET has such benefits as fast switching, low switching

loss and nearly resistive conduction voltage drop. However, it

has failure risk due to reverse recovery issues of body diode

especially in high voltage and hard switching applications.

Therefore, the use of MOSFET in the traditional hard switching

inverter is normally not suggested [37, 19-20]. For a power

level at which the resistive conduction voltage drop of

MOSFET is lower than the fixed voltage drop of IGBT, the use

of MOSFET as switching device is preferred for high frequency

and high efficiency operation, provided that the risk of

MOSFET failure due to reverse recovery of body diode is

prevented. The topologies of VSI [21-27], ac-dc rectifier [28],

and ac-ac converters [29-32, 36, 38] are implemented with

MOSFETs and external fast recovery diodes to obtain high

efficiency.

The dual-buck inverter patented by Xantrex technology [15]

is shown in Fig. 5. It uses four MOSFETs 1 4S S , four

external fast recovery diodes 1 4D D , and four split-phase

inductors 1 2a bL L . Due to the use of 1 4D D and 1 2a bL L ,

body diodes of the MOSFETs never conduct with this topology.

Therefore, the benefits of MOSFET can be achieved without

the reverse recovery issues of body diode. In addition, the

dual-buck inverter has no current shoot-through problem, thus

does not require dead-time. For these reasons, the dual-buck

inverter can be considered as one of the high reliability and high

efficiency inverter. The research on the dual-buck inverter has

been focused on the development of new topologies, efficiency

improvement, and PWM control [21-27]. All the topologies

developed with the dual-buck structure have step-down

function. In order to achieve the buck-boost operation, a boost

dc-dc converter is required in the front-end with dcC as

depicted in Fig. 6(a). Fig. 6(b) is a bidirectional BBI obtained

from Fig. 6(a) where the MOSFET and diode are replaced with

IGBTs to avoid the issues of MOSFET body diode during hard

switching.

Recently, novel ac-ac converters termed as switching cell

(SC) ac-ac converters are developed in [29]. The boost-type SC




3

ac-ac converter is shown in Fig. 7. Similar to the dual-buck

inverter and unlike the conventional ac-ac converters, this

converter is highly reliable because it has no current

shoot-through and dead-time problems. It can also obtain high

efficiency by using MOSFET as switching device. In addition,

it does not require lossy snubbers or current/voltage polarity

sensing modules for commutation. The research on the SC

ac-ac converters are focused on the development of new ac-ac

converter topologies, efficiency improvement, and magnetic

volume reduction [30-33, 36, 38].

Fig. 8 shows the circuit topology of the proposed quasi

single-stage BBI. It is a combination of the dual-buck and SC

structures. The dc input of the proposed inverter takes the

dual-buck structure and the ac output takes the SC ac-ac

structure. Similar to the qZSI and the dual-buck inverter, the

proposed inverter is very resistant to EMI noise’s misgating-on

or -off. However, as shown in Table I, unlike the qZSI, the

proposed inverter requires relatively low

current/voltage rating devices. The proposed inverter can be

designed with MOSFET, therefore, high frequency and high

efficiency operation can be realized. As shown in Fig. 8, each

switching device is connected in series with an external diode,

therefore no shoot-through current is possible in the proposed

inverter. The inductors 1 1 2 2, , ,a b a bL L L L split the phase legs

and serve as buck, boost and current limiting inductors. The

two capacitors 1C and 2C in the output are added to provide a

safe path for inductor currents when dead-time occurs in the

gate signals of ( 5 6,S S ) or ( 7 8,S S ) or ( 5 8S S ). They also

serve as both output filter capacitor and lossless snubbers

reducing the voltage spikes caused by the stray inductances in

the circuit layout.

The gate signal generation of the proposed inverter is shown

in Fig. 9. The switches 1 4S S are switched with simple

bipolar sinusoidal PWM (SPWM) scheme, and the switches

5 8S S are switched with simple complementary PWM

scheme. The gate signals of 1 4S S are obtained by comparing

a sinusoidal control signal sv with a carrier signal triv , and the

gate signals of 5 8S S are obtained by comparing a dc control

signal cV with triv .

III. OPERATION OF THE PROPOSED BUCK-BOOST INVERTER

The voltage spwmv produced by the input dc bridge

( 1 4S S ) for a given input voltage inV can be expressed as:

( )spwm inv MV sin t (1)

In (1), M is modulation index. The voltage gain of the output

ac bridge ( 5 8S S ) can be obtained the same as that of the

traditional boost-type ac-ac or dc-dc converter [29], [31] as:

1S

2D

1D

2S

1aL 3S

4D

3D

4S

2bL

1bL

LR ov+

-inC CoinV 2aL

Fig. 5. Dual-buck dc-ac inverter [15].

1S

2D

1D

2S

1aL 3S

4D

3D

4S

2bL

1bL

LR ov+

-

Co2aL

dcC

inV inC

inL

5S

inD

(a)

1S

2D

1D

2S

1aL 3S

4D

3D

4S

2bL

1bL

LR ov+

-

Co2aL

dcC

inVinC

inL

5S

6S

(b)

Fig. 6. Dual-buck dc-ac inverter cascaded with a boost dc-dc converter. (a) Unidirectional. (b) Bidirectional.

1S

2D

1D

2S

3S

4D

3D

4S

ov+ -

inL 1CL

oC

1C 2Cinv2CLinC

+

-

Fig. 7. Boost-type switching cell (SC) ac-ac converter [29].

1S

2D

1D

2S

3S

4D

3D

4S

5S

6D

5D

6S

7S

8D 8S

1C

2C

LR ov+

-

+

-

+

-

inV 1Cv

2Cv

1aL

2aL

1bL

1Li

2Li

+-

+ -

+- 7D

2bL+ -3Li

4Li

oi

inC

oC

Fig. 8. Proposed buck-boost inverter.

cV6 7S ,S

5 8S ,S

1 3S ,S

2 4S ,S

sv

triv1

0

-1

10triv

Fig. 9. Gate signal generation of the proposed inverter.




4

1

1

o

spwm

v

v D

(2)

where ov is the output ac voltage, and D is the duty ratio

defined as the ON time of switches 6 7,S S . From (1) and (2),

voltage gain of the proposed inverter can be expressed as:

( )1

o

in

v Msin t

V D

(3)

The voltage gain in (3) is plotted in Fig. 10. As shown in Fig.

10, the proposed inverter can operate both in buck and boost

modes based on the values of M and D. When inV is greater

than the peak ov , the proposed inverter operates in the buck

mode by keeping D=0 and adjusting M. When inV is lower

than the peak ov , the proposed inverter operates in the boost

mode by keeping M=1 and adjusting D.

A. Buck Operation

PWM strategy during the buck operation is depicted in Fig.

11. The switches 6 7,S S are always OFF and 5 8,S S are ON,

that is, D=0. The diodes 6 7,D D are reverse biased and

5 8,D D are forward biased. The equivalent circuit during the

buck operation is shown in Fig. 12. During the buck operation,

the proposed inverter reduces to the dual-buck inverter in Fig. 5

with only one extra MOSFET and diode conducting the main

current at a time. The inductors 1aL and 1bL conduct the main

current during the positive half-cycle of output current with the

direction shown in Fig. 13, and 2aL and 2bL conduct current

during the negative half-cycle of output current. During the

buck operation, the proposed inverter has two consecutive

modes as discussed below.

In the following mode analysis, all the inductors are

assumed to have an equal inductance, / 2L . Fig. 13 shows the

operation when the output current is positive and the same

analysis can be made for the negative half-cycle of current.

1) Mode 1 As shown in Fig. 13(a), the switches 1 3,S S are turned-on

and 2 4,S S are turned-off, thus the diodes 2 4,D D are reverse

biased. The current relation is given as follows:

1 3,S S

2 4,S S

5 8,S S

6 7,S S

svtriv

cV

t

t

t

t

t

Mode 1 Mode 2

Fig. 11. PWM strategy during buck operation.

1S

2D

1D

2S

3S

4D

3D

4S

5S

6D

5D

6S

7S

8D 8S

1C

2C

LR ov+

-

+

-

+

-

inV1Cv

2Cv

1aL

2aL

1bL

1Li

2Li

+-

+ -

+- 7D

2bL+ -3Li

4Li

oi

inC

Fig. 12. Equivalent circuit of the proposed inverter during buck operation.

1S

2D

1D

2S

3S

4D

3D

4S

5S

6D

5D

6S

7S

8D 8S

1C

2C

LR ov+

-

+

-

+

-

inV1Cv

2Cv

1aL

2aL

1bL

1Li

2Li

+-

+ -

+- 7D

2bL+ -3Li

4Li

oi

inC

(a)

1S

2D

1D

2S

3S

4D

3D

4S

5S

6D

5D

6S

7S

8D 8S

1C

2C

LR ov+

-

+

-

+

-

inV1Cv

2Cv

1aL

2aL

1bL

1Li

2Li

+-

+ -

+- 7D

2bL+ -3Li

4Li

oi

inC

(b)

Fig. 13. Buck operation of the proposed inverter. (a) Mode 1 (Mode 1 & 5 for

boost operation). (b) Mode 2 (Mode 2 & 4 for boost operation).

0.50 1M

0.5 10D

0D

1M

Boost Region

Buck Region

0.2

0.4

0.6

0.8

1

5

10

15

20

o

in

v

V

Fig. 10. Voltage gain of the proposed inverter.




5

1L in odi V v

dt L

(4)

2) Mode 2

As shown in Fig. 13(b), the switches 1 3,S S are OFF and

2 4,S S are ON, and the diodes 2 4,D D are forward biased due

to freewheeling action. The current relation is given as follows:

1L in odi V v

dt L

(5)

B. Boost Operation

During the boost operation, M is set to 1, and D is varied to

regulate ov . The switching states are shown in Fig. 14. In Fig.

14, cV is defined as (1 cV ) and it is the dc control signal that

determines the duty cycle of switches 5 8,S S , that is, (1-D).

Fig. 14(a) shows the switching signals when c sV v (or when

the instantaneous output voltage is lower than inV ). Fig. 14(b)

shows the switching signals for s cv V . In this paper, the

voltages before and after inductors are designated as dc-bridge

and ac-bridge voltages, respectively. The dc-bridge voltage is

varied between inV and inV , whereas the ac-bridge voltage

is varied between 0 and ov . The inductors ( 1aL and 1bL ), and

( 2aL and 2bL ) are in series, therefore the voltage across 1aL

(or 1bL ) becomes / 2inV , / 2inV , ( ) / 2in oV v , and

( ) / 2in oV v . Similarly, during the negative half-cycle, the

voltage across 2aL (or 2bL ) becomes / 2inV , / 2inV ,

( ) / 2in oV v , and ( ) / 2in oV v . Modes 1-4 for in oV v are

shown in Fig. 14(a), and modes 5-8 for in oV v are shown in

Fig. 14(b).

1) Mode 1&5

These modes are the same as mode 1 of the buck operation

shown in Fig. 13(a).

2) Mode 2&4

These modes are the same as mode 2 of the buck operation

shown in Fig. 13(b).

3) Mode 3&7

In mode 3 and 7, as shown in Fig. 15(a), the switches

1 3 5, ,S S S , and 8S are OFF and the switches 2 4 6, ,S S S , and

7S are ON. The inductor current decreases with a slope as:

1L indi V

dt L (6)

4) Mode 6&8

In mode 6 and 8, as shown in Fig. 15(b), the switches

1 3 6, ,S S S , and 7S are ON, and 2 4 5, ,S S S , and 8S are OFF.

The inductor current rises with a slope as:

1 3,S S

2 4,S S

5 8,S S

6 7,S S

cV

t

t

t

t

t

Mode 1 Mode 2 Mode 3 Mode 4

trivsv

(a)

1 3,S S

2 4,S S

5 8,S S

6 7,S S

t

t

t

t

t

Mode 5 Mode 6 Mode 7 Mode 8

trivsv cV

(b)

Fig. 14. PWM strategy during boost operation. (a) in oV v (or c sV v ). (b)

in oV v (or c sV v ).

1S

2D

1D

2S

3S

4D

3D

4S

5S

6D

5D

6S

7S

8D 8S

1C

2C

LR ov+

-

+

-

+

-

inV1Cv

2Cv

1aL

2aL

1bL

1Li

2Li

+-

+ -

+- 7D

2bL+ -3Li

4Li

oi

inC

(a)

1S

2D

1D

2S

3S

4D

3D

4S

5S

6D

5D

6S

7S

8D 8S

1C

2C

LR ov+

-

+

-

+

-

inV1Cv

2Cv

1aL

2aL

1aL

1Li

2Li

+-

+ -

+- 7D

2bL+ -3Li

4Li

oi

inC

(b)

Fig. 15. Boost operation of the proposed inverter. (a) Mode 3&7. (b) Mode

6&8.




6

1L indi V

dt L (7)

The following two modes show the operation of the

proposed inverter when dead- or overlap-time caused either by

purpose or by EMI noise’s misgating-on or -off occurs although

they are not the desired modes of operation of the proposed

inverter.

C. Overlap-time Mode

As shown in Fig. 16(a), when all the switches 1 8S S are

ON, the freewheeling diodes 1 8D D become reverse biased,

and the inductors 1( , ) 2( , )a b a bL L limit the shoot-through

current by providing opposition. Thus, when multiple switches

are turned-on simultaneously, there is no shoot-through current

problem. As a result, the dead-time in gate signals can be

eliminated and high quality output waveforms can be obtained.

D. Dead-time Mode

Similar to the overlap-time mode, when 1 8S S are all OFF

either by purpose or EMI noise as shown in Fig. 16(b),

1 8D D become forward biased. The capacitors 1C and 2C

provide safe path for inductor currents. Thus, when two or more

switches are turned-off simultaneously, the inductor current

finds safe path to flow.

IV. CONTROL STRATEGY AND PARAMETER DESIGN OF THE

PROPOSED INVERTER

A. Inductor Design

The inductors 1aL , 1bL , 2aL and 2bL are designed based

on their maximum current handling capacity and maximum

permitted current ripple. The maximum inductor current

.maxLI for output power oP occurs during the boost operation

with minimum input voltage ( .mininV ) and expressed as:

.max.min

oL

in

PI

V (8)

The maximum inductor current ripple .maxLi occurs

during the buck mode with maximum input voltage .maxinV .

Since the inductors 1aL and 1bL (or 2aL and 2bL ) are always

in series and the inductance of each inductor is defined as / 2L ,

the inductor current slope during mode 1 (see Fig. 13(a)) is

obtained as:

in oL V vdi

dt L

(9)

At zero crossing point, ov becomes zero and the ON-time of

1 3,S S becomes T/2. Thus, from (9), .maxLi is obtained as:

.max.max

2

inL

Vi T

L (10)

Where T is the switching period.

Consider that .maxLi is restricted to x% of .maxLI , i.e.,

.max .max%L Li x I . Thus, the required inductance is obtained

as:

.max

.max

.max .min

2 4 %

2 4 %

in

L

in in

o

VLT

x I

V VLT

x P

(11)

B. Capacitor Design

The capacitors 1C and 2C provide safe path for inductor

currents during dead-time, and they also serve as output filter

capacitors. If oC in Fig. 8 is removed, then 1C and 2C can be

designed to serve as output filter capacitor. In this paper, oC is

used as the main output filter capacitor, thus 1C and 2C can be

designed for the dead-time ( dt ) in gate signals of 5 8S S . The

sum of voltages across 1C and 2C is always ov regardless of

the operation modes. During dt , the current 1Li (=

3Li ) is

flowing through 1C (see Fig. 16(b)) when 0oi , and the

current 2Li (=

4Li ) is flowing through 2C when 0oi ,

respectively. Thus, the voltage ripples 1Cv and

2Cv of 1C

1S

2D

1D

2S

3S

4D

3D

4S

5S

6D

5D

6S

7S

8D 8S

1C

2C

LR ov+

-

+

-

+

-

inV1Cv

2Cv

1aL

2aL

1bL

1Li

2Li

+-

+ -

+- 7D

2bL+ -3Li

4Li

oi

inC

(a)

1S

2D

1D

2S

3S

4D

3D

4S

5S

6D

5D

6S

7S

8D 8S

1C

2C

LR ov+

-

+

-

+

-

inV1Cv

2Cv

1aL

2aL

1bL

1Li

2Li

+-

+ -

+- 7D

2bL+ -3Li

4Li

oi

inC

(b)

Fig. 16. Operation of the proposed inverter when dead- or overlap-time occurs

due to EMI noise. (a) Overlap-time. (b) Dead-time.




7

and 2C can be obtained as:

1

1

2

2

LC d

LC d

Iv t

C

Iv t

C

(12)

where C is the capacitance of 1C and 2C . The maximum

voltage ripples 1.maxCv and

2.maxCv occurs during the

boost mode when .mininV and .maxLI as given by (8).

Consider that 1.maxCv and

2.maxCv are restricted to

1 2.max .max, %C C ov v y v . To maintain these voltage

ripples, the capacitance is obtained as

.max

.min

%

( / )

%

Ld

o ind

IC t

y vo

P VC t

y vo

(13)

C. Rating of Semiconductor Devices

The voltage and current stress of MOSFETs and relevant

external diodes are the same, and the inductor currents

1 4L LI I flow through the switches. Therefore, the maximum

current stress for all switches is equal to .maxLI as given by (8).

The voltage stress of 1 4S S is inV , therefore the maximum

voltage stress of 1 4S S is determined by maximum input

voltage. On the other hand, the maximum voltage stress of

5 8S S is determined by maximum output voltage.

D. Modulation Strategy of the Proposed Inverter

Fig. 17 shows control block diagram of the proposed

standalone inverter. As shown, ov is sensed and fed into peak

voltage detector. The sensed peak output voltage oV is then

multiplied by (1 ) /D M to get oV for the ideal condition (i.e.,

D=0 and M=1). The resultant (1 ) /oD V M is compared with

reference voltage ( refV ) to determine the buck or boost

operating mode. The inverter operates in buck mode when

(1 ) /o refD V M V , and in boost mode when

(1 ) /o refD V M V .

During the buck operation, cV is zero, and oV is compared

with refV to generate the error signal eu , which is fed into

proportional-integral (PI) controller for compensation, and

the modulation index ( )M t is determined as follows,

( ) ( ) ( )p ref o i ref oM t k V V k V V dt (14)

where pk and ik are the proportional and integral gain of

the PI controller. During the buck operation, /ref inM V V .

The ( )M t is multiplied with sinusoidal signal sin( t) to

get sv which is compared with triv to generate the pulsating

signals for 1 4S S .

In boost mode, M is set to 1 and oV is compared with refV

to generate the error signal ev . The ev is fed into the PI

controller for compensation, and cV is determined

accordingly which is compared with triv to generate the

pulsating signals for switches 5 8S S .

( ) ( ) ( )c p ref o i ref oV t k V V k V V dt (15)

During boost operation, 1 /c in refV V V .

V. COMPARISON WITH THE CONVENTIONAL SINGLE-PHASE

BUCK-BOOST INVERTERS

The traditional cascaded buck-boost inverter (TCBBI), qZSI,

and cascaded dual-buck boost inverter (CDBBI) are shown in

Figs. 2, 4, and 6, respectively. Table I summarizes the basic

features of the proposed and the aforementioned single-phase

BBIs.

A. Comparison of Basic Functionality and Reliability

The TCBBI and CDBBI are two-stage inverters. The

proposed inverter, similar to the qZSI, is quasi single-stage.

The shoot-though duty cycle DZSI and modulation index M

are interdependent (i.e., M=1-DZSI) in the qZSI. Therefore, M

decreases with increase in DZSI (with increase in gain G),

which results in lower output power quality and higher

voltage stress on inverter bridge with poor utilization of

inverter bridge voltage. On the other hand, similar to the

TCBBI and CDBBI, the M and D are independent in the

proposed inverter. Therefore, the voltage gain of the

proposed inverter can be increased by increasing D while

keeping M to its maximum value (M=1), which results in

1S

2S

3S

4S

Proposed

SPWM

dcV

ov

Voltage peak

detection

(1 )?o ref

DV V

M

no

PWM

5S

6S

7S

8S

yesPI refV

oV

0set D

( )M t

PIrefV

oV

1set M

( )sin wt

( )cV D t

( )sv tinverter

eu ev

Buck mode Boost mode

Fig. 17. Control block diagram.




8

better power quality with better utilization of inverter bridge

voltage.

In the TCBBI and qZSI, current flow through body diodes of

switches. Therefore, they usually use IGBTs as switching

devices to avoid reverse recovery issues of MOSFET body

diode. In the proposed inverter, current does not flow through

body diodes of switches, therefore power MOSFETs can be

used as switching devices to utilize its benefits (see Fig. 20).

In the proposed inverter, external diodes are used for current

freewheeling. They can be selected with the features of

negligible reverse recovery loss and low forward voltage

drop to decrease the power loss and realize the use of higher

switching frequency.

The proposed inverter allows bidirectional power flow

without conducting body diodes of switches, and any short-

or open-circuit problems. For unidirectional power flow, the

boost dc-dc converter of the TCCBI and CDBBI can be

designed with MOSFET and external fast recovery diode.

For bidirectional power flow, to avoid the reverse recovery

issues of MOSFET body diode, the boost dc-dc converter

should be designed with IGBTs. Therefore, for hard

switching and bidirectional power flow, the boost dc-dc

converter of the TCBBI and CDBBI cannot benefit from high

speed MOSFETs.

The ZSI has start-up inrush current problem [33], which can

be solved with the qZSI. The TCBBI and CDBBI use boost

dc-dc converter which has the start-up inrush current

problem. The existence of uncontrollable range when the

output voltage of boost dc-dc converter is below the peak

value of the source voltage results in the start-up inrush

current [34]. The proposed inverter takes the structure of the

dual-buck inverter at the input side which is buck type,

therefore it has no start-up inrush current problem.

The TCBBI has current shoot-through problem and needs

dead-time. The proposed inverter, similar to the qZSI, does

not suffer from the shoot-through or open-circuit problem.

Therefore, it does not require dead time. The unidirectional

CDBBI (see Fig. 6(a)) does not require dead time. However,

for bidirectional power flow, the boost dc-dc converter has

the risk of current shoot-through due to the use of active

switches (see Fig. 6(b)). Thus, finite dead time is required

between 5S and 6S .

B. Voltage and Current Stresses of Switching Devices

From Table I, the switch voltage stresses normalized with

ôv for buck and boost modes are plotted in Figs. 18(a) and (b),

respectively. During the buck mode, only 1 4S S are switched

at high frequency in all inverters and the voltage stress of

1 4S S is equal to inV . Therefore, the voltage stress increases

as voltage gain (G) decreases. On the other hand, the 5 8S S in

the proposed inverter have lower voltage stress than the

switches in other three inverters because their voltage stress is

only determined by ôv (see Fig. 18(a)).

During the boost mode as shown in Fig. 18(b), 5 8S S of

the proposed inverter have the same voltage stress as that of all

the switches in the TCBBI and CDBBI, and lower than that of

switches in the qZSI. While the switches 1 4S S in the

proposed inverter have lower voltage stress than the switches in

all other three inverters and the difference becomes significant

with increase in gain G (as inV becomes lower).

During the buck operation, the current stress of switches in

the proposed inverter is ôi , which is the same as those of

1 4S S in the TCCBI, CDBBI, and qZSI. In the boost

operation, the current stress of switches in the proposed inverter

is inI , which is the same as those of the switches in the boost

dc-dc converter in the TCBBI and CDDBI while smaller than

that of in the qZSI.

1 6S SV

5 8S SV

1 5S SV

SxV Proposedinverter

SxV qZSI

SxVTCBBI

SxV CDBBI

1 6S SV 1 4S SV

Norm

aliz

ed s

wit

ch v

olt

age

stre

sses

ˆV oltage gain ( / )o inG v V

4

3.5

3

2.5

2

1.5

1

0.5

00.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

(a)

1

1 4S SV

1 5S SV

1 6S SV

1 6S SV

5 8S SV

SxV Proposedinverter SxVTCBBI

SxV qZSI SxV

CDBBI

Norm

aliz

ed s

wit

ch v

olt

age

stre

sses

1.5 2 2.5 3 3.5 4 4.5 5

2.5

2

1.5

1

0.5

0

ˆVoltagegain ( / )o inG v V

(b)

Fig. 18. Comparison of normalized switch voltage stresses of four inverters. (a) Buck mode. (b) Boost mode.

Proposedinverter

qZSI

Lfi

TCBBI

CDBBILfi

Lfi

( , )Lx a bi

( , )Lx a b

Lf

i

i

( , )Lx a b

Lf

i

i

( , )Lx a b

Lf

i

i

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1 1.5 2 2.5 3 3.5 4 4.5 5ˆVoltagegain ( / )o inG v V

Induct

or

curr

ent

ripple

Fig. 19. Ratio of inductor current ripple of the proposed inverter to the current

ripple of other inverters during boost mode.




9

TABLE I

COMPARISON OF THE PROPOSED AND CONVENTIONAL BUCK-BOOST INVERTERS

Parameters qZSI

(Fig. 4)

TCBBI

( Fig. 2)

CDBBI

(Fig. 6)

Proposed inverter

(Fig. 8)

Power conversion Quasi single-stage Two-stage Two-stage Quasi single-stage

Relation between M and D M=1-DZSI independent independent independent

Shoot-through risk

(unidirectional power

flow)

no yes no no

Reverse recovery issues of MOSFET body diode

(unidirectional power

flow)

yes yes no no

Independent selection of

active switches and

freewheeling diodes (unidirectional power

flow)

no no yes yes

No. of switches

(unidirectional power flow) 4 ( 1 4S S ) 5 ( 1 5S S ) 5 ( 1 5S S ) 8 ( 1 8S S )

No. of switches

(bidirectional power flow) 5 ( 1 5S S ) 6 ( 1 6S S ) 6 ( 1 6S S ) 8 ( 1 8S S )

External fast recovery

diodes (unidirectional power flow)

1 ( inD ) 1 ( inD ) 5 ( 1 4,inD D D ) 8 ( 1 8D D )

No. of inductors 3 ( 1 2, , fL L L ) 2 ( ,in fL L ) 5 ( 1 1, , ,in a bL L L 2 2,a bL L ) 4 ( 1 1 2 2, , ,a b a bL L L L )

No. of inductors conducting current at a

time

3 ( 1 2, , fL L L ) 2 ( ,in fL L ) 3 ( 1 , 1,in a bL L L or

2 2, ,in a bL L L ) 2 ( 1 , 1a bL L or 2 , 2a bL L )

Energy storing or dc link capacitors

2 ( 1 2,C C ) 2 ( inC , dcC ) 2 ( inC , dcC ) 1( inC )

Voltage gain

ˆ( / )o inG v V 1 2 zsi

M

D

1

M

D

1

M

D

1

M

D

Switch voltage stresses

1 5

1 5

( )

(2 1)

ˆ(2 1)( )o

S S in

S S in

in

V V Buck

V G V

G vBoost

GV

1 6ˆ

oS S inV GV v

(Boost)

1 6S S inV V (Buck)

1 6ˆ

oS S inV GV v (Boost)

1 6S S inV V (Buck)

1 4S S inV V

5 8ˆ

oS SV v

Switch current stresses

1 4 5ˆ ,S S o S inI i I I (Buck)

1 4 52 ,

(2 1)(Boost )

S S in S

in

I I I

G I

G

5 6S S inI I ,

1 4ˆ

S S oI i 5 6S S inI I , 1 4

ˆS S oI i

1 8ˆ

S S oI i (Buck)

inI (Boost)

Capacitor voltage stresses

1, 2C C inV V (Buck)

2 ( 1)C inV G V

1C inV GV (Boost)

Cin inV V

Cdc inV V (Buck)

Cdc inV GV (Boost)

Cin inV V

Cdc inV V (Buck)

Cdc inV GV (Boost)

Cin inV V

Inductor currents 1, 2L L inI I

ˆLf oI i

Lin inI I

ˆLf oI i

Lin inI I

1 2ˆ

L a L b oI i 1 2

ˆL a L b oI i (Buck)

1 2L a L b inI I (Boost)

Inductor current ripples

1, 2

ˆ ( 1)

(2 1)

o

L L

v Gi T

G L

(Boost)

ˆ

2

o

Lf

vi T

ML (Buck)

ˆ (2 1)

2

o

Lf

v Gi T

GL

(Boost)

Where, 1 2, , fL L L L

2

ˆ ( 1)o

Lin

v Gi T

G L

(Boost)

ˆ

2

o

Lf

vi T

ML

(Buck)

ˆ

2

o

Lf

vi T

L (Boost)

Where, ,in fL L L

2

ˆ ( 1)o

Lin

v Gi T

G L

(Boost)

1 2

ˆ

2

o

L a L b

vi T

ML (Buck)

1 2

ˆ

2

o

L a L b

vi T

L (Boost)

Where, inL L , / 2xa xbL L L

x=1, 2

1 2

ˆ

2

o

L a L b

vi T

ML (Buck)

1 2

ˆ

2

o

L a L b

vi T

GL (Boost)

Where, , / 2xa xbL L L ,

x=1, 2




10

C. Inductor Requirement and Current Ripples

The number of inductors required is summarized in Table I.

Compared with the fL in the TCBBI, the two inductors 1aL

and 1bL (or 2aL and 2bL ) in both the dual-buck inverter of the

CDBBI and the proposed inverter are always in series.

Therefore, the required inductance for 1aL and 1bL or ( 2aL

and 2bL ) becomes / 2fL . Therefore, the magnetic volume of

the proposed inverter and the TCCBI could be comparable, and

the magnetic volume of the proposed inverter could be smaller

that of the qZSI and CDBBI.

The inductor current ripples of filter inductors ( fL for the

qZSI and TCBBI, 1 1a bL L (or 2 2a bL L ) for the CDBBI and

the proposed inverter) are given in Table 1. During the buck

operation, the current ripples of filter inductors are the same for

all inverters. Fig. 19 shows the ratios of the inductor current

ripples of the proposed inverter to those of the qZSI, CDBBI,

and TCBBI during the boost operation. It can be seen that the

inductor current ripple of the proposed inverter is smaller than

those of other three inverters for same value of inductance L,

and the difference becomes significant as the voltage gain

increases (as inV becomes lower).

D. Capacitor Requirement

The qZSI requires two energy storing capacitors 1C and 2C

. The TCBBI and CDBBI require two capacitors, an input

capacitor inC and dcC . The dcC can be designed to handle the

low frequency current component and to filter the pulsating

voltage of boost dc-dc converter. The proposed inverter does

not require dcC . However, like the single-phase dual-buck and

H-bridge inverters, the proposed inverter requires an input

capacitor inC , which can be designed to handle the low

frequency current component. If the low frequency current

component is ignored, then the proposed inverter can be

operated without dc link capacitors.

The proposed inverter has one extra MOSFET or diode in

the conduction loop, while the CDBBI and TCBBI have one

extra inductor inL in the conduction loop, and the qZSI has

two extra inductors 1L and 2L in the conduction loop. In

comparison with the conventional inverters, the proposed

inverter allows bidirectional power flow without body diodes

conducting and current shoot-through problem (see Fig. 20).

VI. SIMULATION RESULTS

The electrical specifications of the proposed inverter are

listed in Table II. Simulation results of the proposed

closed-loop standalone inverter are given in Fig. 21. Fig. 21

shows the results for the worst case when inV step up instantly

from 185 V to 400 V at the peak of ov or sv . To regulate ov at

311 V, magnitude of sv , M changes from 1 to 0.78, and cV

changes from 0.4 to 0. At t= 0.2 s, inV step down instantly from

400 V to 185 V. To regulate ov at the rated output voltage, M

changes from 0.78 to 1, and cV changes from 0 to 0.4. Fig. 21(b)

shows the results for mode change at the zero crossing of ov or

sv . From the simulation results, it is found that by changing the

operational mode no noticeable distortion occur in the output

voltage.

TABLE II.

ELECTRICAL SPECIFICATIONS OF THE PROPOSED INVERTER

1S

2D

1D

2S

3S

4D

3D

4S

5S

6D

5D

6S

7S

8D 8S

1C

2C

+

-

+

-

1Cv

2Cv

1aL

2aL

1bL

1Li

2Li

+-

+ -

+- 7D

2bL+ -3Li

4Li

oi

inC

oC

BV

acv

Fig. 20. Bidirectional power flow without body diode conducting.

Fig. 21. Simulated dynamic response of the proposed inverter with step input

change at the peak of ov (or sv ).

Output voltage 220 Vrms/60 Hz

Input voltage 185-400 Vdc

Output power 1.1 kW

Switching frequency 30 kHz

MOSFETs ( 1 8S S ) 47N60CFD

Diodes ( 1 8D D ) RURG3060

Inductors ( 1 2a bL L ) 0.5 Hm

Capacitors ( 1 2,C C ) 2.2 F

Output capacitor ( oC ) 8 F




11

VII. EXPERIMENTAL RESULTS

A hardware prototype of the proposed inverter is

fabricated and tested in standalone mode using open-loop

control with the electrical specifications listed in Table II.

Although the proposed inverter can be operated properly

without PWM dead-time and the risk of shoot-through current,

a small dead-time in the gate signals of 1 4S S is used in the

experiment to decrease the circulating current which occurs

when the upper and lower switches are turned-on

simultaneously.

A. Resistive Load

Fig. 22 shows experimental waveforms of the proposed

inverter with resistive load during the buck operation when

D=0, M=0.78, 400inV V . Fig. 22(a) shows the waveforms of

input voltage inV , output voltage ov , and inductor currents.

Fig. 22(b) shows the waveforms of drain-source voltages of

switches 1S , 2S , 5S and 7S , respectively. Fig. 22(c) shows

the expanded waveforms of Fig. 22(b).

Fig. 23 shows the same waveforms of the proposed inverter

in the boost mode when D=0.4, M=1, 185inV V .

B. No Load Condition

Fig. 24 shows the no load waveforms of inV , ov , 1Li and

6DSv during the boost mode with D=0.4, M=1, 185inV V .

[200 / div]ov V

1[10 / div]Li A

[10 sec/ div]m

[200 / div]inV V

2[10 / div]Li A

(a)

1[220 / div]DSv V

7[220 / div]DSv V

2[220 / div]DSv V

5[220 / div]DSv V

[10 sec/ div]m

(b)

7[220 / div]DSv V

5[220 / div]DSv V

[10 sec/ div]

1[220 / div]DSv V

2[220 / div]DSv V

(c)

Fig. 22. Experimental results with resistive load when M=0.78, D=0 and Vin

=400 V. (a) Inductor currents, input and output voltages. (b) Drain-source

voltages of switches. (c) Expanded waveforms of (b).

[200 / div]ov V

1[10 / div]Li A

[10 sec/ div]m

[200 / div]inV V

2[10 / div]Li A

(a)

7[200 / div]DSv V

5[200 / div]DSv V

[10 sec/ div]m

1[200 / div]DSv V

2[200 / div]DSv V

(b)

7[200 / div]DSv V

5[200 / div]DSv V

[10 sec/ div]

1[200 / div]DSv V

2[200 / div]DSv V

(c)

Fig. 23. Experimental results with resistive load when M=1, D=0.4 and Vin

=185 V. (a) Inductor currents, input and output voltages. (b) Drain-source

voltages of switches. (c) Expanded waveforms of (b).




12

C. Partially Inductive Load

Fig. 25 shows the waveforms of inV , ov , 1Li ,

6DSv and

output current oi during the boost mode for partially inductive

load ( 44LR , 10L mH ).

D. Dynamic Experimental Results

Fig. 26 shows the dynamic experimental results for instant

mode change when 185inV V . Fig. 26(a) shows the results

when mode changes from the boost (M=1, D=0.4, 1.1oP kW )

to buck (M=0.78, D=0, 200oP W ). Fig. 26(b) shows the

expanded waveforms of Fig. 26(a) at the transition region. Fig.

26(c) shows the waveforms for the worst case when mode

6[200 / div]DSv V

[200 / div]ov V

[200 / div]inV V

1[10 / div]Li A

[10 sec/ div]m

Fig. 24. Experimental results for no load conditions: M=1, D=0.4 and Vin =185 V.

6[200 / div]DSv V

[200 / div]ov V [200 / div]inV V

1[10 / div]Li A

[10 sec/ div]m

[10 / div]oi A

Fig. 25. Experimental results with partially inductive load: M=1, D=0.4 and Vin

=185 V.

5[200 / div]DSv V

[10 sec/ div]m

[200 / div]inV V[200 / div]ov V

[200 / div]oi V

(a)

5[200 / div]DSv V

[0.5 sec/ div]m

[200 / div]inV V

[200 / div]ov V

[200 / div]oi V

(b)

5[200 / div]DSv V

[10 sec/ div]m

[200 / div]inV V[200 / div]ov V

[200 / div]oi V

(c)

Fig. 26. Dynamic experimental results for step mode change when 185inV V

. (a) Boost to buck. (b) Expanded waveforms of (a) at the transition point. (c)

Buck to boost at the peak of ov .

TABLE III. PARAMETERS OF THE CONVENTIONAL INVERTERS

Parameters TCBBI (Fig. 2) CDBBI (Fig. 6) qZSI (Fig. 4)

Switching

frequency

Boost dc-dc

converter 25 kHz Boost dc-dc converter 25 kHz

20 kHz

H-bridge VSI 25 kHz Dual-buck inverter 30 kHz

Inductors inL 1.5 mH inL 1.5 mH 1 2,L L 1 Hm

fL 1.2 mH 1 2a bL L 0.5 mH fL 1.5 mH

Switches 1 6S S IGW40N60H3 5 6S S IGW40N60H3

1 4S S CM100TL_24NF 1 4S S 47N60CFD

Diodes - 1 4D D RURG3060 inD IXYS DSEI

2X61-12B




13

changes instantly from the buck (M=0.78, D=0, 200oP W ) to

boost (M=1, D=0.4, 1.1oP kW ) at the peak of ov . The

experimental results in Fig. 26 confirmed that similar to the

simulation results in Fig. 21, the proposed inverter has no

noticeable distortion when the mode is changed.

E. Power Transfer Efficiency

Table III shows the parameters of the conventional inverters

for efficiency measurement. The TCBBI, qZSI, and boost dc-dc

converter of the CDBBI are designed with IGBTs to avoid the

reverse recovery issues and relevant loss of MOSFET body

diode. The qZSI is operated at 20 kHz. The TCBBI and boost

dc-dc converter of the CDBBI are operated at 25 kHz to keep

the switching loss of IGBTs lower. The proposed inverter is

designed with MOSFETs and is operated at 30 kHz.

The efficiency is measured using Yokogawa WT1600 power

meter. Fig. 27 shows the measured efficiency of the proposed

inverter at the rated and varied output power. The maximum

97.8 % and minimum 96.1 % efficiency are obtained for the

proposed inverter.

Fig. 28 shows the measured efficiencies of the four inverters

mentioned in Table I. The efficiencies of the proposed inverter

and the CDBBI are comparable and they are greater than the

efficiencies of the TCBBI and qZSI. The efficiencies could be

improved if the inverters are optimized properly. Fig. 29 shows

prototype photo of the proposed inverter.

5[200 / div]DSv V

(a)

0D

Buck Region0.8

1

(b)

Fig. 27. Measured efficiency of the proposed inverter. (a) Rated output power.

(b) Varied output power.

10

Fig. 28. Measured efficiencies of the buck-boost inverters.

Fig. 29. Prototype photo.

VIII. CONCLUSION

In this paper, a highly reliable and high efficiency quasi

single-stage single-phase bidirectional buck-boost inverter is

proposed. The proposed inverter takes the dual-buck structure

at the input dc side and the switching cell structure at the ac

output side. It is immune from both short-circuit and

open-circuit problems. Therefore, PWM dead-times can be

eliminated in the proposed inverter, which results in high

quality output voltage waveforms. Moreover, it utilizes high

speed power MOSFETs along with externally selected fast

recovery diodes, which decrease the switching and conduction

losses. Thus, high frequency and high efficiency operation is

realized. The operation principle and circuit analysis of the

proposed topology are presented in detail. To verify

performance of the proposed inverter, a 1.1 kW laboratory

prototype inverter is fabricated and experiments are performed

for both buck and boost modes to obtain a 220 Vrms ac output

voltage for wide range of input dc voltage (185 V-400 V) . The

efficiency measurement shows that the proposed inverter can

obtain maximum efficiency of 97.8 % and minimum efficiency

of 96. 1 % at 30 kHz frequency with simple PWM control.

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14

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PWM inverting buck-boost ac-ac converter,” IEEE Trans. Ind.

Electron.,(Accepted for publication: DOI: 10.1109/TIE.2016.2565461)

Ashraf Ali Khan received his B.E.

in Electronics Engineering from National University of Sciences and Technology (NUST), Islamabad

Pakistan, in 2012. He is currently working towards

his MS combined Ph.D. degree in the School of Energy Engineering, Kyungpook National

University, Korea. His current research interests

include magnetics, reliable buck-boost inverters, multilevel inverters, multilevel converters and ac-ac

converters. He is the author of more than 25 technical publications. He received third best paper award in ECCE-ASIA 2015, and scholarships from NICT R&D

Fund Pakistan, BISE SWAT, NUST and Kyungpook National University. He

also received best researcher award from brain-Korea organization.

Honnyong Cha (S’08-M’10) received his B.S. and M.S. in Electronics Engineering from Kyungpook

National University, Daegu, Korea, in 1999 and

2001, respectively, and his Ph.D. in Electrical Engineering from Michigan State University, East

Lansing, Michigan, in 2009. From 2001 to 2003, he

was a Research Engineer with the Power System Technology (PSTEK) Company, An-san, Korea.

From 2010 to 2011, he worked as a Senior

Researcher at the Korea Electrotechnology Research Institute (KERI), Changwon, Korea. In 2011, he joined Kyungpook National

University as an Assistant Professor in the School of Energy Engineering. His

current research interests include high power dc-dc converters, dc–ac inverters, ZS inverters, and power conversion for electric vehicles and wind power

generation.




15

Hafiz Furqan Ahmed received his B.S. in Electronics Engineering from National

University of Sciences and Technology (NUST),

Islamabad Pakistan, in 2012. He is currently working towards his MS leading to Ph.D. degree

in the School of Energy Engineering, Kyungpook

National University, Korea. His current research interests include high efficiency bidirectional

dc-dc converters, ZS inverters, and high reliable

ac-ac converters without commutation problem.

Juyong Kim received the M.S. and Ph.D. degrees from Kyungpook National University in 1994 and in 2007,

respectively. He joined the KEPRI (Korea Electric

Power Corp. Research Institute) as a researcher in 1994. His main research interests are DC distribution system

and DC microgrid. He is currently a principal researcher

at Smart Power Distribution Lab. of KEPRI.

Jintae Cho received the B.S. and M.S. degrees in Electrical Engineering from Korea University, Seoul,

Korea, in 2006 and 2008, respectively, and he is in Ph.D

in the area of DC distribution. He is currently a senior researcher at Smart Power Distribution Lab. of KEPRI

(Korea Electric Power Corp. Research Institute),

Daejeon, Korea. His research interests include protection, monitoring and control of LVDC

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