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4 - Bit Arithmetic Logic Unit74HC/HCT181

Aruna KetarajuSowmya ParamkusamBalakrishna PeddireddiAdvisor: Dave Parent

12/06/2004

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Agenda

• Abstract• Introduction• Design Process Methodology• Logic Verification• Worst-case Delay Calculations• Results• Cost Analysis• Conclusions

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Abstract

• We designed a 4-bit Arithmetic Logic Unit that operates at 200 MHz and uses 20.3W/cm2 of Power and occupies an area of 710x340m2.

• Full look-ahead for high speed operation on long words.

• Arithmetic operating modes:

-Addition, Subtraction• Logic function modes:

- NAND, AND, OR, NOR, EX-OR, Comparator plus ten other logic operations.

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Introduction

• The 74HC/HCT181 is a 4-bit ALU.• Controlled by S0, S1, S2, S3, M.• For M = High , Logical operations are performed• For M = Low & Cn = High, Arithmetic operations are

performed.• It can perform 16 arithmetic and 16 logical operations.

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Design Process Methodology of the ALU

• Sizing Transistors through the use of analytical equations.

• Cell-based circuit implementation.• Simulation.• Layout.• Design Rule Check.• Layout versus Schematic Check.• Extraction.• Post Simulation

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Logic Diagram

Philips 74HC/HCT181

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DFFs

• DFFs are placed on either side of the combinational logic.

• The DFF drives a load of 14.5fF and based on that the Wns and Wps are calculated.

• The set-up and hold-times are .59ns and .63ns respectively.

9ns

nsPHL 29.

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5 Note: All widths are in microns

and capacitances in fF

LOGICLEVELS

GATE Cg to Drive

# Cdn’s # cdp’s #Ln’s #Lp’s Wn(hc)

Wp(hc)

Wn(s)

Wp (s)

Cg of Gate

1 INV(buffer) 20 1 1 1 1 0.53 2.62 1.5 2.55 6.9

1 INV(buffer) 6.9 1 1 1 1 1.5 2.625 1.5 2.55 6.9

1 NOR2 6.9 2 3 1 2 1.5 5.25 1.5 2.55 6.9

1 NAND2 6.9 3 2 2 1 1.5 1.2 1.5 1.5 6.9

2 XOR2 28.8 4 4 2 2 6.78 11.8 4 7 31.6

XOR2 31.6 2 3 1 2 1.5 5.25 4 7 11.5

1 INV 11.5 1 1 1 1 1.5 2.625 1.5 2.55 6.9

1 NAND2 6.9 3 2 2 1 1.5 1.2 1.5 1.5 5.09

1 NOR2 5.09 2 3 1 2 1.5 5.25 1.5 2.4 6.64

1 NOR2 6.64 2 3 1 2 1.5 5.19 1.5 2.55 6.9

1 NAND3 6.9 5 3 3 1 1.65 1.5 1.65 1.95 6.10

1 NOR2 44.2 2 3 1 2 2.03 7.1 2.4 5.7 13.8

1 INV 13.8 1 1 1 1 1.5 2.625 1.5 2.55 6.9

1 NAND3 6.9 5 3 3 1 1.65 1.5 1.95 1.65 6.10

1 INV 11.1 1 1 1 1 1.5 2.625 1.5 2.55 6.9

1 INV(buffer) 35.7 1 1 1 1 1.5 2.55 3.75 4.8 14.5

1 INV(buffer) 14.5 1 1 1 1 1.5 2.55 3.75 4.8 14.5

Longest Path Calculations

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SCHEMATIC

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S3 S2 S1 S0

L L L L

L L L H

L L H L

L L H H

L H L L

L H L H

L H H L

L H H H

H L L L

H L L H

H L H L

H L H H

H H L L

H H L H

H H H L

H H H H

Logic (M=H)

Arithmetic (M=L, Cn=H)

A’ A

(A+B)’ A+B

A’B A+B’

Logical 0 Minus 1

(AB)’ A plus AB’

B’ (A+B) plus AB’

A xor B A minus B minus 1

AB’ AB’ minus 1

A’+B A plus AB

(A xor B)’ A plus B

B (A+B’) plus AB

AB AB minus 1

Logical 1 A plus A

A+B’ (A +B) plus A

A+B (A+B’) plus A

A A minus 1

Functions performed by ALU

12Logic Verification

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LAYOUT

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Verification

LVS REPORT

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Worst-case Delay Calculations

Longest Path is between B2 and A=B.

The test vectors to calculate the worst-case propagation delay are:

A0, A1, A2, A3, B0, B1, B3, S1 = 0;

M, Cn = 1;

B2 = toggle;

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Simulations

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Cost Analysis

Time spent on each phase of the project– Verifying logic : 3days

– Verifying timing : 7days

– Layout : 15days

– Post extracted timing : 7days

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Lessons Learned

• Every PMOS should be in contact with n-tap.

• Never route with poly.

• The input data shouldn't near the clock rising edge.

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Conclusions

• 4-bit ALU has been simulated and verified

• Frequency, area and power specifications have been met.

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Acknowledgements

• Thanks to Cadence Design Systems for the VLSI lab

• Thanks to Synopsys for Software donation

• Thanks to Prof. Parent for his support and guidance in each and every step of the project.