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1 An Overview of Some Microcontrollers/Microprocessors for Embedded Systems Slide 2 2 Some Microcontrollers/Microprocessors to be Addressed ================ In B.Sc. Course ======== ================ In B.Sc. Course ======== 8051 Family (MCS-51) (Intel and Others) 8051 Family (MCS-51) (Intel and Others) PIC (Arizona Microchip) PIC (Arizona Microchip) ============ in M. Sc. Course =========== ============ in M. Sc. Course =========== X86 (Intel, AMD computers) X86 (Intel, AMD computers) ARM Family (32-bit RISC from Accorn) ARM Family (32-bit RISC from Accorn) TMS320XX DSP Family (Texas Instruments) TMS320XX DSP Family (Texas Instruments) Slide 3 3 MCS-51 Family Slide 4 4 The 8051 8-bit Microprocessor/ Microcontroller Family (MCS-51) (Intel, Philips, Atmel, Siemens, AMD, etc) 8051, 8751, 8031, 8052, 8752, 8032, Atmel 89ATC2051 (20 pins), Philips 80C552 (with A/D converter and PWM), 8051XA (16 bits) Slide 5 5 8051 (old chip) Block Diagram CPU Interrupt Control OSC Bus Control 4k ROM Timer 1 Timer 2 Serial 128 bytes RAM 4 I/O Ports TXD RXD External Interrupts P0 P2 P1 P3 Addr/Data Slide 6 6 8051 Internal Block Diagram Slide 7 7 8051 I/O Pins for 40-Pin DIP Package Slide 8 8 8051 Family (8051, 8052, 802051, etc) The 8051 is a Single Chip Computer or microcontroller Developed Initially by Intel. It is one of the most widely used microcontroller chips in the world. The 8051 is a Single Chip Computer or microcontroller Developed Initially by Intel. It is one of the most widely used microcontroller chips in the world. Other Companies have binary-compatible microcontrollers with additional features. Other Companies have binary-compatible microcontrollers with additional features. There are several versions of the 8051 family. At the lowest end there is a 20-pin AT89C2051 microcontroller chip from Atmel (cost : US$ 3.00 !!!). There are several versions of the 8051 family. At the lowest end there is a 20-pin AT89C2051 microcontroller chip from Atmel (cost : US$ 3.00 !!!). IMPORTANT PINS: IMPORTANT PINS: Port 0 (acts as a multiplexed low byte address and data bus for large external memory design). Port 0 (acts as a multiplexed low byte address and data bus for large external memory design). Port 1 8-bit R/W - General Purpose I/O Port 1 8-bit R/W - General Purpose I/O Port 2 (act as the high byte of the address bus for large external memory design). Port 2 (act as the high byte of the address bus for large external memory design). Port 3 General Purpose I/O if not using any of the internal peripherals (timers) or external interrupts. Port 3 General Purpose I/O if not using any of the internal peripherals (timers) or external interrupts. PSEN (out): Program Store Enable, the read strobe to external program memory (active low). PSEN (out): Program Store Enable, the read strobe to external program memory (active low). ALE (out): Address Latch Enable, to latch address outputs at Port0 and Port2 ALE (out): Address Latch Enable, to latch address outputs at Port0 and Port2 EA (in): External Access Enable, active low for access external program memory locations 0 to 4K EA (in): External Access Enable, active low for access external program memory locations 0 to 4K UART pins for serial I/O on Port 3 UART pins for serial I/O on Port 3 XTAL1 & XTAL2: Crystal inputs for internal oscillator. XTAL1 & XTAL2: Crystal inputs for internal oscillator. Slide 9 9 Basic 8051 Characteristics 4K bytes of internal ROM 4K bytes of internal ROM 128 bytes of internal RAM: 128 bytes of internal RAM: four register banks (0 - 3), each containing R0 - R7 8-bit registers.four register banks (0 - 3), each containing R0 - R7 8-bit registers. 16 bytes of bit addressable area.16 bytes of bit addressable area. 80 bytes of general purpose memory.80 bytes of general purpose memory. Four 8-bit I/O ports (P0 - P3). Four 8-bit I/O ports (P0 - P3). Two 16-bit timers/counters Two 16-bit timers/counters One serial receiver/ transmitter (UART) interface. One serial receiver/ transmitter (UART) interface. One instruction cycle = 12 clock cycles (1us per instruction at 12 MHz clock) One instruction cycle = 12 clock cycles (1us per instruction at 12 MHz clock) Five (2 external and 3 internal) interrupt sources. Five (2 external and 3 internal) interrupt sources. Expandable to 64K external code (program) memory space. Expandable to 64K external code (program) memory space. Expandable to 64K external data memory space. Expandable to 64K external data memory space. Boolean instructions work with one bit at a time. Boolean instructions work with one bit at a time. 4 s for either an 8-bit multiply or divide instruction. (Assume a 12 MHz clock signal). 4 s for either an 8-bit multiply or divide instruction. (Assume a 12 MHz clock signal). On chip oscillator to generate clock. On chip oscillator to generate clock. One cycle 8-bit Multiply and Divide Instructions Very Limited use One cycle 8-bit Multiply and Divide Instructions Very Limited use Slide 10 10 I/O Port (P0 - P3) Structure (Cont.) One of the most useful features of the 8051 is that it contains four I/O ports (P0 - P3). One of the most useful features of the 8051 is that it contains four I/O ports (P0 - P3). All ports are bidirectional (they can take inputs and can provide output signals).All ports are bidirectional (they can take inputs and can provide output signals). Each port has an 8-bit latch, an output driver and an input buffer (see next slide example of Port 3 pin)Each port has an 8-bit latch, an output driver and an input buffer (see next slide example of Port 3 pin) All ports have multiple functions (except P1).All ports have multiple functions (except P1). On RESET all the ports associated with latches are set to 1s.On RESET all the ports associated with latches are set to 1s. The bit latch is represented as a D type flip-flop.The bit latch is represented as a D type flip-flop. When a bit latch is to be used as an input, a 1 must be written to the corresponding latch by the program to configure it as an input.When a bit latch is to be used as an input, a 1 must be written to the corresponding latch by the program to configure it as an input. An instruction can read the status of the latch (read latch signal) and a different instruction can read the status of the input pin signal (read pin signal).An instruction can read the status of the latch (read latch signal) and a different instruction can read the status of the input pin signal (read pin signal). Slide 11 11 Port P3 8051 Port 3 Bit Latches and I/O Buffers Slide 12 12 Port P0 Acts as a multiplexed data bus: Acts as a multiplexed data bus: Tristate bus with strong pull-ups.Tristate bus with strong pull-ups. 8-bit instruction bus, strobed by PSEN.8-bit instruction bus, strobed by PSEN. Low byte of address bus, strobed by ALE.Low byte of address bus, strobed by ALE. 8-bit data bus, strobed by WR and RD.8-bit data bus, strobed by WR and RD. Port 0 may not be used as general purpose I/O when being used as the address/data bus.Port 0 may not be used as general purpose I/O when being used as the address/data bus. 3.2 mA outputs (about 8 LSTTL loads). 3.2 mA outputs (about 8 LSTTL loads). Slide 13 13 Port P1 This is an I/O port only (it does not have other functions like timer or interrupt) This is an I/O port only (it does not have other functions like timer or interrupt) Input: Input: 1 is written to the latch on RESET or by a program, the pins are floating on high impedance.1 is written to the latch on RESET or by a program, the pins are floating on high impedance. Any external device can alter the state which can be read by reading the latches.Any external device can alter the state which can be read by reading the latches. Output: Output: Directly 0 to 0 or 1 to 1, whatever, it will appear on the corresponding pins.Directly 0 to 0 or 1 to 1, whatever, it will appear on the corresponding pins. All bit latches have a fixed internal pullup resistor. All bit latches have a fixed internal pullup resistor. 1.6 mA outputs (about 4 LSTTL loads). 1.6 mA outputs (about 4 LSTTL loads). Slide 14 14 Port P2 and P3 Port P2 operates similarly to port P1, and with an alternate function as high byte of address bus for external program and data memory accesses. Port P2 operates similarly to port P1, and with an alternate function as high byte of address bus for external program and data memory accesses. Port 2 may not be used as general purpose I/O when being used as the address bus.Port 2 may not be used as general purpose I/O when being used as the address bus. Port P3 operates similarly to port P1, but it also provides the alternate functions (see next slide). Port P3 operates similarly to port P1, but it also provides the alternate functions (see next slide). Slide 15 15 Port 3 Alternate Functions Slide 16 16 Read-Modify-Write Feature Some instructions that read a port read the latch and others read the pin. Some instructions that read a port read the latch and others read the pin. The instructions that read the latch rather than the pin are the ones that read a value, possibly change it, and then rewrite it to the latch. These are called read-modify-write instructions. The instructions that read the latch rather than the pin are the ones that read a value, possibly change it, and then rewrite it to the latch. These are called read-modify-write instructions. The read-modify-write instructions are directed to the latch rather than the pin. The objective is to avoid a possible misinterpretation of the voltage level at the pin (you cant read and modify an externally provided input signal if you dont have control over it) The read-modify-write instructions are directed to the latch rather than the pin. The objective is to avoid a possible misinterpretation of the voltage level at the pin (you cant read and modify an externally provided input signal if you dont have control over it) Slide 17 17 Read-Modify-Write Instructions The instructions listed below are read-modify-write instructions. The instructions listed below are read-modify-write instructions. When the destination operand is a port, or a port bit, these instructions read the latch rather than the pin. If only examine P1.0, then read the pin e.g. MOV C, P1.0 Slide 18 18 Memory Organization Code/Data Space Space for code/program is separate from data Space for code/program is separate from data Max of 64K of code and 64K of data space, using external components Max of 64K of code and 64K of data space, using external components How does the hardware know when it is an internal or external access to ROM or RAM? Use different instructions for each case !! How does the hardware know when it is an internal or external access to ROM or RAM? Use different instructions for each case !! MOV Internal RAM MOVC ROM/EPROM MOVX External RAM Notable Features Registers & I/O ports are memory mapped. Registers & I/O ports are memory mapped. Stack resides in internal RAM Stack resides in internal RAM Parts of the RAM are bit-wise accessible. Parts of the RAM are bit-wise accessible. Slide 19 19 Register Banks 4 banks of registers (R0 to R7) 4 banks of registers (R0 to R7) The idea of register banks permits fast and effective context switching whereby separate sections of software use a private set of registers independent of other sections of software. The idea of register banks permits fast and effective context switching whereby separate sections of software use a private set of registers independent of other sections of software. Why? What does this mean? What uses does this have? Why? What does this mean? What uses does this have? Slide 20 20 An Accumulator Architecture: the 8051 8051 is an accumulator architecture (not a pure one) 8051 is an accumulator architecture (not a pure one) Theres one register, the accumulator (ACCU), that is both source and destination register of most operations Theres one register, the accumulator (ACCU), that is both source and destination register of most operations ADDA,ADDRESSB; A = A + Mem[ADDRESSB] Registers are 8 bits wide Registers are 8 bits wide Special instructionsSpecial instructions add with carry add with carry subtract with borrow subtract with borrow Despite their age, 8051-like chips are still often used in calculators, digital clocks, VCRs, etc. Despite their age, 8051-like chips are still often used in calculators, digital clocks, VCRs, etc. Slide 21 21 8051 Registers and PSW ACC - accumulator ACC - accumulator B - used in multiply and divide B - used in multiply and divide PSW - Program Status Word PSW - Program Status Word SP - Stack Pointer SP - Stack Pointer PC Program Counter - not user accessible PC Program Counter - not user accessible IP, IE (Interrupt Priority and Interrupt Enable) IP, IE (Interrupt Priority and Interrupt Enable) DPH and DPL (Data Pointer High and Low) DPH and DPL (Data Pointer High and Low) PCON Power Control Register PCON Power Control Register SBUFFER and SCON Serial Buffer and Serial Control Reg SBUFFER and SCON Serial Buffer and Serial Control Reg TH0, TL0, TH1, TL1 (Timer High and Low 0 and 1) TH0, TL0, TH1, TL1 (Timer High and Low 0 and 1) TCON and TMOD Timer Control Reg and Timer Mode Reg TCON and TMOD Timer Control Reg and Timer Mode Reg CY AC F0 RS1 RS0 OV - P CY - Carry AC Aux. Carry (cy from b2 to b3 - BCD) F0 General Use Flag no specific func RS0,RS1 - Bank Select (4 banks or sets) OV - Overflow - User defined flag P - Parity PSW: 0 0 - 00h to 07h 0 1 - 08h to 0Fh 1 0 - 10h to 17h 1 1 - 18h to 1Fh Slide 22 22 8051 Special Function Registers and Bit-Addressable Memory Special Function Registers Registers appear in internal memory space Registers appear in internal memory space Working registersWorking registers Port data registersPort data registers Peripheral control registersPeripheral control registers Addresses 80 - FF Addresses 80 - FF Above internal Data memoryAbove internal Data memory Bit-Addressable Memory 16 Special Function Registers are bit addressable. 16 Special Function Registers are bit addressable. Byte addresses 80, 88, 90, F8 Byte addresses 80, 88, 90, F8 Bit addresses 80 - FFBit addresses 80 - FF 16 bytes of internal Data memory are bit addressable. 16 bytes of internal Data memory are bit addressable. Byte addresses 20 to 2F Byte addresses 20 to 2F Bit address 00 - 7FBit address 00 - 7F Slide 23 23 8051 Programmers Model Program Memory(64K) OR FFFF 0000 FFFF 0000 1000 0FFF if EA = HIif EA = LO All instructions Constant Data (Using MOVC) 64 K External 60 K External 4 K Internal 0 7 7 0 Data Memory(64K) SFRs RAM 80 FF 00 7F AND Direct Direct, Register, Reg. Indirect FFFF 0000 64 K External (Using MOVX) @R @DPTR Internal Slide 24 24 8051 Internal RAM Which set of 8 registers is being used depends on 2 bits in the Program Status Word (PSW) Which set of 8 registers is being used depends on 2 bits in the Program Status Word (PSW) 00 08 10 18 20 28 30 38 40 48 50 58 60 68 70 78 Address Register Set 0 Register Set 1 Register Set 2 Register Set 3 Bit Addressable RAM + stack Slide 25 25 8051 Special Function Registers (SFRs) 80 88 90 98 a0 a8 b0 b8 c0 c8 d0 d8 e0 e8 f0 f8 Address P0 P1 P2 P3 SPDPLDPHPCON TCONTMODTL0PL1TH0TH1 SCONSBUF IE IP PSW ACC B Slide 26 26 8051 Programmers Model Port 0 Stack pointer Data pointer DPTR Power Control timer/counter control timer/counter Mode timer 0 Low timer 1 Low timer 0 High timer 1 High Port 1 Serial Control Serial Data Buffer Port 2 Interrupt Enable Ctr 1* IE * P2 SBUF * SCON * P1 TH1 TH0 TL1 TL0 TMOD * TCEN PCON DPH DPL SP * P080 81 82 83 87 88 89 8A 8B 8C 8D 90 98 A0 99 A8 SFRs * P3 * IP * PSW * ACC * B F0 FF E0 D0 B8 B0 SFRs 7F 00 08 10 18 20 30 Scratch Pad Area RAM Bit Addressable RAM Bank 3 Bank 2 Bank 1 Bank 0 R0 R7 R0 R7 R0 R7 R0 R7 Select Bank with PSW.4,.3 = RS1, RS0 Bit #00 7F OR 20.0 2F.7 * = Bit Addressable Slide 27 27 8051 Assembly Code Example ORG 440h ; Define Origin (ORG) for Data ORG 440h ; Define Origin (ORG) for Data Dat DB 0FFh ; Define Byte (DB) in Program Memory Dat DB 0FFh ; Define Byte (DB) in Program Memory Wait EQU 35 ; Associate Label to Constant (equate) Wait EQU 35 ; Associate Label to Constant (equate) Myword DW 1234h ; Define Word (DW) in Program Memory Myword DW 1234h ; Define Word (DW) in Program Memory ORG 0 ; Define Origin (ORG) for Program ORG 0 ; Define Origin (ORG) for Program Start: MOV A,#2Ch ; Acc 2C Start: MOV A,#2Ch ; Acc 2C INC R2 ; R2 R2+1 INC R2 ; R2 R2+1 SETB P0.7 ; Port 0 Bit 7 1 SETB P0.7 ; Port 0 Bit 7 1 ADD A,Wait ; A Acc + M(35) ADD A,Wait ; A Acc + M(35) DEC @R0 ; M(R0) M(R0) - 1 DEC @R0 ; M(R0) M(R0) - 1 LJUMP Finished ; PC Finished LJUMP Finished ; PC Finished Finished : Finished : General Format Label: Opcode dest,src ; Comments Slide 28 28 8051 Addressing Modes (1) Immediate - # Label or Number Immediate - # Label or Number MOV R6,#14 ; R6 14 10 MOV R6,#14 ; R6 14 10 MOV A, #CAh ; Acc CA 16 MOV A, #CAh ; Acc CA 16 MOV DPTR,#loc ; DPTR value of symbol loc MOV DPTR,#loc ; DPTR value of symbol loc Direct - Label or Number Direct - Label or Number MOV PSW,R5 ; M(PSW) R5 MOV PSW,R5 ; M(PSW) R5 MOV A,045h ; Acc M(45 16 ) MOV A,045h ; Acc M(45 16 ) Register - Rn Register - Rn MOV R1,A ; R1 Acc MOV R1,A ; R1 Acc MOV B,R3 ; B R3 MOV B,R3 ; B R3 Slide 29 29 8051 Addressing Modes (2) Register Indirect - @R0, @R1, @DPTR Register Indirect - @R0, @R1, @DPTR MOV @R0,#250 ; M(R0) 250 10 MOV @R0,#250 ; M(R0) 250 10 MOV A,@R1 ; A M(R1) MOV A,@R1 ; A M(R1) MOVX @DPTR,A ; External data M(DPTR) A MOVX @DPTR,A ; External data M(DPTR) A Register Indirect Indexed - @A+DPTR, @A+PC Register Indirect Indexed - @A+DPTR, @A+PC MOVC A,@A+DPTR ; A ROM(A+DPTR) MOVC A,@A+DPTR ; A ROM(A+DPTR) MOVC A,@A+PC ; A ROM(A+PC) MOVC A,@A+PC ; A ROM(A+PC) JMP @A+DPTR ; PC (A+DPTR) JMP @A+DPTR ; PC (A+DPTR) Bit - bit number or label.bit or bit label Bit - bit number or label.bit or bit label MOV C,IE.0 ; cy bit 0 of IE reg (EX0) MOV C,IE.0 ; cy bit 0 of IE reg (EX0) MOV C,EX0 ; same MOV C,EX0 ; same SETB 07Fh ; Bit 7F 1 SETB 07Fh ; Bit 7F 1 SETB 2F.7 ; same SETB 2F.7 ; same Slide 30 30 Subroutines 8051 stack grows from low addresses to high addresses 8051 stack grows from low addresses to high addresses SFR SP ( address 81H ) points to top of stack, i.e., if you push a value onto the stack, it will be stored at address SP+1 SFR SP ( address 81H ) points to top of stack, i.e., if you push a value onto the stack, it will be stored at address SP+1 Be careful: SP is initialized to 07H, alternate register banks 1, 2, and user bit vars occupy internal RAM addresses 08H-2FH Be careful: SP is initialized to 07H, alternate register banks 1, 2, and user bit vars occupy internal RAM addresses 08H-2FH Special instructions: Special instructions: PUSH opPUSH op POP opPOP op op must be specified using direct addressing!op must be specified using direct addressing! Slide 31 31 Parameter passing Options for parameter passing: Options for parameter passing: In internal memoryIn internal memory In registers. Not really useful, because registers are part of (and thus as fast as) internal memoryIn registers. Not really useful, because registers are part of (and thus as fast as) internal memory On stack. Also not really useful because push and pop instructions allow only direct addressing. Necessary for implementing recursive functions (but because stack is at most 128 bytes, recursion depth must be limited).On stack. Also not really useful because push and pop instructions allow only direct addressing. Necessary for implementing recursive functions (but because stack is at most 128 bytes, recursion depth must be limited). In external memory. Disadvantages: (1) slow, (2) can only be accessed via DPTR registerIn external memory. Disadvantages: (1) slow, (2) can only be accessed via DPTR register Slide 32 32 Interrupt Sources in 8051 Family (non vectored) External Interrupt INT0 (B2h Address) External pin that has to be enabled (and also have its priority set) via software. Deviation address: 0003h External Interrupt INT0 (B2h Address) External pin that has to be enabled (and also have its priority set) via software. Deviation address: 0003h External Interrupt INT1 (B3h Address) Another external pin similar to INT0. Deviaton address: 0013h External Interrupt INT1 (B3h Address) Another external pin similar to INT0. Deviaton address: 0013h NOTE: INT0 and INT1 are pins of port P3 more precisely P3.2 and P3.3. Internal Interrupt TIMER/COUNTER 0 It is generated by TIMER_0 that is an internal peripheral. Deviation address: 000Bh Internal Interrupt TIMER/COUNTER 0 It is generated by TIMER_0 that is an internal peripheral. Deviation address: 000Bh Internal Interrupt TIMER/COUNTER 1 It is generated by TIMER_1 that is an internal peripheral. Deviation address: 001Bh Internal Interrupt TIMER/COUNTER 1 It is generated by TIMER_1 that is an internal peripheral. Deviation address: 001Bh Serial Communication Interrupt Generated by the internal serial communications controller. Deviation address: 0023h Serial Communication Interrupt Generated by the internal serial communications controller. Deviation address: 0023h Slide 33 33 Interrupt Control Bits Enable Interrupt (IE address A8h) Enable Interrupt (IE address A8h) EX0 External Interrupt INT0 ET0 - Interrupt from TIMER/COUNTER_0 EX1 - External Interrupt INT1 ET1 Interrupt from TIMER/COUNTER_1 ES - Interrupt from Serial Controller EA - Enable All, that is, enable each individual enable to operate Interrupt Priority (IP address B8h) Interrupt Priority (IP address B8h) PX0 =0 Low Priority; PX0= 1 High Priority Highest priority within group PT0 =0 Low Priority; PT0= 1 High Priority PX1 =0 Low Priority; PX1= 1 High Priority PT1 =0 Low Priority; PT1= 1 High Priority PS =0 Low Priority; PS = 1 High Priority Lowest priority within group EA - - ES ET1 EX1 ET0 EX0 AF - - AC AB AA A9 A8 IE BIT DDRESS - - - PS PT1 PX1 PT0 PX0 - - - BC BB BA B9 B8 IE BIT DDRESS Slide 34 34 Interrupt Control Bits (cont) Timer Control TCON (address 88h) - (part of this register is used to control level interrupts or edge generated interrupts) Timer Control TCON (address 88h) - (part of this register is used to control level interrupts or edge generated interrupts) IT0, IT1 = 0 = Level IT0, IT1 = 0 = Level IE0, IE1 = 0 = Level, else (=1) Negative Edge IE0, IE1 = 0 = Level, else (=1) Negative Edge TF1 Timer 1 overflow flag. Cleared by processor upon vectoring to the interrupt service routine. TF1 Timer 1 overflow flag. Cleared by processor upon vectoring to the interrupt service routine. TR1 Timer 1 control bit. If TR1=1, timer 1 runs. If TR1=0, timer 1 stops TR1 Timer 1 control bit. If TR1=1, timer 1 runs. If TR1=0, timer 1 stops TF0 Timer 0 overflow flag. Similar to TF1 TF0 Timer 0 overflow flag. Similar to TF1 TR0 Timer 0 control bit. If TR0=1, timer 0 runs. If TR0=0, timer 0 stops TR0 Timer 0 control bit. If TR0=1, timer 0 runs. If TR0=0, timer 0 stops IE1 External Interrupt 1 edge flag. Set when a valid falling edge is detected at pin P3.3. Cleared by hardware when the interrupt is serviced. IE1 External Interrupt 1 edge flag. Set when a valid falling edge is detected at pin P3.3. Cleared by hardware when the interrupt is serviced. IT1 Interrupt 1 type control bit. If IT1=1, interrupt 1 is triggered by a falling edge on P3.3. If IT1=0, interrupt 1 is triggered by a low logic level on P3.3. IT1 Interrupt 1 type control bit. If IT1=1, interrupt 1 is triggered by a falling edge on P3.3. If IT1=0, interrupt 1 is triggered by a low logic level on P3.3. IE0 External Interrupt 0 edge flag. Set when a valid falling edge is detected at pin P3.2. Cleared by hardware when the interrupt is serviced. IE0 External Interrupt 0 edge flag. Set when a valid falling edge is detected at pin P3.2. Cleared by hardware when the interrupt is serviced. IT0 Interrupt 0 type control bit. If IT0=1, interrupt 0 is triggered by a falling edge on P3.2. If IT0 = 0, interrupt 0 is triggered by a low logic level on P3.2. IT0 Interrupt 0 type control bit. If IT0=1, interrupt 0 is triggered by a falling edge on P3.2. If IT0 = 0, interrupt 0 is triggered by a low logic level on P3.2. * * * * IE1 IT1 IE0 IT0 * * * * 8B 8A 89 88 TCON BIT DDRESS Slide 35 35 Interrupt Control Bits (cont) Timer Mode Register TMOD (not bit addressable) Timer Mode Register TMOD (not bit addressable) Specifies the Operation Mode of a TimerSpecifies the Operation Mode of a Timer GATE If GATE = 1, timer x will run only when TRx=1 and INTx = 1. If GATE=0, timer x will run whenever TRx=1. GATE If GATE = 1, timer x will run only when TRx=1 and INTx = 1. If GATE=0, timer x will run whenever TRx=1. C/T Timer mode select. If C/T=1, timer x runs in counter mode taking its input from Tx pin. If C/T=0, timer x runs in timer mode taking its input from the system clock. C/T Timer mode select. If C/T=1, timer x runs in counter mode taking its input from Tx pin. If C/T=0, timer x runs in timer mode taking its input from the system clock. M1 Mode selector bit 1. MSB of selector. M1 Mode selector bit 1. MSB of selector. M0 Mode selector bit 0. LSB of selector. M0 Mode selector bit 0. LSB of selector. GATE C/T M1 M0 GATE C/T M1 M0 TMOD Timer Zero Timer One Slide 36 36 Interrupt Control Bits (cont) Timer 2 Control Register T2CON Timer 2 Control Register T2CON TF2 Timer 2 overflow flag. Will not be set if RCLK=1 or TCLK=1. TF2 Timer 2 overflow flag. Will not be set if RCLK=1 or TCLK=1. EXF2 Timer 2 external flag. EXF2 is set when a falling edge is detected on T2Ex and EXEN2=1. This causes an interrupt, if the timer 2 is enabled. EXF2 Timer 2 external flag. EXF2 is set when a falling edge is detected on T2Ex and EXEN2=1. This causes an interrupt, if the timer 2 is enabled. RCLK Receive clock flag. When RCLK=1, the UART (if in mode 1 or 3) will use the timer 2 overflow frequency for the receive clock. RCLK Receive clock flag. When RCLK=1, the UART (if in mode 1 or 3) will use the timer 2 overflow frequency for the receive clock. TCLK Transmit clock flag When TCLK=1, the UART (if in mode 1 or 3) will use the timer 2 overflow frequency for the receive clock. TCLK Transmit clock flag When TCLK=1, the UART (if in mode 1 or 3) will use the timer 2 overflow frequency for the receive clock. EXEN2 External enable flag If EXEN2=1, a capture or reload will be caused by a falling edge on T2EX. If EXEN2=0, external events on T2EX are ignored. EXEN2 External enable flag If EXEN2=1, a capture or reload will be caused by a falling edge on T2EX. If EXEN2=0, external events on T2EX are ignored. TR2 Timer run control bit If TR2=1, the timer will run. If TR2=0, the timer will stop. TR2 Timer run control bit If TR2=1, the timer will run. If TR2=0, the timer will stop. C/T2 Timer mode select If C/T2=1, timer 2 will act as an external event counter. If C/T2=0, timer 2 will count processor clock cycles. C/T2 Timer mode select If C/T2=1, timer 2 will act as an external event counter. If C/T2=0, timer 2 will count processor clock cycles. CP/RL2 Capture/Reload flag If CP/RL2=1, detection of a falling edge on T2EX causes a capture if EXEN2=1. If CP/RL2=0, detection of a falling edge on T2EX or an overflow causes a timer reload if EXEN=1. CP/RL2 Capture/Reload flag If CP/RL2=1, detection of a falling edge on T2EX causes a capture if EXEN2=1. If CP/RL2=0, detection of a falling edge on T2EX or an overflow causes a timer reload if EXEN=1. TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 T2CON Slide 37 37 Interrupts on MCS-51 Family At which Moment Are Interrupts Sampled by the Microcontroller ? At which Moment Are Interrupts Sampled by the Microcontroller ? Every S5P2 clock cycle of every machine cycle See figure belowEvery S5P2 clock cycle of every machine cycle See figure below S1S2S3S4S5 S6 One Machine Cycle S5P1S5P2S6P1S6P2 Once Sampled, an Interrupt will be accepted if: There isnt another interrupt of same or higher priority being executed If the next machine cycle is the last cycle of an instruction If in the next cycle there is no RETI or any access to the interrupt registers IE and IP. If the above conditions are followed, interrupt is accepted. In the following two cycles the uP saves the PC in the Stack and loads the PC with the interrupt address. Slide 38 38 Basic Structure of a Program with Interrupts: org0000h; beginning after RESET ljmpBEGIN; Go to BEGIN. Instructions below written in MEM org0003h; INT0 interrupt address nop; If this int is used substitute nop and reti by reti; a long jump, the routine and an reti at the end. org000Bh; TIMER_0 interrupt address nopreti org0013h; INT1 interrupt address nopreti org001Bh; TIMER_1 interrupt address nopreti org0023h; SERIAL interrupt address (Receive + Transmit) nopreti BEGIN:; Begin of MAIN PROGRAM - - -; - - -; - - - - - - end; Program END Slide 39 39 Example: Changing P1.0 and P1.1 Output Values on Timer_0 and Timer_1 Interrupts org0000h; Microcontroller RESET ljmpBEGIN; Goto BEGIN ;---------------------------------------------------------------------------------------------------- org000Bh; TIMER_0 interrupt address cplP1.0; Toggles output level of pin P1.0 movTH0, #3Ch ; Load THIGH of TIMER_0 with initial value movTL0, #0AFh; Load TLOW of TIMER_0 with initial value reti; Return from Interrupt for TIMER_0 ;--------------------------------------------------------------------------------------------------- org001Bh; TIMER_1 interrupt address cplP1.1; Toggles output level of pin P1.1 reti; Return from Interrupt for TIMER_1 ;--------------------------------------------------------------------------------------------------- BEGIN:; Begin of MAIN PROGRAM movTMOD, #21h; Prog TIMER_0 - Mode1 / Timer_1 Mode 2 (auto reload) movTH0, #3Ch; Load THIGH of TIMER_0 initial value part HIGH movTL0,#0AFh; Load TLOW of TIMER_0 initial value part LOW movTH1,#0CDh; Load THIGH of TIMER_1 initial value part HIGH movTL1,#0CDh; Load TLOW of TIMER_1 initial value part LOW movIE, #8Ah; Programs Interrupt of both timers movIP, #08h; Gives more priority to TIMER_1 setbTR1; Turns TIMER_1 on setbTR0; Turns TIMER_0 on -------; Other program instructions ------- end; Program END Slide 40 40 Contagem de Tempo no 8051 (Funo que espera acabar o tempo) #include #include # define CLOCK (12.000000) /* cristal de 12 MHz */ /* Entradas */ #define P_Iniciar P3_3 /* INT1 */ #define P_Tampa_Aberta P3_2/* INT 0 */ - - - - - - /* Saidas */ #define LED_Molho P1_1 - - - - - /* Prototipos de funcoes */ void delay_ms (int tempo); void HabilitaIntTampaAberta (void); Void DesabilitaIntTampaAberta (void); - - - - - Void main (void) /* corpo principal */ { - - - - delay_ms (1000); - - - - - } void delay_ms (int tempo) { /*Timer0 no modo 1 (16 bits) */ /*Timer0 no modo 1 (16 bits) */ TMOD = 0x21; TMOD = 0x21; while (tempo);/* FICA PRESO NA FUNO */ while (tempo);/* FICA PRESO NA FUNO */ { /* Para que a contagem seja correta, deve-se: /* Para que a contagem seja correta, deve-se: (1) carregar o valor 65535-tempo, com tempo em us, que se quer contar= 65535-1000= 0xFC17) */ que se quer contar= 65535-1000= 0xFC17) */ TL0 = 0x17; TH0 = 0xFC; /* (2) Setar o flag de overflow p/ zero */ TF0 = 0; /* (3) Ligar o Timer */ TR0 = 1; /* (4) Contar (fica esperando overflow) */ while (!TF0); /* fica preso at TF0 =0 */ /* (5) Desligar o timer pois deu OVF */ TR0 = 0; /* (6) Na reentrada do loop setar tudo novamente. Se isso nao for feito o timer comecaria a contar de zero. Mesmo que recarregassemos novamente o valor em TH e TL, mas nao o desligassemos e ligassemos novamente, o timer nao iria funcionar de forma correta. */ tempo--; }} Slide 41 41 Uso de Contador e Interrupo para contar Tempo Antes de Mais nada verificar se o clock do contador e o nmero de bits do contador permitem contar o tempo desejado numa nica contagem. Exemplo: clock de 1 MHz (T=1us) e contador de 16 bits. Posso contar um tempo de 1 segundo? Antes de Mais nada verificar se o clock do contador e o nmero de bits do contador permitem contar o tempo desejado numa nica contagem. Exemplo: clock de 1 MHz (T=1us) e contador de 16 bits. Posso contar um tempo de 1 segundo? 1 us x 65536 = 65,536 ms. Portanto nessas condies nao consigo contar 1 segundo. Tenho que contar vrias vezes 65,536 ms, ou melhor, tenho que contar 16 vezes o valor total do contador (16 x 65,536 1s). 1 us x 65536 = 65,536 ms. Portanto nessas condies nao consigo contar 1 segundo. Tenho que contar vrias vezes 65,536 ms, ou melhor, tenho que contar 16 vezes o valor total do contador (16 x 65,536 1s). H contadores que contam de um valor at zero (down counter) ou de um valor carregado at dar overflow (up counter). H contadores que contam de um valor at zero (down counter) ou de um valor carregado at dar overflow (up counter). Se no for por interrupo, carrego o contador de hardware com o valor desejado (o qual incrementado por um clock), libero o contador e fico esperando no programa principal, ou numa rotina especfica, o flag que indica o fim da contagem virar. Isto ruim pois a UCP fica presa na tarefa. Se no for por interrupo, carrego o contador de hardware com o valor desejado (o qual incrementado por um clock), libero o contador e fico esperando no programa principal, ou numa rotina especfica, o flag que indica o fim da contagem virar. Isto ruim pois a UCP fica presa na tarefa. Se for por interrupo, alguns possveis passos so: Se for por interrupo, alguns possveis passos so: Liberar a interrupo do contador utilizado e Iniciar Semforos de Fim_Contador = FALSE e Fim_Tempo = FALSE. Liberar a interrupo do contador utilizado e Iniciar Semforos de Fim_Contador = FALSE e Fim_Tempo = FALSE. Instanciar a funo de inicializao, a qual recebe o parametro tempo, e que carrega o contador com o valor adequado. Fazer semforo Fim_Contador = FALSE. Instanciar a funo de inicializao, a qual recebe o parametro tempo, e que carrega o contador com o valor adequado. Fazer semforo Fim_Contador = FALSE. Liberar o incio da contagem do contador e sair da funo Liberar o incio da contagem do contador e sair da funo Na rotina que trata interrupo do contador fao Fim_Contador = TRUE. Na rotina que trata interrupo do contador fao Fim_Contador = TRUE. No programa principal fico testando (entre outras coisas) o semforo Fim_Contador. Se for FALSE vou fazer outras coisas. Se for TRUE, incremento um contador de loops. Se atingi o nmero de loops desejado fao semforo Fim_Tempo = TRUE e vou em frente. Se no atingi o nmero de loops desejado chamo novamente a funo de inicializao do contador. No programa principal fico testando (entre outras coisas) o semforo Fim_Contador. Se for FALSE vou fazer outras coisas. Se for TRUE, incremento um contador de loops. Se atingi o nmero de loops desejado fao semforo Fim_Tempo = TRUE e vou em frente. Se no atingi o nmero de loops desejado chamo novamente a funo de inicializao do contador. Ao final inibo a interrupo do contador. Ao final inibo a interrupo do contador. Slide 42 42 Lendo de Chaves Sem Debouncing : Sem Debouncing : - - - - - - - - void main (void) { unsigned char Port1_value;/* varivel que guardar o que vou ler */ unsigned char Port1_value;/* varivel que guardar o que vou ler */ P1 = 0xFF;/* Configura porta P1 para poder ler os Pinos de entrada */ P1 = 0xFF;/* Configura porta P1 para poder ler os Pinos de entrada */ /* Para ler de uma porta, o latch correspond. Deve ser 1 */ while(1) while(1) { Port1_value = P1;/* Atribui varivel o valor dos pinos de entrada */ P2 = Port1_value;/* Copia valor para P2 */ } } Slide 43 43 Implementando Debouncing de Chaves ou Botes Para realizar o Debouncing : Para realizar o Debouncing : 1.Ler o pino da porta que interessa 2.Se for detetado um estado de chave apertada, esperamos 20ms (dependendo do tipo de chave) e ento lemos a porta de novo 3.Se a segunda leitura confirmar a primeira leitura, assumimos que a chave foi realmente apertada e possivelmente setamos uma varivel indicando chave apertada. Slide 44 44 Implementando Debouncing de Chaves ou Botes ( sem Interrupo e sem Timer ) - 1 /* Programa le (e faz debounce) de chave em P1^0 e se apertada escreve na saida P3 */ #include #include Sbit switch_pin = P1^0; /* chave em P1.0 */ #define Output_port P3 #define SWITCH_NOT_PRESSED (bit) 0 #define SWITCH_PRESSED (bit) 1 // Function Prototypes void Switch_Init (void); Bit Switch_Get_Input (const unsigned char Debounce_Period; Void Display_Switch_Status_Init (void); Void Display_Switch_Status_Update (const bit); Void Delay_Loop_Wait (const unsigned int DELAY_MS); /* ================================== */ Void main (void) // MAIN PROGRAM { bit Sw_state; bit Sw_state; Switch_Init (); Switch_Init (); Display_Switch_Status_Init(); Display_Switch_Status_Init(); while (1) while (1) { Sw_state = Switch_Get_Input (30); /* 30 ms */ Sw_state = Switch_Get_Input (30); /* 30 ms */ Display_Switch_Status_Update (Sw_state); Display_Switch_Status_Update (Sw_state); }} Void Switch_Init (void); { switch_pin = 1; // Use this pin as INPUT switch_pin = 1; // Use this pin as INPUT}//---------------------------------------------------------- bit Switch_Get_Input (const unsigned char Debounce_Period) { bit Return_value = SWITCH_NOT_PRESSED; bit Return_value = SWITCH_NOT_PRESSED; if (Switch_pin == 0) if (Switch_pin == 0) { Delay_Loop_Wait (Debounce_Period); Delay_Loop_Wait (Debounce_Period); if (Switch_pin == 0) if (Switch_pin == 0) { Return_value = SWITCH_PRESSED; } } } return Return_value; return Return_value;} // -------------------------------------------------------------- Void Display_Switch_Status_Init (void) { Output_port = 0xF0; } Slide 45 45 Implementando Debouncing de Chaves ou Botes ( sem Interrupo e sem Timer ) - 2 void Display_Switch_Status_Update (const bit SWITCH_STATUS) { if (SWITCH_STATUS == SWITCH_PRESSED) { Output_Port = 0x0F; }else { Output_Port = 0xF0; }}//------------------------------------------------------------------ // Delay duration varies with parameter and is // Roughly the delay in ms on 12 MHz 8051 // (12 ciclos do oscilador) // Adjust timing for application and processor Void Delay_Loop_Wait (const unsigned int DELAY_MS) { unsigned int x, y; for (x = 0; x