1 chapter 8 flip-flops and related devices. 2 figure 8--1 two versions of set-reset (s-r) latches...
TRANSCRIPT
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Chapter 8
Flip-Flops and Related Devices
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Figure 8--1 Two versions of SET-RESET (S-R) latches
S-R (Set-Reset) Latch
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Figure 8--2 Negative-OR equivalent of the NAND gate S-R latch in Figure 8-1(b).
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Figure 8--3 The three modes of basic S-R latch operation (SET, RESET, no-change) and the invalid condition.
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Figure 8--4 Logic symbols for the S-R and S-R latch.
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Figure 8-5 : Example 8-1
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Figure 8--6 The S-R latch used to eliminate switch contact bounce.
Application Example
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Figure 8--7 The 74LS279 quad S-R latch.
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Figure 8--8 A gated S-R latch.
Gated S-R Latch
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Figure 8--9 : Example 8-2
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Figure 8--10 A gated D latch.
Gated D Latch
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Figure 8—11 : Example 8-3
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Figure 8--12 The 74LS75 quad gated D latches.
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17Figure 8--13 Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative
edge-triggered).
Edge-Triggered Flip-Flops
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18Figure 8--14 Operation of a positive edge-triggered S-R flip-flop.
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Figure 8--15 : Example 8-4 Determine output waveform
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Figure 8--16
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22Figure 8--17 Edge triggering.
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Figure 8--18 Flip-flop making a transition from the RESET state to the SET state on the positive-going edge of the clock pulse.
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Figure 8--19 Flip-flop making a transition from the SET state to the RESET state on the positive-going edge of the clock pulse.
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Figure 8--20 A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter.
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Figure 8--21 : Example 8-5
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Figure 8--22 A simplified logic diagram for a positive edge-triggered J-K flip-flop.
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Figure 8--23 Transitions illustrating the toggle operation when J =1 and K = 1.
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Figure 8--24 : Example 8-6
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Figure 8--25 : Example 8-7
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Figure 8--26 Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs.
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Figure 8--27 Logic diagram for a basic J-K flip-flop with active-LOW preset and clear inputs.
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Figure 8--28 Example 8-8
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Figure 8--29 Logic symbols for the 74AHC74 dual positive edge-triggered D flip-flops.
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Figure 8--30 Logic symbols for the 74HC112 dual negative edge-triggered J-K flip-flops.
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Figure 8—31 : Example 8-9
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Figure 8--32 Basic logic diagram for a master-slave J-K flip-flop.
Master-Slave Flip-Flops
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Figure 8--33 Pulse-triggered (master-slave) J-K flip-flop logic symbols.
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Figure 8--34 : Example 8-10
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Figure 8--35 Propagation delays, clock to output.
Flip-Flop Operating Characteristics
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Figure 8--36 Propagation delays, preset input to output and clear input to output.
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Figure 8--37 Set-up time (ts). The logic level must be present on the D input for a time equal to or greater than ts before the triggering edge of the clock pulse for reliable data entry.
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Figure 8--38 Hold time (th). The logic level must remain on the D input for a time equal to or greater than th after the triggering edge of the clock pulse for reliable data entry.
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Figure 8--39 Example of flip-flops used in a basic register for parallel
data storage.
Flip-Flop Application
Parallel Data Storage
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Figure 8--40 The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK.
Application: Frequency Division
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Figure 8--41 Example of two J-K flip-flops used to divide the clock frequency by 4. QA is one-half and QB is one-fourth the frequency of CLK.
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Figure 8--42 : Example 8-11
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Figure 8--43
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53Figure 8--44 Flip-flops used to generate a binary count sequence. Two repetitions (00, 01,
10, 11) are shown.
Application: Counting
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Figure 8--45 : Example 8-12
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Figure 8--46