1 combinational logic lecture #6. 모바일컴퓨터특강 2 강의순서 combinational circuit...

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Combinational LogicCombinational Logic

Lecture #6Lecture #6

모바일컴퓨터특강 2

강의순서 Combinational Circuit 개요 Multiplexer Decoder Half Adder Full Adder Ripple carry Adder Carry-Lookahead Adder 4-bit Adder


Combinational LogicCombinational Logic

One or more digital signal inputsOne or more digital signal outputsOutputs are only functions of current input

values (ideal) plus logic propagation delays

Combinational Logic

i1

im

O1

On

titiFttO m,...111

titiFttO mnn ,...1


Combinational Logic Combinational Logic (cont.)(cont.) Combinational logic has no memory

Outputs are only function of current input combination

Nothing is known about past events Repeating a sequence of inputs always gives the same output sequence

Sequential logic does have memory Repeating a sequence of inputs can result in an entirely different output sequence


Combinational Logic Combinational Logic (cont.)(cont.) Design Procedure

회로 기능 명세 서술문

논리식(Logic Expression)

최소화된 논리식(Minimized Logic

Expression)

하드웨어 논리회로

합성 (Synthesis)

구현(Implementation)

진리표를 이용한

정규논리식 정의

카르노맵 등을 이용하여

논리식 단순화


(( 참고참고 ))Design Entry Flow with Quartus IIDesign Entry Flow with Quartus II


Logic simplificationsLogic simplifications

Consider an automobile buzzer Buzzer = (Key In and Door Open) or (Headlight On

and Door Open) B = KD + HD = (K+H)D


SimulationSimulation

Verify if b_reduced yields the same result.


Compilation ReportCompilation Report

Verify the reduced equation with Fitter Equation & : AND

! : NOT

# : OR

$ : XOR


Floorplan

Verify the reduced equation with Floorplan


Exercise (1)Exercise (1)

Simplify X = (ABC’ + B)BC’ by starting with a BDF

Verify the result with compilation report & floorplan


Exercise (2)Exercise (2)

Simplify the equations by starting with a VHDL file X = (AB + (B’+C))’ Y = (AB)’ + (B+C)’

Verify the result with compilation report & floorplan


Exercise (3) –Entering a Truth Table with VHDL

Identify the logic with compilation report & floorplan


MUX (Multiplexer)

2N data input, 1 data output, N control inputs that select one of the data

inputs.D0

D7

D1F

S2 S1 S0


library ieee;use ieee.std_logic_1164.all;

entity mux41_ when is port( a, b, c, d: in std_logic; s : in std_logic_vector(1 downto 0); y : out std_logic);end mux41_ when;

architecture a of mux41_when isBEGIN y <= a when (s=“00”) else b when (s=“01”) else c when (s=“10”) else d;END a;

Mux 4x1(Signal Assignment, Conditional)


library ieee;

use ieee.std_logic_1164.all;

entity mux41_with is

port( a, b, c, d: in std_logic;

s : in std_logic_vector(1 downto 0);

y : out std_logic);

end mux41_with;

architecture a of mux41_with is

BEGIN

WITH s SELECT

y<= a WHEN "00",

b WHEN "01",

c WHEN "10",

d WHEN others;

END a;

Mux 4x1(Signal Assignment, Selected)


library ieee;use ieee.std_logic_1164.all;entity mux41_if_proc is port( a,b,c,d : in std_logic; s : in std_logic_vector(1 downto 0); y : out std_logic);end mux41_if_proc;architecture proc of mux41_if_proc isbegin

process(a,b,c,d,s)begin

if( s="00") theny<=a;

elsif( s="01") theny<=b;

elsif( s="10") theny<=c;

elsey<=d;

end if;end process;

end proc;

Mux 4x1 (IF)


library ieee;use ieee.std_logic_1164.all;entity mux41_case_proc is port( a,b,c,d : in std_logic; s : in std_logic_vector(1 downto 0); y : out std_logic);end mux41_case_proc;architecture proc of mux41_case_proc isbegin process(a,b,c,d,s) begin case s is when "00" => y<=a;

when "01" => y<=b;when "10" => y<=c;when others => y<=d;

end case; end process;end proc;

Mux 4x1 (case)


Library ieee; Use ieee.std_logic_1164.all;

entity mux8_1 is

port( a, b, c, d, e, f, g, h : in std_logic;

s2, s1, s0 : in std_logic;

y : out std_logic);

end mux8_1;

architecture xxx of mux8_1 is

component decoder3_8

port( a, b, c : in std_logic;

d0,d1,d2,d3,d4,d5,d6,d7 : out std_logic);

end component;

signal t : std_logic_vector(7 downto 0);

signal d0,d1,d2,d3,d4,d5,d6,d7 : std_logic;

begin

U1: decoder3_8 port map( s2,s1,s0,d0,d1,d2,d3,d4,d5,d6,d7);

t(0) <= a and d0; t(1) <= b and d1; t(2) <= c and d2;

t(3) <= d and d3; t(4) <= e and d4; t(5) <= f and d5;

t(6) <= g and d6; t(7) <= h and d7;

y <= t(0) or t(1) or t(2) or t(3) or t(4) or t(5) or t(6) or t(7);

end xxx;

t(0)

t(1)

t(2)

t(3)

t(4)

t(5)

t(6)

t(7)

Decoder3_8.vhd 는 미리 작성된 상태임

Decoder3_8.vhd 는 미리 작성된 상태임

Mixed Modeling : structure +

dataflow

Mux 8x1 (Mixed Modeling)


library ieee; use ieee.std_logic_1164.all;entity mux8_1_proc is port( a,b,c,d,e,f,g,h : in std_logic;

s2, s1, s0 : in std_logic; y : out std_logic);

end mux8_1_proc;architecture proc of mux8_1_proc isconstant bits3_0 : std_logic_vector(2 downto 0) := "000";constant bits3_1 : std_logic_vector(2 downto 0) := "001";constant bits3_2 : std_logic_vector(2 downto 0) := "010";constant bits3_3 : std_logic_vector(2 downto 0) := "011";constant bits3_4 : std_logic_vector(2 downto 0) := "100";constant bits3_5 : std_logic_vector(2 downto 0) := "101";constant bits3_6 : std_logic_vector(2 downto 0) := "110";constant bits3_7 : std_logic_vector(2 downto 0) := "111";begin

process(a,b,c,d,e,f,g,h,s2,s1,s0)variable sel : std_logic_vector(2 downto 0);begin

sel := s2 & s1 & s0;case sel is

when bits3_0 => y<= a;when bits3_1 => y<= b;when bits3_2 => y<= c;when bits3_3 => y<= d;when bits3_4 => y<= e;when bits3_5 => y<= f;when bits3_6 => y<= g;when others => y<= h;

end case;end process;

end proc;

sel(2) := s2;sel(1) := s1;sel(0) := s0;

같은 표현

같은 표현

Mux 8x1 (Constants)


library ieee;use ieee.std_logic_1164.all;

entity mux81_4bits_with is port( a, b, c, d, e, f, g, h : in

std_logic_vector(3 downto 0); s2, s1, s0 : in std_logic; y : out std_logic_vector(3 downto 0));end mux81_4bits_with;

architecture a of mux81_4bits_with issignal s : std_logic_vector(2 downto 0);BEGIN s <= s2 & s1 & s0; -- s(2)<=s2; s(1)<=s1;s(0)<=s0;

WITH s SELECT y <= a WHEN "000",

b WHEN "001", c WHEN "010", d WHEN "011", e WHEN "100",

f WHEN "101", g WHEN "110",

h WHEN others;END a;

Mux 8x1 4bits (Signal Assignment, Selected)


library ieee; use ieee.std_logic_1164.all;

entity mux81_4bits_proc is port( a,b,c,d,e,f,g,h : in std_logic_vector(3 downto 0);

s2, s1, s0 : in std_logic; y : out std_logic_vector(3 downto 0));

end mux81_4bits_proc;

architecture proc of mux81_4bits_proc issignal sel : std_logic_vector(2 downto 0);begin

sel <= s2 & s1 & s0;process(a,b,c,d,e,f,g,h,sel)begin

case sel iswhen "000" => y<= a;when "001" => y<= b;when "010" => y<= c;when "011" => y<= d;when "100" => y<= e;when "101" => y<= f;when "110" => y<= g;when others => y<= h;

end case;end process;

end proc;

Mux 8x1 4bits (case)


• 3-to-8, 4-to–16, n–to–2 n

M0M1

M7

A0

A1

A2

A typical 3 – to - 8 decoder circuit

DecoderDecoder


3x8 Decoder (Signal assignment, Conditional)

LIBRARY ieee;-- 3x8 decoder using Boolean equations--USE ieee.std_logic_1164.ALL;

ENTITY decoder_a ISPORT(a0,a1,a2 : IN std_logic;

y0,y1,y2,y3,y4,y5,y6,y7 : OUT std_logic);END decoder_a ;

ARCHITECTURE arc OF decoder_a ISBEGIN

y0 <= (NOT a2) AND (NOT a1) AND (NOT a0);y1 <= (NOT a2) AND (NOT a1) AND ( a0);y2 <= (NOT a2) AND ( a1) AND (NOT a0);y3 <= (NOT a2) AND ( a1) AND ( a0);y4 <= ( a2) AND (NOT a1) AND (NOT a0);y5 <= ( a2) AND (NOT a1) AND ( a0);y6 <= ( a2) AND ( a1) AND (NOT a0);y7 <= ( a2) AND ( a1) AND ( a0);

END arc;


3x8 Decoder (Signal assignment, Select; Truth Table)LIBRARY ieee; -- 3x8 decoder using vectors USE ieee.std_logic_1164.ALL; -- and selected signal assignment

ENTITY decoder_b ISPORT(a : IN STD_LOGIC_VECTOR (2 downto 0);

y : OUT STD_LOGIC_VECTOR (7 downto 0));END decoder_b ;

ARCHITECTURE arc OF decoder_b ISBEGIN

WITH a SELECTy<="00000001" WHEN "000",

"00000010" WHEN "001", "00000100" WHEN "010", "00001000" WHEN "011", "00010000" WHEN "100", "00100000" WHEN "101", "01000000" WHEN "110", "10000000" WHEN "111", "00000000" WHEN others;

END arc;


3x8 Decoder with enable

LIBRARY ieee; -- 3x8 decoder with enable --USE ieee.std_logic_1164.ALL;

ENTITY decoder_c ISPORT(en : IN std_logic;

a : IN STD_LOGIC_VECTOR (2 DOWNTO 0); y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));

END decoder_c ;

ARCHITECTURE arc OF decoder_c ISSIGNAL inputs : std_logic_vector(3 DOWNTO 0);BEGIN

inputs<=en & a;WITH inputs SELECT

y<="00000001" WHEN "1000", "00000010" WHEN "1001", "00000100" WHEN "1010", "00001000" WHEN "1011", "00010000" WHEN "1100", "00100000" WHEN "1101", "01000000" WHEN "1110", "10000000" WHEN "1111", "00000000" WHEN others;

END arc;

concatenate

concatenate


3x8 Decoder 3x8 Decoder (CASE)(CASE) (1) (1)

library ieee; use ieee.std_logic_1164.all;entity decoder38_proc is port( d2, d1, d0 : in std_logic; y0,y1,y2,y3,y4,y5,y6,y7 : out std_logic);end decoder38_proc;architecture xxx of decoder38_proc issignal d : std_logic_vector(2 downto 0);signal t : std_logic_vector( 0 to 7);begin d <= d2&d1&d0; process(d) begin case d is

when "000" => t<="10000000";when "001" => t<="01000000";when "010" => t<="00100000";when "011" => t<="00010000";when "100" => t<="00001000";when "101" => t<="00000100";when "110" => t<="00000010";when others => t<="00000001";

end case; end process; y0 <= t(0); y1 <= t(1); y2 <= t(2); y3 <= t(3); y4 <= t(4); y5 <= t(5); y6 <= t(6); y7 <= t(7);end xxx;

d(2) <= d2;d(1) <= d1;d(0) <= d0;

같은 표현같은 표현

회로보다는 설계사양에 관심을 둔

설계방식 .

회로보다는 설계사양에 관심을 둔

설계방식 .


Timing Simulation Result

3x8 Decoder 3x8 Decoder (CASE)(CASE) (2) (2)


Combinational logic circuits give us many useful devices.

One of the simplest is the half adder, which finds the sum of two bits.

Based on the truth table, we’ll construct the circuit.

Half Adder (1)Half Adder (1)


The sum can be found using the XOR operation and the carry using the AND operation.

S = X Y, C = XY

Half Adder (2)Half Adder (2)


Full Adder (1)Full Adder (1)

Full adder adds carry_in as well.

The truth table for a full adder is shown at the right.


Full Adder (2)Full Adder (2)- Boolean expression- Boolean expression

S = m(1,2,4,7)= X’ Y’ Cin + X’ Y Cin’ + X Y’ Cin’ + X Y Cin

= X’ (Y’ Cin + Y Cin’) + X (Y’ Cin’ + Y Cin)= X’ (Y Cin) + X (Y Cin)’= X Y Cin

Cout = m(3,5,6,7) = X’ Y Cin + X Y’ Cin + X Y Cin’ + X Y Cin

= (X’ Y + X Y’) Cin + XY(Cin’ + Cin)= (X Y) Cin + XY

or Cout = XCin + Y Cin + XY

X Y Cin Cout S

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1


Full Adder (3)Full Adder (3)


LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY fulladd ISPORT ( x , y, cin : IN STD_LOGIC ; s, cout : OUT STD_LOGIC );

END fulladd ;

ARCHITECTURE fulladd_dataflow OF fulladd ISBEGIN

s <= x XOR y XOR cin ;cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;

END fulladd_dataflow ;

Full Adder (4)Full Adder (4) - Dataflow VHDL - Dataflow VHDL DescriptionDescription


Full Adder (5) Full Adder (5) – using Half adder– using Half adder


Just as we combined half adders to make a full adder, full adders can be connected in series.

The carry bit “ripples” from one adder to the next; hence, this configuration is called a ripple-carry adder.

Today’s systems employ more efficient adders.

ripple: 잔물결 , 파문

Ripple Carry AdderRipple Carry Adder


Ripple Carry Adder Operation All 2n input bits available at the same time Carries propagate from the FA in position 0 (with inputs x0 and

y0) to position i before that position produces correct sum and carry-out bits

Carries ripple through all n FAs before we can claim that the sum outputs are correct and may be used in further calculations



ENTITY rca_8bit ISPORT ( x , y : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; cout : OUT STD_LOGIC );

END rca_8bit ;

8-bit RC Adder 8-bit RC Adder - Structural - Structural

Description (1)Description (1)


ARCHITECTURE structure OF rca_8bit IScomponent fulladd is port(x, y, cin : IN STD_LOGIC; s, cout : OUT STD_LOGIC);end component;signal C : STD_LOGIC_VECTOR(8 downto 0);BEGIN

C(0) <= cin;U0 : fulladd port map(x(0), y(0), C(0), s(0), C(1));U1 : fulladd port map(x(1), y(1), C(1), s(1), C(2));U2 : fulladd port map(x(2), y(2), C(2), s(2), C(3));U3 : fulladd port map(x(3), y(3), C(3), s(3), C(4));U4 : fulladd port map(x(4), y(4), C(4), s(4), C(5));U5 : fulladd port map(x(5), y(5), C(5), s(5), C(6));U6 : fulladd port map(x(6), y(6), C(6), s(6), C(7));U7 : fulladd port map(x(7), y(7), C(7), s(7), C(8));cout <= C(8) ;

END structure ;





ENTITY rca_32bit ISPORT ( x , y : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ; cout : OUT STD_LOGIC; overflow : OUT STD_LOGIC );

END rca_32bit ;


Description (1)Description (1) 생성문 (generate statement) 사용

규칙적인 구조를 가지는 회로를 반복적으로 생성 반복 생성문 (for-generate) / 조건 생성문 (if-generate)


ARCHITECTURE structure OF rca_32bit IScomponent fulladd is port(x, y, cin : IN STD_LOGIC; s, cout : OUT STD_LOGIC);end component;signal C : STD_LOGIC_VECTOR(32 downto 0);BEGIN

C(0) <= cin;for k in 0 to 31 generate Uk : fulladd port map(x(k), y(k), C(k), s(k), C(k=1));end generate;cout <= C(32) ;

overflow <= C(32) xor C(31);END structure ;



for-generate 문장

Overflow 계산



ENTITY rca_nbit ISGENERIC( n : integer := 32);PORT ( x , y : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0) ; cout : OUT STD_LOGIC; overflow : OUT STD_LOGIC );

END rca_nbit ;

n-bit RC Adder n-bit RC Adder - Dataflow Description - Dataflow Description

(1)(1) 범용문 (Generic statement) 사용

회로의 크기 또는 입출력 크기를 매개변수 (parameter) 에 의해 결정 entity 또는 component 내에서 선언 반드시 port 문장보다 먼저 선언


ARCHITECTURE dataflow OF rca_nbit ISBEGIN

PROCESS(x, y, cin)variable sum : STD_LOGIC_VECTOR(n-1 downto 0);variable C : STD_LOGIC_VECTOR(n downto 0);variable k : integer;BEGIN C(0) := cin; for k in 0 to n-1 loop sum(k) := x(k) xor y(k) xor C(k);

C(k+1) := (x(k) and C(k)) or (y(k) and C(k)) or (x(k) and y(k)); end loop; s <= sum; cout <= C(n) ;

overflow <= C(n) xor C(n-1);END PROCESS;

END dataflow ;


(2)(2)



ENTITY rca_64bit ISPORT ( x , y : IN STD_LOGIC_VECTOR(63 DOWNTO 0) ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ; cout : OUT STD_LOGIC; overflow : OUT STD_LOGIC );

END rca_64bit ;


(3)(3) 예제 : 64-bit Ripple Carry Adder

n-bit RC Adder 회로를 이용하여 64-bit RC Adder 를 구현하여라


ARCHITECTURE structure OF rca_64bit IScomponent rca_nbit is generic(n : integer); port ( x , y : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

cin : IN STD_LOGIC ; s : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0) ; cout, overflow : OUT STD_LOGIC );

end component;BEGIN

U0 : rca_nbit generic map(64)port map(x, y, cin s, cout, overflow);

END structure ;


(4)(4)


Ripple-Carry Adder 의 장단점 장점 : 구조가 단순하다 단점 : 캐리 전파지연 (carry propagation delay) 으로 인한 늦은 연산 속도

Carry-Lookahead Adder 각 비트에서 발생하는 캐리를 미리 계산하는 회로를 부가함으로써 연산 속도를 향상 입력 비트 수가 커지면 부가 회로가 복잡해지는 문제점 발생

Hierarchical Carry-Lookahead Adder

Carry Lookahead Adder (1)Carry Lookahead Adder (1)


Carry-Lookahead Adder 원리 n-th full adder 에서의 sum & carry 논리식

Carry 논리식의 확장


S = Xn Yn Cn

Cn+1 = XnYn + (Xn Yn)Cn = Gn + PnCn

where Gn = XnYn : generate function Pn = Xn Yn: propagate function

Cn+1 = Gn + PnCn = Gn + Pn(Gn-1 + Pn-1Cn-1) = Gn + PnGn-1 + PnPn-1Cn-1

= Gn + PnGn-1 + PnPn-1Gn-2 + PnPn-1Pn-2Cn-2

… = Gn + PnGn-1 + PnPn-1Gn-2 + … + PnPn-1…P1G0 + PnPn-1Pn-2…P1P0C0

모든 캐리 비트를 입력

신호를 이용하여 미리

계산 가능



Carry-Lookahead Adder 회로도

Ripple-Carry Adder Carry-Lookahead Adder


Carry Lookahead Adder Carry Lookahead Adder 설계설계 (1)(1) CLA Block Diagram


CLA 구현 CGCPU(Carry-Generate/Carry-Propagate Unit) 설계

Carry Lookahead Adder Carry Lookahead Adder 설계설계 (2)(2)


ENTITY cgcpu_uint ISPORT ( a, b : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; g, p : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );

END cgcpu_unit ;

ARCHITECTURE dataflow OF cgcpu_unit ISBEGIN

g <= a and b;p <= a xor b;

END dataflow ;


CLA 구현 CLU(Carry-Lookahead Unit) 설계



ENTITY clu_uint ISPORT ( c0 : IN STD_LOGIC; g, p : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; c : OUT STD_LOGIC_VECTOR(4 DOWNTO 1) );

END clu_unit ;

ARCHITECTURE dataflow OF clu_unit ISBEGIN

c(1) <= g(0) or (p(0) and c0);c(2) <= g(1) or (p(1) and g(0)) or (p(1) and p(0) and c0);c(3) <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0))

or (p(2) and p(1) and p(0) and c0);c(4) <= g(3) or (P(3) and g(2)) or (p(3) and p(2) and g(1))

or (p(3) and p(2) and p(1) and g(0)) or (p(3) and p(2) and p(1) and p(0) and c0);

END dataflow ;


CLA 구현 CSU(Carry-Summation Unit) 설계



ENTITY csu_uint ISPORT ( c, p : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; s : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );

END csu_unit ;

ARCHITECTURE dataflow OF csu_unit ISBEGIN

PROCESS (C, P)variable k : integer;BEGIN for k in 0 to 3 loop s(i) <= p(i) xor c(i); end loop;END PROCESS;

END dataflow ;


CLA 구현 CLA(Carry-Lookahead Adder) 설계



ENTITY cla_4bit ISPORT ( a, b : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; cin : IN STD_LOGIC; s : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cout : OUT STD_LOGIC );

END cla_4bit ;

ARCHITECTURE structure OF cla_4bit IScomponent cgcpu_unit is

PORT ( a, b : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; g, p : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );

end component ;



component clu_unit isPORT ( c0 : IN STD_LOGIC; g, p : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; c : OUT STD_LOGIC_VECTOR(4 DOWNTO 1) );

end component ;component csu_unit is

PORT ( c, p : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; s : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );

end component ;SIGNAL c_tmp : STD_LOGIC_VECTOR(4 downto 1); SIGNAL g_tmp, p_tmp : STD_LOGIC_VECTOR(3 downto 0);

BEGIN CGCPU_B : cgcpu_uint port map(a, b, g_tmp, p_tmp); CLU_B : clu_uint port map( cin, g_tmp, p_tmp, c_tmp); CSU_B : csu_unit port map(c_tmp(3 downto 1) & cin, p_tmp, s); cout <= c_tmp(4); END structure ;


디지털 시스템에서의 감산 (Subtraction) 디지털 시스템에서의 음수 (Negative number) 표현

부호와 절대값 (Sign-and-Magnitude Representation) 1 의 보수 (1’s Complement Representation) 2 의 보수 (2’s Complement Representation)

감산 (Subtraction) Y = K – P = K + (-P) = K + (2n – P)

= K + (2n – 1 – P) + 1

가산기 (adder) 를 이용하여 감산을 수행

Adder & Subtractor Unit (1)Adder & Subtractor Unit (1)

2 의 보수

1 의 보수



Adder & Subtractor Unit 회로도


Adder & Subtractor Unit 설계



ENTITY rca_32bit ISPORT ( add_sub : IN STD_LOGIC;

a, b : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ; s : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); cout, overflow : OUT STD_LOGIC );

END rca_32bit ;

ARCHITECTURE structure OF rca_32bit IScomponent rca_nbit is generic(n : integer); port ( x , y : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

cin : IN STD_LOGIC ; s : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0) ; cout, overflow : OUT STD_LOGIC );

end component;


Adder & Subtractor Unit 설계


signal comp_1s : std_logic_vector(31 downto 0);

BEGINcomp_1s <= not b when add_sub = ‘1’ else

b;U0 : rca_nbit generic map(32)

port map(a, comp_1s, add_sub, s, cout, overflow);END structure ;


VHDL 에서의 산술 연산 VHDL 에서는 IEEE 라이브러리를 이용하여 산술 연산을

수행 가능 관련 package

ieee.std_logic_unsigned ieee.std_logic_signed ieee.std_logic_arith

가산 및 감산에 대해 실리콘 컴파일러가 선택적으로 회로를 선택하여 컴파일 수행

기본적으로 carry-lookahead adder 를 사용

산술연산을 이용한 산술연산을 이용한 Adder Adder 설계설계


4-bit Adder4-bit Adder

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity add_4bits_proc is port( a, b : in std_logic_vector(3 downto 0); s : out std_logic_vector(3 downto 0));end add_4bits_proc;

architecture a of add_4bits_proc isbegin

s <= a+b;end a;

+ 연산자가 사용될 때 꼭 사용 .

+ 연산자가 사용될 때 꼭 사용 .

Carry Out 이

16 이므로 14 를

더하면 30이됨 .

Carry Out 이

16 이므로 14 를

더하면 30이됨 .


32-bit Adder and Subtractor Unit32-bit Adder and Subtractor Unit

LIBRARY ieee ;USE ieee.std_logic_1164.all USE ieee.std_logic_signed.all;

ENTITY adder_32bit ISPORT ( add_sub : IN STD_LOGIC;

a, b : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ; s : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); cout, overflow : OUT STD_LOGIC );

END adder_32bit ;

ARCHITECTURE behavioral OF adder_32bit ISsignal sum : std_logic_vector(32 downto 0);BEGIN

PROCESS(a, b, add_sub)BEGIN if (add_sub) then sum <= (a(31)&a) – (b(31)&b); else sum <= (a(31)&a) + (b(31)&b);END PROCESS;s <= sum(31 downto 0);cout <= sum(32);overflow <= sum(32) xor a(31) xor b(31) xor sum(31);

END behavioral;

1 combinational logic lecture #6. 모바일컴퓨터특강 2 강의순서 combinational circuit...

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