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COMP541COMP541

Combinational Logic - 2Combinational Logic - 2

Montek SinghMontek Singh

Jan 18, 2007Jan 18, 2007

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Friday LabsFriday Labs No lab tomorrow – start Jan 26No lab tomorrow – start Jan 26

Fairly fast PCs in labFairly fast PCs in lab To use your laptop, go toTo use your laptop, go to

http://http://www.xilinx.com/ise/logic_design_prod/webpack.htmwww.xilinx.com/ise/logic_design_prod/webpack.htm

Windows or LinuxWindows or Linux Don’t install Modelsim – see meDon’t install Modelsim – see me

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HomeworkHomework HW1 will be assigned Jan 23, due Jan 30HW1 will be assigned Jan 23, due Jan 30 Send via email or paperSend via email or paper

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TopicsTopics More gatesMore gates Simple VerilogSimple Verilog Minterms and maxterms (again!)Minterms and maxterms (again!)

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Exclusive ORExclusive OR Exclusive ORExclusive OR What lay people mean by What lay people mean by

“or”“or” Symbol is Symbol is

Plus in a circlePlus in a circle

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Parity FunctionParity Function Recall how parity worksRecall how parity works

Ask classAsk class

Write truth table for two input even parityWrite truth table for two input even parity What needs to be generated for parity bit?What needs to be generated for parity bit?

What function of two inputs gives you this?What function of two inputs gives you this?

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XOR Gives XOR Gives Odd FunctionOdd Function

As many inputs as necessaryAs many inputs as necessary How do you get odd parity?How do you get odd parity? Design even parity generator for 3-bit Design even parity generator for 3-bit

signalsignal Perhaps make truth table and K-MapPerhaps make truth table and K-Map Draw with XOR, then sum-of-products w/ Draw with XOR, then sum-of-products w/

NAND gatesNAND gates How do you design a detector?How do you design a detector? How about a 7-bit ASCII character?How about a 7-bit ASCII character?

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BufferBuffer No inversionNo inversion No change, except in No change, except in

power or voltagepower or voltage Used to enable driving Used to enable driving

more inputsmore inputs

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OthersOthers

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Tri-StateTri-State Output w/ 3 states: H, L, and Hi-ZOutput w/ 3 states: H, L, and Hi-Z

High impedanceHigh impedance Behaves like no output connection if in Hi-Z stateBehaves like no output connection if in Hi-Z state Allows connecting multiple outputsAllows connecting multiple outputs

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Multiplexed with Hi-ZMultiplexed with Hi-Z

Normal operation is blue areaNormal operation is blue areaSmoke

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CMOS Transmission GatesCMOS Transmission Gates Act like electronic switchesAct like electronic switches

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XOR w/ Transmission Gate XOR w/ Transmission Gate

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Schematic DiagramsSchematic Diagrams Can you design a Pentium or a graphics chip Can you design a Pentium or a graphics chip

that way?that way?

Well, yes, but diagrams are overly complexWell, yes, but diagrams are overly complex These days people represent the same thing These days people represent the same thing

with text (code)with text (code)

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Hardware Description LanguagesHardware Description Languages Main ones are Verilog and VHDLMain ones are Verilog and VHDL

Others: Abel, SystemC, HandelOthers: Abel, SystemC, Handel

Origins as testing languagesOrigins as testing languages To generate sets of input valuesTo generate sets of input values

Levels of use from very detailed to more Levels of use from very detailed to more abstract descriptions of hdwabstract descriptions of hdw Think about C++ from assembly level description to Think about C++ from assembly level description to

very abstract HLLvery abstract HLL

Today – very basic use of VerilogToday – very basic use of Verilog

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Levels of VerilogLevels of Verilog StructuralStructural DataflowDataflow ConditionalConditional BehavioralBehavioral

Look at first two todayLook at first two today

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Example 1Example 1 Output is 1 when input < 011Output is 1 when input < 011

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Structural VerilogStructural Verilog Explicit description of gates and connectionsExplicit description of gates and connections Textual form of schematicTextual form of schematic Specify Specify netlistnetlist

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Example 1 in Structural VerilogExample 1 in Structural Verilogmodule example_1(X,Y,Z,F);module example_1(X,Y,Z,F); input X;input X; input Y;input Y; input Z;input Z; output F;output F;

//wire X_n, Y_n, Z_n, f1, f2;//wire X_n, Y_n, Z_n, f1, f2;notnot

g0(X_n, X),g0(X_n, X),g1(Y_n, Y),g1(Y_n, Y),g2(Z_n, Z);g2(Z_n, Z);

nandnandg3(f1, X_n, Y_n),g3(f1, X_n, Y_n),g4(f2, X_n, Z_n),g4(f2, X_n, Z_n),g5(F, f1, f2);g5(F, f1, f2);

endmoduleendmodule

Can also be input X, Y, Z;

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Slight Variation – Gates not Slight Variation – Gates not namednamedmodule example_1_c(X,Y,Z,F);module example_1_c(X,Y,Z,F);

input X;input X;

input Y;input Y;

input Z;input Z;

output F;output F;

not(X_n, X);not(X_n, X);

not(Y_n, Y);not(Y_n, Y);

not(Z_n, Z);not(Z_n, Z);

nand(f1, X_n, Y_n);nand(f1, X_n, Y_n);

nand(f2, X_n, Z_n);nand(f2, X_n, Z_n);

nand(F, f1, f2);nand(F, f1, f2);

endmoduleendmodule

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ExplanationExplanation Each of these gates is an Each of these gates is an instanceinstance

Like object vs classLike object vs class In first example, they had namesIn first example, they had names

notnotg0(X_n, X),g0(X_n, X),

In second example, no nameIn second example, no namenot(X_n, X);not(X_n, X);

Later see why naming can be usefulLater see why naming can be useful

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GatesGates Standard set of gates availableStandard set of gates available

and, or, notand, or, not nand, nornand, nor xor, xnorxor, xnor bufbuf

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Dataflow DescriptionDataflow Description

Basically a Basically a logical logical expressionexpression

No explicit No explicit gatesgates

module example_1_b(X,Y,Z,F);module example_1_b(X,Y,Z,F);

input X;input X;

input Y;input Y;

input Z;input Z;

output F;output F;

assign F = (~X & ~Y) | (~X & ~Z);assign F = (~X & ~Y) | (~X & ~Z);

endmoduleendmodule

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Design from SpecificationDesign from Specification So, now that we know how to implement, let’s talk So, now that we know how to implement, let’s talk

about how to specifyabout how to specify Usually we can make up a truth table from specsUsually we can make up a truth table from specs

Is there a mechanical way to come up with a function?Is there a mechanical way to come up with a function? Are there standard ways to structure the gates in the Are there standard ways to structure the gates in the

design?design?

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From Truth Table to FuncFrom Truth Table to Func Consider a truth tableConsider a truth table Can implement F by taking OR of all terms that Can implement F by taking OR of all terms that

are 1are 1

XYZZXYZYXZY XZ YX F

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Let’s Look at Standard FormsLet’s Look at Standard Forms Not necessarily simplest FNot necessarily simplest F But it’s mechanical way to go from truth table But it’s mechanical way to go from truth table

to functionto function

Definitions:Definitions: Product terms – AND Product terms – AND ĀBZ ĀBZ Sum terms – OR Sum terms – OR X + Ā X + Ā

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Definition: MintermDefinition: Minterm Product term in which all variables appear Product term in which all variables appear

once (complemented or not)once (complemented or not)

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Number of MintermsNumber of Minterms For For nn variables, there will be variables, there will be 22nn minterms minterms Like binary numbers from 0 to 2Like binary numbers from 0 to 2nn-1-1 In book, numbered same way (with decimal In book, numbered same way (with decimal

conversion)conversion)

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MaxtermsMaxterms Sum term in which all variables appear once Sum term in which all variables appear once

(complemented or not)(complemented or not)

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Minterm related to MaxtermMinterm related to Maxterm Minterm and maxterm with same subscripts Minterm and maxterm with same subscripts

are complementsare complements

ExampleExample

33 MZYXYZXm

Mjm j

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Sum of MintermsSum of Minterms OR all of the minterms OR all of the minterms

of truth table for rows of truth table for rows with a 1 outputwith a 1 output

XYZZXYZYXZY XZ YX F

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Sum of ProductsSum of Products Simplifying sum-of-minterms can yield a sum Simplifying sum-of-minterms can yield a sum

of productsof products Difference is each term need not have all Difference is each term need not have all

variablesvariables ANDs and one ORANDs and one OR

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Two-Level ImplementationTwo-Level Implementation Sum of products has 2 levels of gatesSum of products has 2 levels of gates

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More Levels of Gates?More Levels of Gates? What’s best?What’s best?

Hard to answerHard to answer More gate delays (more on this later)More gate delays (more on this later) But maybe we only have 2-input gatesBut maybe we only have 2-input gates

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Complement of a FunctionComplement of a Function Definition: 1s & 0s swapped in truth tableDefinition: 1s & 0s swapped in truth table Mechanical way to derive algebraic formMechanical way to derive algebraic form

Take the dualTake the dualRecall: Interchange AND and OR, and 1s & 0sRecall: Interchange AND and OR, and 1s & 0s

Complement each literalComplement each literal

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Complement of FComplement of F Not surprisingly, just sum of the other Not surprisingly, just sum of the other

mintermsminterms In this caseIn this case

mm11 + m + m33 + m + m44 + m + m66

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Product of MaxtermsProduct of Maxterms Recall that maxterm is true except for its own Recall that maxterm is true except for its own

casecase So M1 is only false for 001So M1 is only false for 001

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Product of MaxtermsProduct of Maxterms Can express F as AND of all rows that should Can express F as AND of all rows that should

evaluate to 0evaluate to 0

6431 MMMMF

))(( ZYXZYXF ))(( ZYXZYX

oror

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Product of SumsProduct of Sums Result: another standard formResult: another standard form ORs followed by ANDORs followed by AND

))(( ZYXZYXF

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Read & DoRead & Do Chapter 3, Sections 1 – 3Chapter 3, Sections 1 – 3

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Next WeekNext Week Software demo, and first labSoftware demo, and first lab Hierarchical DesignHierarchical Design

How do we express something more complex in How do we express something more complex in VerilogVerilog

ImplementationImplementation Brief look at logic familiesBrief look at logic families PackagesPackages

Timing characteristics, delayTiming characteristics, delay Then look at storing dataThen look at storing data