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Computer System Overview

Chapter 1

From: Operating Systems Internals and Design Principlesby William Stallings

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Operating System

• Exploits the hardware resources of one or more processors

• Provides a set of services to system users

• Manages secondary memory and I/O devices

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Basic Elements

• Processor• Main Memory

– volatile– referred to as real memory or primary memory

• I/O modules– secondary memory devices– communications equipment– terminals

• System bus– communication among processors, memory, and

I/O modules

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Processor

• Two internal registers– Memory address register (MAR)

• Specifies the address for the next read or write

– Memory buffer register (MBR)• Contains data written into memory or receives

data read from memory

– I/O address register– I/O buffer register

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Top-Level Components

PC MAR

IR MBR

I/O AR

I/O BR

CPU Main Memory

SystemBus

I/O Module

•••

•••

•••

Buffers

Instruction

012

n - 2n - 1

Data

Data

Data

Data

Instruction

Instruction

Figure 1.1 Computer Components: Top-Level View

PC = Program counterIR = Instruction registerMAR = Memory address registerMBR = Memory buffer registerI/O AR = Input/output address registerI/O BR = Input/output buffer register

Executionunit

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Processor Registers

• User-visible registers– Enable programmer to minimize main-

memory references by optimizing register use

• Control and status registers– Used by processor to control operating of

the processor– Used by privileged operating-system

routines to control the execution of programs

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User-Visible Registers

• May be referenced by machine language• Available to all programs - application

programs and system programs• Types of registers

– Data – Address

• Index• Segment pointer• Stack pointer

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User-Visible Registers

• Address Registers– Index

• Involves adding an index to a base value to get an address

– Segment pointer• When memory is divided into segments,

memory is referenced by a segment and an offset

– Stack pointer• Points to top of stack

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Control and Status Registers

• Program Counter (PC)– Contains the address of an instruction to be fetched

• Instruction Register (IR)– Contains the instruction most recently fetched

• Program Status Word (PSW)– Condition codes

– Interrupt enable/disable

– Supervisor/user mode

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Control and Status Registers

• Condition Codes or Flags– Bits set by the processor hardware as a

result of operations– Examples

• Positive result

• Negative result

• Zero

• Overflow

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Instruction Execution

• Two steps– Processor reads instructions from memory

• Fetches

– Processor executes each instruction

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Instruction Cycle

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Instruction Fetch and Execute

• The processor fetches the instruction from memory

• Program counter (PC) holds address of the instruction to be fetched next

• Program counter is incremented after each fetch

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Instruction Register

• Fetched instruction is placed in the instruction register

• Categories– Processor-memory

• Transfer data between processor and memory

– Processor-I/O• Data transferred to or from a peripheral device

– Data processing• Arithmetic or logic operation on data

– Control• Alter sequence of execution

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Characteristics of a Hypothetical Machine

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Example of Program Execution

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Direct Memory Access (DMA)

• I/O exchanges occur directly with memory

• Processor grants I/O module authority to read from or write to memory

• Relieves the processor responsibility for the exchange

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Interrupts

• Interrupt the normal sequencing of the processor

• Most I/O devices are slower than the processor– Processor must pause to wait for device

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Classes of Interrupts

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Program Flow of Control Without Interrupts

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Program Flow of Control With Interrupts, Short I/O Wait

UserProgram

WRITE

WRITE

WRITE

I/OProgram

I/OCommand

InterruptHandler

END

1

2a

2b

3a

3b

4

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(b) Interrupts; short I/O wait

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Program Flow of Control With Interrupts; Long I/O Wait

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Interrupt Handler

• Program to service a particular I/O device

• Generally part of the operating system

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Interrupts

• Suspends the normal sequence of execution

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Interrupt Cycle

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Interrupt Cycle

• Processor checks for interrupts

• If no interrupts fetch the next instruction for the current program

• If an interrupt is pending, suspend execution of the current program, and execute the interrupt-handler routine

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Timing Diagram Based on Short I/O Wait

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Timing Diagram Based on Short I/O Wait

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Simple Interrupt Processing

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Changes in Memory and Registers for an Interrupt

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Changes in Memory and Registers for an Interrupt

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Multiple Interrupts

• Disable interrupts while an interrupt is being processed

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Multiple Interrupts

• Define priorities for interrupts

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Multiple Interrupts

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Multiprogramming

• Processor has more than one program to execute

• The sequence the programs are executed depend on their relative priority and whether they are waiting for I/O

• After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt

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Memory Hierarchy

• Faster access time, greater cost per bit

• Greater capacity, smaller cost per bit

• Greater capacity, slower access speed

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Memory Hierarchy

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Going Down the Hierarchy

• Decreasing cost per bit

• Increasing capacity

• Increasing access time

• Decreasing frequency of access of the memory by the processor– Locality of reference

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Secondary Memory

• Nonvolatile

• Auxiliary memory

• Used to store program and data files

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Disk Cache

• A portion of main memory used as a buffer to temporarily to hold data for the disk

• Disk writes are clustered

• Some data written out may be referenced again. The data are retrieved rapidly from the software cache instead of slowly from disk

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Cache Memory

• Invisible to operating system

• Increase the speed of memory

• Processor speed is faster than memory speed

• Exploit the principle of locality

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Cache Memory

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Cache Memory

• Contains a copy of a portion of main memory

• Processor first checks cache

• If not found in cache, the block of memory containing the needed information is moved to the cache and delivered to the processor

Cache/Main Memory SystemMemoryaddress

012

012

C - 1

3

2n - 1WordLength

Block Length(K Words)

Block(K words)

Block

LineNumberTag Block

(b) Main memory

(a) Cache

Figure 1.17 Cache/Main-Memory Structure

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Cache Read Operation

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Cache Design

• Cache size– Small caches have a significant impact on

performance

• Block size– The unit of data exchanged between cache and

main memory– Larger block size more hits until probability of

using newly fetched data becomes less than the probability of reusing data that have to be moved out of cache

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Cache Design

• Mapping function– Determines which cache location the block

will occupy

• Replacement algorithm– Determines which block to replace– Least-Recently-Used (LRU) algorithm

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Cache Design

• Write policy– When the memory write operation takes

place– Can occur every time block is updated– Can occur only when block is replaced

• Minimizes memory write operations

• Leaves main memory in an obsolete state

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Programmed I/O

• I/O module performs the action, not the processor

• Sets appropriate bits in the I/O status register

• No interrupts occur• Processor checks status until

operation is complete

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Interrupt-Driven I/O

• Processor is interrupted when I/O module ready to exchange data

• Processor saves context of program executing and begins executing interrupt-handler

• No needless waiting

• Consumes a lot of processor time because every word read or written passes through the processor

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Direct Memory Access

• Transfers a block of data directly to or from memory

• An interrupt is sent when the transfer is complete

• Processor continues with other work