1

Cross ID Cross ID Tag identification emulatorTag identification emulator

Final presentationFinal presentationPerformed by:

Shuki Yasharzada

Raanan Steinberg

Yido Shalev

Project instructor:

Yossi Hipsh

Technion – Israel Institute of TechnologyDepartment of Electrical EngineeringHigh Speed Digital Systems Lab

2

OverviewOverview

Electromagnetic tracking and identifying system.

Optional applications:– Electromagnetic bar-code– Blind aid devices.– Information security.

3

OverviewOverview

TransmitterProduct

Receiver

4

Project GoalsProject Goals

Design and realization of a digital emulator which Identifies Cross ID tag units.

The emulator will operate in base band. Realization will be implemented by high

speed digital elements.

5

ProgressProgress

Learning the problem.General design.Equipment learning processBlock diagram:

– Choosing components.– ID gate realization.

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`ID gate testID gate test

High speed Pulse generator

T = 100trise DIP switchManually

controlling delay unit

SCOPE

triggertrigger

7

`Block diagramBlock diagram

And gate #2

Delay unit

Processor+

Control unit

High speed Pulse generator

T = 100trise

Tags

A/D

display

D2=T*G

T

G

Enable

E

Pulse

P

Gate Pulse

Tag Pulses

D1=P*E

∫D2

t0 + 100T

t0 dt

Latch

SetR

Reset

S

R

Int. clockT(Int.) ≈ 10T

Main transmitterTag ID unit

LAB-VIEW

And gate #1 Vout

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System characterizationSystem characterization

Pulse GeneratorDelay unitAnd unitLab-VIEW

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Pulse GeneratorPulse Generator

Pulse generator

33250A Agilent Pulse width 8 ns Rise time 5 ns Output Trigger

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System characterizationSystem characterization

Pulse GeneratorDelay unitAnd unitLab-VIEW

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Monolithic 8bit programmable delay line (3D7408-0.25)

Min delay 10-14 nsMax delay 77.75 ns0.25 ns step

Delay unitDelay unit

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System characterizationSystem characterization

Pulse GeneratorDelay unitAnd unitLab-VIEW

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And UnitAnd Unit

D1

1

2

3

4 5

6

7

8

MC10EL04

NC

NC

D0

D1

Vcc = 5.0 Volt1

2

3

4 5

6

7

8

MC10EL04

NC

NC

D0

D1

Vcc = 5.0 Volt

1

2

3

4 5

6

7

8

MC10ELT22

Q0

Q1

D0

Q0

Q1

PECL TTL

Vcc = 5.0 Volt1

2

3

4 5

6

7

8

MC10ELT22

Q0

Q1

D0

D1

Q0

Q1

PECL TTL

Vcc = 5.0 Volt

Enable Tag Pulse

E*PT

Q Q

Q Q

T*G

Gate Pulse

14

System characterizationSystem characterization

Pulse GeneratorDelay unitAnd unitLab-VIEW

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Controller block diagramController block diagram

8 digital outputs(delay unit control)

display LAB-VIEW

Controller+

Processor Analog input(from the integrator)

Digital output(enable for pulse generator)

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LAB-VIEWLAB-VIEW

Graphical programming language

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System characterizationSystem characterization

Pulse GeneratorDelay unitAnd unitLab-VIEW

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Identification test Identification test

Can we recognize the tag pulse?What is the pulse width (Tag*Gate)?What is the pulse rise and fall time?What is the delay (ref and T*G)?Can we determine the Tag delay

number?

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Agilent 33250Apulser

Delay

Delay

Delay

Delay

Agilent scope54246AAnd

unit

G.P

T.P

EN '1'

Gate unit

Tag unit

REF

T*G*EN

r

r

CC

mC

Z

0

80

0

sec]/[103

][50

2.2

3.1m3.1m

0.4m0.4m

1m1m

2.5m2.5m

1m1m

1m1m

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Tag emulator block diagramTag emulator block diagram

מקורפולסים

משהה נשלטפיצול(בר-תכנות)

פולסהמקור

לשלושהפולסיםזהים

משהה נשלט(בר-תכנות)

אוסף מתגים

פולס מושההפולס ייחוס המשמש

לכיול תג-הזיהוי

פולס מושהה

פולס מושהה

משהה נשלט(בר-תכנות)

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Tag emulator realizationTag emulator realization

33250A 80MHzPulse

Generator

LowVoltage

1:10CMOSClock

Driver - MPC946

3 DIP Switches

3D7408-0.25פולס מושהה

3D7408-0.25

שם היצרן:Agilent

שם היצרן: MOTOROLA

SEMICONDUCTOR

שם היצרן:data

delay device

פולס מושההפולס ייחוס המשמש

לכיול תג-הזיהוי

3D7408-0.25 פולס מושהה

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Agilent scope54246A

T.P

REF

r

r

CC

mC

Z

0

80

0

sec]/[103

][50

2.2

3.1m3.1m

1m1m

2.5m2.5m

1m1m

0.4m0.4m

Distribution Buffer Mpc 946

Agilent 33250APulse generator

And unit

G.P

EN '1'

T*G*EN

1m1m

controller

3D7408Delay Unit

DIPSWITCH

3D7408Delay Unit

DIPSWITCH

3D7408Delay Unit

DIPSWITCH

3D7408Delay Unit

DIPSWITCH

Dis

trib

uti

on

Bu

ffer

Mp

c 94

6

integrator

MC10ELT22

MC10ELT22

MC10EL04

MC10EL04

Gate unit

Tag unit

23

24

T*G delayT*G delay

REFREF

T*GT*G

25

T*G pulse widthT*G pulse width

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Final experiment Final experiment

Checking every line individually.Finding the reference pulse.Identifying the tag number.

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Search and identification Search and identification

Gate unitGate unit

Tag unitTag unit

G*TG*T

No overlapNo overlap

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Gate unitGate unit

Tag unitTag unit

G*TG*T

Partial overlapPartial overlap

Search and identification Search and identification

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Search and identification Search and identification

Gate unitGate unit

Tag unitTag unit

G*TG*T

Partial overlapPartial overlap

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Search and identification Search and identification

Gate unitGate unit

Tag unitTag unit

G*TG*T

Full overlapFull overlap

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Search and identification Search and identification

Gate unitGate unit

Tag unitTag unit

G*TG*T

Partial overlapPartial overlap

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Gate unitGate unit

Tag unitTag unit

G*TG*T

Partial overlapPartial overlap

Search and identification Search and identification

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Search and identification Search and identification

Gate unitGate unit

Tag unitTag unit

G*TG*T

No overlapNo overlap

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No overlap No overlap

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Full overlap gate unit = 36 nsFull overlap gate unit = 36 ns

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Partial overlapPartial overlap

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Tag unit name =14 nsTag unit name =14 ns

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Full overlap gate unit = 50 nsFull overlap gate unit = 50 ns

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ResultsResults

We have certain identification of the Tag pulse!

We have certain determination of Tag number!

T*G pulse width 10.4 ns. T*G rise time 680 ps and fall time 840 ps.

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Project summaryProject summary

The system can detect the tag.The system can be controlled

automatically by an external controller/computer.

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The EndThe End

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Appendix Delay Summary Delay Summary

* g_t

t_a a_s

0REF

0T*G

1 cable

3.1 cable + mpc946 + delay unit

+ R*C + 2.5m cable + translator + 1m cable

Delay /1 4.944[ ]1 *

Daley 32.63[ ]6.6 *

REF

T G

r

r

Delay m

Delay m

cc m ns

m

cCable ns

m

Delay u

REF *

12[ ] 946 3[ ] Translator=1.2[ns]

RC=8[ns]

Delay 4.944[ ] 56.83[ ]T G

nit ns mpc ns

ns Delay ns

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D1

1

2

3

4 5

6

7

8

MC10EL04

NC

NC

D0

D1

Vcc = 5.0 Volt1

2

3

4 5

6

7

8

MC10EL04

NC

NC

D0

D1

Vcc = 5.0 Volt

1

2

3

4 5

6

7

8

MC10ELT22

Q0

Q1

D0

Q0

Q1

PECL TTL

Vcc = 5.0 Volt1

2

3

4 5

6

7

8

MC10ELT22

Q0

Q1

D0

D1

Q0

Q1

PECL TTL

Vcc = 5.0 Volt

Enable Tag Pulse

E*PT

Q Q

Q Q

T*G

Gate Pulse

And unitAnd unit

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Electrical scheme for the tag emulator (1)

Pulse Generator

) IN (13D7408-0.25

15 (OUT)

Vcc 3.3v

10KΩ

Vcc 3.3v

Pulse in

SMA

Pulse out

Vcc 3.3v

Vcc 3.3v

Vcc 3.3v

Vcc 3.3v

Vcc 3.3v Vcc 3.3v

) IN (13D7408-0.25

15 (OUT)Pulse out

Pulse out

10KΩ

10KΩ

100Ω

100Ω

100Ω

100Ω

100Ω

RFI - Filter

Vcc 3.3v

Test points

) IN (13D7408-0.25

15 (OUT)

• Connections map for the MPC946

9V DC

45

DIPswitch

#nDIP

switch #n

Output

Qa1 from MPC946

10KΩ

10KΩ

9V DC RFI - Filter

Vcc 5v

Vcc 5v

Vcc 5v

"1"

10KΩ

1KΩ

SMA

"1"

"1"

3D7408-0.25

Electrical scheme for the tag emulator (2)

• Connections map for the 3D7408-0.25