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1 Delay Insensitivity does not mean slope insensitivity! Vainbaum Yuri

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2 Delay Insensitivity does not mean slope insensitivity! Paper presented in NOC-2010 Authors : Florent Ouchet, Katell Morin-Allory, Laurent Fesquet - TIMA Laboratory

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3 Talk outline Phenomenon highlight C-element implementation models C-element robustness for slow slopes Improving C-element impelemetaton Area/power penalty analysis

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4 Asynchronous circuit quality Self-timed circuit robustness evaluation: PVT variations Chip aging: transistors, nets, vias Low supply voltage Harden the behavior in harsh environment Avoid dead locks Avoid wrong operations

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5 Asynchronous circuit quality-Slopes Local effects on the circuit: Very slow signal variations Slow slopes on pads and nets Ex.: In synchronous design slopes are treated carefully Tools developed to check slopes Designer must fix all slopes violations

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6 Asynchronous circuit quality-Slopes Self-timed circuit assumptions usually reduced to delays But slopes must be considered

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7 2 half-buffers

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8 1 fast output environment

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9 2 half-buffers 1 fast output environment 1 slow input environment

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17 Slow slop!

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19 Slow slop!

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21 VTL- voltage level for logic 0 VTH- voltage level for logic 1

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22 REQ M V TH V TL

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23 REQ M V TH V TL

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24 VTH>VTL safe and robust behavior VTL>VTH, VTH < Vin < VTL C-element sensitive to noise

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25 Assumption: VTH