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Design of Two-Level Multiple-Output Networks

Design a network with four inputs and threeoutputs which realizes the functionsF1(A,B,C,D) = m(11,12,13,14,15)

F2(A,B,C,D) = m(3,7,11,12,13,15)

F3(A,B,C,D) = m(3,7,12,13,14,15)

ABAB

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Direct Realization(each function as a min.sum of prime implicants)

Note: AB is common to F1, F3

Multiple-Output Realization

= AB+ACD

= ABC’+A’CD+ACD

= A’CD+AB

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Example: Using Common Terms in Multiple Output Network Design

f1 = a’bd + abd+ab’c’ + b’cf2 = c + a’bd f3 = bc + ab’c’ + abd

8 gates, 22 gate inputs

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Best Soln.

Soln. Requires extra gate

Another Example

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Soln. with max.number of common terms (8 gates, 26 inputs)

Best Soln.has no common terms(7 gates, 18 inputs)

Another Example

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Code Converters

Code converters – take an input code, translate to its equivalent output code.

Codeconverter

Inputcode

Outputcode

Example: BCD to Excess-3 Code Converter.

Input: BCD digit

Output: Excess-3 digit

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BCD-to-Excess-3 Code Converter Truth table:

BCD Excess-3A B C D W X Y Z

0 0 0 0 0 0 0 1 11 0 0 0 1 0 1 0 02 0 0 1 0 0 1 0 13 0 0 1 1 0 1 1 04 0 1 0 0 0 1 1 15 0 1 0 1 1 0 0 06 0 1 1 0 1 0 0 17 0 1 1 1 1 0 1 08 1 0 0 0 1 0 1 19 1 0 0 1 1 1 0 0

10 1 0 1 0 X X X X11 1 0 1 1 X X X X12 1 1 0 0 X X X X13 1 1 0 1 X X X X14 1 1 1 0 X X X X15 1 1 1 1 X X X X

W =m(5,6,7,8,9)

x = m(1,2,3,4,9)

y = m(0,3,4,7,8)

z = m(0,2,4,6,8)

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AB 01

1

00 CD 00

1

1

01

11

10

x 1

x 1

x x

x x

11 10

0

1

3

2

4

5

7

6

12 8

9

11

10

13

15

14

x =m(1,2,3,4,9)+d(10,11,12,13,14,15)bc’d’+b’d+b’c=bc’d’+b’(c+d)

y =m(0,3,4,7,8)+ d(10,11,12,13,14,15) = c’d’+cd

011

1 00

CD 00

11

01 11

10

x 0x 1x xx x

11 10

0

1

3

2

4

5

7

6

12 8

9

11

10

13

15

14

AB

01

1 1 00 CD 00

1 1

01

11

10

x 1

x

x x

x x

11 10

0

1

3

2

4

5

7

6

12 8

9

11

10

13

15

14

AB

W =m(5,6,7,8,9)+d(10,11,12,13,14,15)= a+bc+bd = a+b(c+d)

z =m(0,2,4,6,8)+ d(10,11,12,13,14,15) = d’

01

1 00 CD 00

1 1

01

11

10

x 1

x

x x

x x

11 10

0

1

3

2

4

5

7

6

12 8

9

11

10

13

15

14

AB

1

Underlinedterms arecommon

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Multi-Output NAND and NOR Networks

Conversion to anetwork of all NAND or allNOR gates can also be done for the case of multiple-output networks, using method of Section 8.6, p. 194

(a) Network of AND and OR gates

(b) NOR network

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Multiplexers

2/1 Multiplexer (MUX)

I0

I1

Z

S

if S = 0, then Z = I0

if S = 1, then Z = I1

S is the Control Input used to select one of the data inputs I0 , I1 and connect it to the output terminal, Z.

Control Input

Data

Inputs

Z = I0S’ + I1S

I0

S’

I1S

Z

Logic Diagram

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Higher Order Muxes

I0

I1 ZI2

I3

4/1 Mux

if S = “00”, then Z = I0

if S = “01”, then Z = I1

if S = “10”, then Z = I2

if S = “11”, then Z = I3

I0

I1

Z

S[2:0]

I2

I3

8/1 Mux

3

I4

I5I6

I7

Z = I0 S1’ S0’ + I1 S1’ S0 + I2 S1 S0’ + I3 S1 S0

S1 S0

Note: S[2:0] means the three control inputs S2 S1 S0 <--lsb

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Logic Diagram for 8-to-1 Multiplexer

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To build a 2/1 mux for 4-bit wide busses, need four 1-bit 2/1 muxes.

I0

I1

Z

S

A[3:0]

B[3:0]D[3:0]

I0I1 Z

S

I0I1

ZS

I0I1

Z

S

I0I1

ZS

A0B0

A1B1

A2B2

A3B3

Z0

Z1

Z2

Z3

S

Muxes are often used to select groups of bits arranged in busses.

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A 4-to-1 MUX can realize any 3-variable function with no added Logic gates.

Example: Realize F(A,B,C)= A’B’ + AC

Soln.: Expanding F so that all terms include both control inputs, A and B, yieldsF = A’B’ + AC(B’+B) = A’B’1 + AB’C + ABCThe general eqn. For 4-to-1 MUX isF = A’B’I0 + A’BI1+ AB’I2+ ABI3Comparing eqns. We see they will be identical ifI0 =1, I1 =0, I2 =C, I3 =C

Function Realization using MUX

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Example: Consider the function Z(A,B,C,D) = m(0,1,3,6,7,8,11,12,14) and implement it

using an 8-to-1MUXSoln.: Assume that A,B,C are applied to control inputs s2,s1,s0 resp.Then all 16 possible minterms that can be generated by the MUX can be represented in a table.

000 001 010 011 100 101 110 111

I0 I1 I2 I3 I4 I5 I6 I7

D’ 0 2 4 6 8 10 12 14

D 1 3 5 7 9 11 13 15

1 D 0 1 D’ D D’ D’

Working out the bottom row tells us what to apply to I0, I1, 12, etc.How to work it out? e.g. I0 col D’+D=1, I1 col only minterm with D appears,(apply D), I2 col no minterms used (apply 0), I3 col D’+D=1, I4 col. only minterm with D’ appears(apply D’).

Function Realization using MUX

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Example: Continued

The function is then realized with an 8-to-1 MUXwith ABC applied to the control inputs and the values found in the table to I0, I1, I2, etc.

S2 S1 S0

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Example: Continued Alternate Solution

Represent all of the minterms of Z on a k-map. Then obtaingroupings corresponding to [I0 = 000 with both D’ and D][I1=001 with both D’ and D] etc. Each of the two-minterm groupingscan be thought of as a 1-variable k-map in D only and simplified.

One-variable k-maps

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Example: Continued Yet anotherAlternate Solution

This time assume that A,B,D are applied to control inputs S2,S1,S0 resp.

000 001 010 011 100 101 110 111

I0 I1 I2 I3 I4 I5 I6 I7

C’ 0 1 4 5 8 9 12 13

C 2 3 6 7 10 11 14 15

C’ 1 C C C’ C 1 0

D

C’

C’

1

0

C

C

1

C

S0S1S2

Mux Realization with Control Inputs A, B, and D

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Example: Continued Yet anotherAlternate Solution usingexternal gates

00 01 10 11

I0 I1 I2 I3

00 0 4 8 12

01 1 5 9 13

11 3 7 11 15

CD

10 2 6 10 14

Table method in this case isequivalent to four 2-variable K-maps

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Decoders

This decoder generates all minterms of of the three input variables

Exactly one of the output lines will be 1 for each combination of the input variables.

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Decoders

Note: Active low outputs

7442 4-to-10 decoder

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f1 = (m1’m2’ m4’)’

= m1 + m2 + m4

f2 = (m4’m7’ m9’)’

=m4 + m7 + m9

Realization of Multiple-Output Network using Decoder

Can realize a function by ORing together selected minterm outputs.In this case outputs are active low, so NAND gates are used (effectively ORing together these outputs).