1 digital fundamentals chapter 8 flip-flops and related devices resource: cyu / csie / yu-hua lee /...

1

Digital Fundamentals

Chapter 8Flip-Flops and Related Devices

Resource:CYU / CSIE / Yu-Hua Lee /

E-mail:[email protected]

Not made by Engr. Umar Talha, special thanks to E#ngr. Jahanzeb Ahmed

2

Chapter 8Flip-Flops and Related Devices 8-1 Latches 8-2 Edge-Triggered Flip-Flops 8-3 Master-Slave Flip-Flops 8-4 Flip-Flop Operating Characteristics 8-5 Flip-Flop Applications 8-6 One-Shots 8-7 The 555 Timer 8-8 Troubleshooting 8-9 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E-mail:[email protected]

3

Figure 8--1 Two versions of SET-RESET (S-R) latches. Open file F08-01 and verify the operation of both latches.


4

Figure 8--2 Negative-OR equivalent of the NAND gate S-R latch in Figure 8-1(b).


5

Figure 8--3 The three modes of basic S-R latch operation (SET, RESET, no-change) and the invalid condition.


6

Figure 8--4 Logic symbols for the S-R and S-R latch.


7

Figure 8--5


8

Figure 8--6 The S-R latch used to eliminate switch contact bounce.


9

Figure 8--7 The 74LS279 quad S-R latch.


10

Figure 8--8 A gated S-R latch.


11

Figure 8--9


12

Figure 8--10 A gated D latch.


13

Figure 8--11


14

Figure 8--12 The 74LS75 quad gated D latches.


15

Chapter 8 Flip-Flops and Related Devices 8-1 Latches 8-2 Edge-Triggered Flip-Flops 8-3 Master-Slave Flip-Flops 8-4 Flip-Flop Operating Characteristics 8-5 Flip-Flop Applications 8-6 One-Shots 8-7 The 555 Timer 8-8 Troubleshooting 8-9 Programmable Logic


16

Figure 8--13 Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative edge-triggered).


17

Figure 8--14 Operation of a positive edge-triggered S-R flip-flop.


18

Figure 8--15


19

Figure 8--16


20

Figure 8--17 Edge triggering.


21

Figure 8--18 Flip-flop making a transition from the RESET state to the SET state on the positive-going edge of the clock pulse.


22

Figure 8--19 Flip-flop making a transition from the SET state to the RESET state on the positive-going edge of the clock pulse.


23

Figure 8--20 A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter.


24

Figure 8--21


25

Figure 8--22 A simplified logic diagram for a positive edge-triggered J-K flip-flop.


26

Figure 8--23 Transitions illustrating the toggle operation when J =1 and K = 1.


27

Figure 8--24


28

Figure 8--25


29

Figure 8--26 Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs.


30

Figure 8--27 Logic diagram for a basic J-K flip-flop with active-LOW preset and clear inputs.


31

Figure 8--28 Open file F08-28 to verify the operation.


32

Figure 8--29 Logic symbols for the 74AHC74 dual positive edge-triggered D flip-flops.


33

Figure 8--30 Logic symbols for the 74HC112 dual negative edge-triggered J-K flip-flops.


34

Figure 8--31


35



36

Figure 8--32 Basic logic diagram for a master-slave J-K flip-flop.


37

Figure 8--33 Pulse-triggered (master-slave) J-K flip-flop logic symbols.


38

Figure 8--34


39



40

8-4 Flip-Flop Operating Characteristics Propagation Delay Times

tPLH

tPHL

Set-up Time ts

Hold Time th

Maximum Clock Frequency fmax

Pulse Widths tw

Power Dissipation


41

Figure 8--35 Propagation delays, clock to output.


42

Figure 8--36 Propagation delays, preset input to output and clear input to output.


43

Figure 8--37 Set-up time (ts). The logic level must be present on the D input for a time equal to or greater than ts before the triggering edge of the clock pulse for reliable data entry.


44

Figure 8--38 Hold time (th). The logic level must remain on the D input for a time equal to or greater than th after the triggering edge of the clock pulse for reliable data entry.


45

Chapter 8 Flip-Flops and Related Devices 8-1 Latches 8-2 Edge-Triggered Flip-Flops 8-3 Master-Slave Flip-Flops 8-4 Flip-Flop Operating Characteristics 8-5 Flip-Flop Applications8-5 Flip-Flop Applications 8-6 One-Shots 8-7 The 555 Timer 8-8 Troubleshooting 8-9 Programmable Logic


46

Figure 8--39 Example of flip-flops used in a basic register for parallel data storage.


47

Figure 8--40 The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK.


48

Figure 8--41 Example of two J-K flip-flops used to divide the clock frequency by 4. QA is one-half and QB is one-fourth the frequency of CLK.


49

Figure 8--42


50

Figure 8--43


51

Figure 8--44 Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown.


52

Figure 8--45


53

Figure 8--46


54



55

Figure 8--47 A simple one-shot circuit.


56

Figure 8--48 Basic one-shot logic symbols. CX and RX stand for external components.


57

Figure 8--49 Nonretriggerable one-shot action.


58

Figure 8--50 Retriggerable one-shot action.


59

Figure 8--51 Logic symbols for the 74121 nonretriggerable one-shot.


60

Figure 8--52 Three ways to set the pulse width of a 74121.


61

Figure 8--53 Logic symbol for the 74LS122 retriggerable one-shot.


62

Figure 8--54


63

Figure 8--55 A sequential timing circuit using three 74LS122 one-shots.


64



65

Figure 8--56 Internal functional diagram of a 555 timer (pin numbers are in parenthesis).


66

Figure 8--57 The 555 timer connected as a one-shot.


67

Figure 8--58 One-shot operation of the 555 timer.


68

Figure 8--59 The 555 timer connected as an astable multivibrator (oscillator).


69

Figure 8--60 Operation of the 555 timer in the astable mode.


70

Figure 8--61 Frequency of oscillation as a function of C1 and R1 1 2R2. The sloped lines are values of R1 1 2R2.


71

Figure 8--62 The addition of diode D1 allows the duty cycle of the output to be adjusted to less than 50 percent by making R1 , R2.


72

Figure 8--63 Open file F08-63 to verify operation.


73



74

Figure 8--64 Two-phase clock generator with ideal waveforms. Open file F08-64 and verify the operation.


75

Figure 8--65 Logic analyzer displays for the circuit in Figure 8-64.


76

Figure 8--66 Two-phase clock generator using negative edge-triggered flip-flop to eliminate glitches. Open file F08-66 and verify the operation.


77



78

Figure 8--67 GAL block diagrams.


79

Figure 8--68 The GAL22V10 OLMC.


80

Figure 8--69 The GAL16V8 OLMC.


81

Combinational LogicChapter 8

Digital System Application


82

Figure 8--70 Traffic light control system block diagram.


83

Figure 8--71 Block diagram of the timing circuits.


84

Figure 8--72


85

Figure 8--73


86

Figure 8--74


87

Combinational LogicChapter 8

Problems


88

Figure 8--75


89

Figure 8--76


90

Figure 8--77


91

Figure 8--78


92

Figure 8--79


93

Figure 8--80


94

Figure 8--81


95

Figure 8--82


96

Figure 8--83


97

Figure 8--84


98

Figure 8--85


99

Figure 8--86


100

Figure 8--87


101

Figure 8--88


102

Figure 8--89


103

Figure 8--90


104

Figure 8--91


105

Figure 8--92


106

Figure 8--93


107

Figure 8--94


108

Figure 8--95


109

Figure 8--96


110

Figure 8--97


111

Figure 8--98


112

Figure 8--99


113

Figure 8--100


114

Figure 8--101


115

Figure 8--102


116

Figure 8--103


117

Figure 8--104


118

Figure 8--105


119

Figure 8--106


120

Figure 8--107


121

Figure 8--108


122

Figure 8--109


123

Figure 8--110


124

Figure 8--111


125

Figure 8--112


126

Figure 8--113


127

Figure 8--114


128

Figure 8--115

1 digital fundamentals chapter 8 flip-flops and related devices resource: cyu / csie / yu-hua lee /...

Documents

gated sr latch

reset sr latches

74ls279 quad sr latch

nand gate sr latch

edgetriggered flipflops8

negative edge

flipflop applications8

edge triggering