1 © fraunhofer iis/eas | m. waqas chaudhary | iwlpc | october 13-15, 2015 interposer-based...
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
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INTERPOSER-BASED INTEGRATION OF ADVANCED MEMORIES AND ASIC
M. Waqas ChaudharyAdvanced System Integration GroupFraunhofer IIS, Design Automation Division EAS
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
AGENDA
Motivation
Memory-ASIC System
ASIC Design cost modelling
Trade-offs discussion
Design Examples
Conclusion
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
2.5D IntegrationInterposer-based Integration (Technology summary)
Passive die with TSVs, top and bottom metallization
Carrier for active dies High interconnect density (e.g. 10µm
width/spacing) Top-bottom or side-by-side
configurations Integrated passives in interposer
Targets
Dense integration of heterogeneous dies
High performance systems(e.g. memory-processor interface)
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
AGENDA
Motivation
Memory-ASIC System
ASIC Design cost modelling
Trade-offs discussion
Design Examples
Conclusion
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
Tire pressure monitor
Image sensor / processor integration
Interposer für JEDEC WideIO/Processor
Heterogeneous IntegrationDifferent examples
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
Memories Overview
Memory Per pin max data
rate (Gb/s)
Interface signals
per channel
400-Gb/s data rate requirements
Channels Signals
Wide IO-2 1.067 97 6 582
HBM 2 202 2 404HMC 15 4 40 160LPDDR4 3.2 45 8 360
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
AGENDA
Motivation
Memory-ASIC System
ASIC Design cost modelling
Trade-offs discussion
Design Examples
Conclusion
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
DESIGN COST MODELLING
lk
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
DESIGN OPTIONS AND DEPENDENCIES
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
AGENDA
Motivation
Memory-ASIC System
ASIC Design cost modelling
Trade-offs discussion
Design Examples
Conclusion
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
TRADE-OFFS
HMC compatible Serdes Phy cost
Signal and power integrity
Serdes power addition to the Interfaced CPU Package
Interposer routing layers and widths for 2.5D systems
Resistive loss in interposer for HBM IOs
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
AGENDA
Motivation
Memory-ASIC System
ASIC Design cost modelling
Trade-offs discussion
Design Examples
Conclusion
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
HMC BASED SYSTEMH
MC
(4-Lin
k x1
6
lan
e)
CPU
31mm
40 lanes
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
HBM BASED SYSTEM
HB
MCPU
404 interconnects
Min 1.21mm
Min
1.2
1m
m
Interposer
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
WIDE IO-2 BASED SYSTEM
Wid
e IO
-2
CPU
6 channels
Min 1.04mmM
in 1
.04
mm
Interposer
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
LPDDR4 2.5D SYSTEMLP
DD
R4
(Qu
ad
ch
an
nel
packa
ge
x6
4)
CPU
15mm
LPD
DR
4
(Qu
ad
ch
an
nel
packa
ge
x6
4)
15mm
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
AGENDA
Motivation
Memory-ASIC System
ASIC Design cost modelling
Trade-offs discussion
Design Examples
Conclusion
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
CONCLUSION
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
150 / 200 / 300 mm wafer processing Design services and design tools Clean room facilities: 3500 m² Test / Analytic-Laboratories : 900 m²
Fraunhofer Cluster 3D-IntegrationMembers and Facts
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© Fraunhofer IIS/EAS | M. Waqas Chaudhary | IWLPC | October 13-15, 2015
Fraunhofer Cluster 3D-IntegrationCompetencies and Services
PROTOTYPING
PILOT MANUFACTURIN
G
SMALL VOLUME PRODUCTION