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1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian Curic, Aude Maignan, Christos Sofronis

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Page 1: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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From Simulink to Lustre to TTA: a layered approach for distributed embedded

applications

Stavros TripakisVERIMAG

Joint work with:Paul Caspi, Adrian Curic, Aude Maignan, Christos

Sofronis

Page 2: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Problem and approach

• How to develop embedded software ?– Safely: safety-critical applications– Efficiently: development cost, time-to-

market

• “Model-based” approach:– High-level design models– Analysis techniques: catch bugs early– Synthesis techniques: correct-by-

construction implementations

Page 3: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Execute

Design

Implement

Our view: a development process in three layers,

supported by:Models

Programminglanguages

OS, middleware,HW architecture

Automation is key!

Semantic preservation!

Page 4: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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TTA

Simulink/Stateflow

Lustre

Our work

• European IST projects:– “NEXT TTA” (2002-2004) and “RISE” (2003-2005).

• Automotive applications: – Audi.

Page 5: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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A Simulink model (parts)

Page 6: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Time Triggered Architecture (TTA)

• Picture of TTA

• Time-triggered:– Processors synchronize their clocks.– Static TDMA non-preemptive scheduling for tasks running

on processors and messages transmitted on the bus.• Fault-tolerance services

Page 7: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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TTA

Simulink/Stateflow

Lustre

Why these choices?

De-facto standardin automotive

Formal semantics,analysis tools,C code generators

Close to synchronous semantics, Audi likes it

Page 8: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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The development process

1. Design/simulate controller in Simulink/Stateflow.

2. Translate it to Lustre.3. Verify the Lustre

program (transparent).4. Distribute the Lustre

program on TTA.5. Generate C code,

compile and run.

TTA

Simulink/Stateflow

Lustre

Page 9: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Plan of talk

• Translating Simulink to Lustre.

• Distributing Lustre on TTA.

• Tool-chain and case studies.

Page 10: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Plan of talk

• Translating Simulink to Lustre.

• Distributing Lustre on TTA.

• Tool-chain and case studies.

Page 11: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Translating Simulink to Lustre

• We only translate discrete-time Simulink: the controller to be implemented.

• Goal: preserve semantics of Simulink.What semantics?

Page 12: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Simulink semantics

• Informal: described in documentation.

• Defined by the simulator.

• Multiple different semantics: user options.

Page 13: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Translation goal

• input/output semantics of generated Lustre program

=• input/output behaviour of original

Simulink model given by Mathworks simulator,

• assuming a fixed set of user-defined options

Page 14: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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From Simulink to Lustre

• A glance into Lustre

• Translation:– Type inference– Clock inference– Hierarchical block-by-block

translation

Page 15: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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A glance into Lustre• A Lustre program models an I/O automaton:

• Implementing a Lustre program:– Read inputs;– Compute next state and outputs;– Write outputs;– Update state;

memory(state)

step function(transition)

inputs outputs

Repeat atevery “trigger”(external event).

Page 16: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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A glance into Lustre

• A simple Lustre program:

• No inputs• Output: x• State: pre(x) (previous value of x)

node Counter() returns(x:int);let x = 0 -> pre(x) + 1;tel

Page 17: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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A glance into Lustre• Multi-clocked (e.g., multi-periodic)

systems:x = 0 -> pre(x) + 2;b = true -> not pre(b);y = x when b;

time 0 1 2 3 4 …

x 0 2 4 6 8 …

b true false true false true …

y 0 4 8 …

clock(y) = b

clock(x) = basic

Page 18: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Simulink versus Lustre

• Both data-flow style.• Both hierarchical:

– Graphical versus textual.

• Different type mechanisms:– Mandatory/explicit in Lustre, not in Simulink.

• Different timing mechanisms:– Implicit logical clocks in Lustre.– Sample times and triggers in Simulink.

A B

C

xy

z wu

sv

Page 19: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Translation steps

1. Type inference

2. Clock inference

3. Hierarchical block-by-block translation

Page 20: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Translation steps

1. Type inference

2. Clock inference

3. Hierarchical block-by-block translation

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Simulink types• Types are not mandatory in Simulink.• Available types: double, single, int32,

int16, int8, …, boolean.• By default signals are “double”.• Basic block type signatures:

Constant , SimNum

Adder … , SimNum

Relation boolean, SimNum

Logical Operator boolean … boolean boolean

Disc. Transf. Func. double double

Data Type Conv

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Simulink type inference• Fix-point computation on a lattice:• E.g.:

+xy

z

Fix-point equations:tx = sup(double, ty, tz)ty = sup(double, tx, tz)tz = sup(double, tx, ty)

Least fix-point:tx = ty = tz = double

error

boolean

int8single

double

_|

Page 23: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Simulink type inference• Fix-point computation on a lattice:• E.g.:

+xy

z

Fix-point equations:tx = int8

ty = sup(double, tx, tz)tz = sup(double, tx, ty)

Least fix-point:tx = ty = tz = int8

error

boolean

int8single

double

_|

int8

Page 24: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Simulink type inference• Fix-point computation on a lattice:• E.g.:

+xy

z

Fix-point equations:tx = sup(double, ty, tz)ty = sup(double, tx, tz)tz = sup(double, tx, ty, boolean, tw)tw = sup(boolean, tz)

notw

error

boolean

int8single

double

_|

Page 25: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Simulink type inference• Fix-point computation on a lattice:• E.g.:

+xy

z

Fix-point equations:tx = sup(double, ty, tz)ty = sup(double, tx, tz)tz = sup(double, tx, ty, boolean, tw)tw = sup(boolean, tz)

tz = error

notw

error

boolean

int8single

double

_|

Page 26: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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The overall algorithm• Generate fix-point equations.

• Find least fix-point.

• If error, reject model.

• Otherwise, map Simulink types to Lustre types:– double, single: real– int32, int16, int8, … : int– boolean: bool

Page 27: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Translation steps

1. Type inference

2. Clock inference

3. Hierarchical block-by-block translation

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Time in Lustre

• One mechanism (clocks) + one rule:– Cannot combine signals of different clocks:

x = 0 -> pre(x) + 2;b = true -> not pre(b);y = x when b;z = x + y;

time 0 1 2 3 4 …

x 0 2 4 6 8 …

b true false true false true …

y 0 4 8 …

Compiler error

Page 29: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Time in Simulink

• Simulink has two timing mechanisms:– sample times : (period,phase)

• Can be set in blocks: in-ports, UD, ZOH, DTF, …• Defines when output of block is updated.• Can be inherited from inputs or parent system.

– triggers :• Set in subsystems• Defines when subsystem is “active” (outputs

updated).• The sample times of all children blocks are

inherited.A

B

xy

z w

s trigger Simulink triggers=

Lustre clocks

Page 30: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Time in Simulink

• Greatest-common divisor (GCD) rule :– A block fed with inputs with different rates:

• Other timing rules, e.g.:– Insert a unit delay when passing from a

“slow” block to a “fast” block.

2 ms1 ms

xz

3 msy

Page 31: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Overview of clock inference algorithm

• Infer the sample time of every Simulink signal.

• Check Simulink’s timing rules.

• Create Lustre clocks for Simulink sample times and triggers.

– Basic clock: GCD of all sample times, e.g., 1ms.– Other clocks: multiples of basic clock, e.g.

true false true false = 2ms.

Page 32: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Sample time inference

• Basic idea: same as type inference.

– Poset with pairs (period, phase).– No error element.– p1 p2 if p1 is “multiple” of p2

• Complex definition of multiple because of phase.

– Sup is “GCD”.– Although poset is infinite, termination

guaranteed:• Can remain within a finite part of the poset (set of

all sample times in the Simulink model, closed by GCD).

Page 33: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Translation steps

1. Type inference

2. Clock inference

3. Hierarchical block-by-block translation

Page 34: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Hierarchical translation

• A Simulink model can be seen as a tree:– root system, subsystems, basic blocks (leaves).

• A simple block (+, gain, …) is translated to a basic Lustre operator (+, , …).

• Complex blocks (transfer functions, …) are translated into Lustre nodes.

• Subsystems are translated into Lustre nodes.

Page 35: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Bottom-up translation

node A(x,y) returns(s);…node B(s,u) returns(v);…node C(z) returns(u,w);…node Root(x,y,z) returns(v,w);var s, u;let s = A(x,y); v = B(s,u); (u,w) = C(z);tel

A B

C

xy

z wu

sv

Simulink model

Lustre program

Page 36: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Plan of talk

• Translating Simulink to Lustre.

• Distributing Lustre on TTA.

• Tool-chain and case studies.

Page 37: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Distributing Lustre on TTA

• A resource allocation problem:– computation is not free– communication is not free

• First, a description problem:– express available/required resources– use annotations (“pragmas”) to do this

• Then, the distribution problem:– map Lustre code to TTA tasks and messages– schedule the tasks on processors and

messages on the bus

Page 38: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Distributing Lustre on TTA

• Extend Lustre with annotations.

• Decompose a Lustre program into tasks.

• Schedule the tasks.

Page 39: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Distributing Lustre on TTA

• Extend Lustre with annotations.

• Decompose a Lustre program into tasks.

• Schedule the tasks.

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Annotations: code distribution

• Meaning:– The execution of Lustre node A is done at

TTA processor P1.– The output y is produced at P1.– If the input x is produced elsewhere, it must

be transmitted to P1.

y = A(x); (location = P1)

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Annotations: timing assumptions

• Meaning:– BCET(A)=10 and WCET(A)=20.– A is a Lustre node, execution time is given

for the C code generated from A (assumed to be executed atomically).

– Different execution times for A can be given in case A is run on different processors or call by different nodes (e.g., with different inputs).

exec-time(A) in [10,20]

Note: rely on external tools for ET analysis.

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Annotations: timing requirements

• Meaning:– The delay from availability of x until availability

of y must be at most 10 time units (deadline).– Availability:– input variables are available when they are

read,– internal variables when they are computed,– output variables when they are written.

date(y) - date(x) 10

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Distributing Lustre on TTA

• Extend Lustre with annotations.

• Decompose a Lustre program into tasks.

• Schedule the tasks.

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Decomposing Lustre into tasks

Call graph anddependenciesof a Lustre program:

Node B calls B1 and B2

B2 depends onresults from B1

Page 45: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Decomposing Lustre into tasks

Call graph anddependenciesof a Lustre program:

Should theentire node Bbe one task?

Page 46: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Decomposing Lustre into tasks

Call graph anddependenciesof a Lustre program:

Or should therebe two tasksB1 and B2 ?

Page 47: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Decomposing Lustre into tasks

• Two extremes:– One task per TTA processor: too coarse,

perhaps no feasible schedule (pre-emption not allowed).

– One task for every Lustre operator: too fine, scheduling too costly (too many tasks).

• Approach:– Start with coarse partition.– Split when necessary (no feasible schedule),

based on feedback from the scheduler.– Feedback: heuristics.

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Distributing Lustre on TTA

• Extend Lustre with annotations.

• Decompose a Lustre program into tasks.

• Schedule the tasks.

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Scheduling• Schedule tasks on each processor.• Schedule messages on the bus.

• Static TDMA schedules (both for bus and processors).

• No pre-emption (problem known NP-hard).

• Algorithm:– Branch-and-bound to fix order of tasks/messages.– Solve a linear program on leaves to find start

times.– Ensures deadlines are met 8 possible exec. times.

Page 50: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Scheduling

T1 ! T4, T3 ! T5

T3 ! T4

T4 ! T3

T1 ! T2

LP

Infeasible(necessaryconditions)

total order

Page 51: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Plan of talk

• Translating Simulink to Lustre.

• Distributing Lustre on TTA.

• Tool-chain and case studies.

Page 52: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Tool chain

Sim2Lus

Simulink/Stateflow model (.mdl file)

Lustre program (.lus file)

Lustre program + annotations

: currently manual

Decomposer

Scheduler Integrator

C code generator

C compiler

Tasks + constraints

Global schedule(bus + processors)

Lustre modules+ task mapping

Glue code

C code

OSEK executables

feed

back

: on-going work

Page 53: 1 From Simulink to Lustre to TTA: a layered approach for distributed embedded applications Stavros Tripakis VERIMAG Joint work with: Paul Caspi, Adrian

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Case studies

• Two case studies from Audi.– A warning-filtering system:

• 6 levels, 20 subsystems, 113 total blocks.• 800 lines of generated Lustre code.

– An autonomous steer-by-wire application:• 6 levels, 18 subsystems, 157 total blocks.• 387 lines of generated Lustre code.• Demo-ed in final NEXT TTA review (Jan ‘04).

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Autonomous steer-by-wire

The industrial demonstrator

Equipment:Equipment:• cameras/imagingcameras/imaging• steering actuatorsteering actuator• TTA networkTTA network• MPC555 nodesMPC555 nodes

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The industrial demonstrator

Autonomous steer-by-wire

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Conclusions and on-going work

• End-to-end tool-chain:– from design to implementation– as automatic as possible– preserving semantics– should not have to repeat analysis twice

• On-going:– Stateflow.– Moving on to event-triggered applications on

asynchronous, pre-emptive platforms.– Trying heuristics for splitting nodes

(scheduler feedback).

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Thank you !

Questions ?

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Two papers

• “From Simulink to Lustre to TTA …”:– in “Languages, Compilers and Tools for

Embedded Systems” (LCTES’03).

• “Translating Discrete-time Simulink to Lustre”:– in “Embedded Software” (EMSOFT’03).

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