1 interrupts

Microprocessor and InterfacesMicroprocessorandInterfaces

Interrupts

InterruptsInterrupts Interruptisaprocesswhereanexternaldevicecanget

tt ti f th iattentionofthemicroprocessor TheprocessstartsfromtheI/Odevice Theprocessisasynchronous

ClassificationofInterrupts Maskable Interrupts(CanbedelayedorRejected) NonMaskable Interrupts(CannotbedelayedorRejected)

ClassificationofInterruptsp Vectored(theaddressoftheserviceroutineishardwired) Nonvectored(theaddressoftheserviceroutineneedstobesupplied

externallybythedevice)

InterruptsInterrupts Aninterruptisconsideredtobeanemergencyp g ysignalthatmaybeserviced TheMicroprocessormayrespondtoitassoonaspossiblepossible

WhathappenswhenMPisinterrupted?pp p WhentheMicroprocessorreceivesaninterruptsignal,itcompletesthecurrentlyexecutingprogramandthenjumpstoanInterruptServiceRoutine(ISR)tothen jumps to an Interrupt Service Routine (ISR) torespondtotheincominginterrupt

EachinterruptwillmostprobablyhaveitsownISR

Responding to InterruptsRespondingtoInterrupts Responsetoaninterruptmaybeimmediateordelayeddependingonwhethertheinterruptismaskable ornonmaskable andwhetherinterruptsarebeingmaskedornot

TherearetwowaysofredirectingtheexecutiontotheISR depending on whether the interrupt is vectored orISRdependingonwhethertheinterruptisvectoredornonvectored. Vectored:Theaddressofthesubroutineisalreadyknownto the MicroprocessortotheMicroprocessor

NonVectored:ThedevicewillhavetosupplytheaddressofthesubroutinetotheMicroprocessor

The 8085 InterruptsThe8085Interrupts

Whenadeviceinterrupts,itactuallywantstheMPtop , ygiveaservicewhichisequivalenttoaskingtheMPtocallasubroutine.ThissubroutineiscalledISR(Interrupt Service Routine)(InterruptServiceRoutine)

TheEIinstructionisaonebyteinstructionandisusedtoEnablethemaskable interruptsp

TheDIinstructionisaonebyteinstructionandisusedtoDisablethemaskable interrupts

The8085hasasingleNonMaskable interrupt(TRAP) Thenonmaskable interruptisnotaffectedbythevalueofthe Interrupt Enable flip floptheInterruptEnableflipflop


The 8085 has 5 interrupt inputsThe8085has5interruptinputs TheINTRinput

TheINTRinputistheonlynonvectoredinterruptp y p INTRismaskable usingtheEI/DIinstructionpair

RST5.5,RST6.5,RST7.5areallautomaticallyvectored RST5.5,RST6.5,andRST7.5areallmaskable

TRAPistheonlynonmaskable interruptinthe8085 TRAP is also automatically vectored TRAPisalsoautomaticallyvectored


Interruptname Maskable VectoredINTR Yes NoINTR Yes No

RST5.5 Yes YesRST6.5 Yes YesRST7.5 Yes YesTRAP No Yes

Interrupt Vectors and the Vector TableInterruptVectorsandtheVectorTable

An interrupt vector is a pointer to where theAninterruptvectorisapointertowheretheISRisstoredinmemory

All interrupts (vectored or otherwise) areAllinterrupts(vectoredorotherwise)aremappedontoamemoryareacalledtheInterruptVectorTable(IVT) TheIVTisusuallylocatedinmemorypage00(0000H 00FFH)

ThepurposeoftheIVTistoholdthevectorsthatredirectthemicroprocessortotherightplacewhen an interrupt arriveswhenaninterruptarrives

ExampleExample

Let a device interrupts the Microprocessor usingLet,adeviceinterruptstheMicroprocessorusingtheRST7.5interruptline. RST 7.5 interrupt is vectoredRST7.5interruptisvectored Microprocessorknows,inwhichmemorylocationithastogousingacallinstructiontogettheISRaddress

RST7.5isknowsasCall003ChtoMicroprocessor Microprocessorgoesto003ClocationandwillgetaJMPinstructiontotheactualISRaddress

TheMicroprocessorwillthen,jumptotheISRlocation

The8085NonVectoredInterruptProcess

Theinterruptprocessshouldbeenabledusinge te upt p ocess s ou d be e ab ed us gtheEIinstruction

The8085checksforaninterruptduringthep gexecutionofeveryinstruction

IfINTRishigh,MPcompletescurrentinstruction,disablestheinterruptandsendsINTA(Interruptacknowledge)signaltothedevicethatinterruptedinterrupted

INTAallowstheI/OdevicetosendaRSTinstruction through data businstructionthroughdatabus


UponreceivingtheRSTinstruction,MPsavesthep g ,memorylocationofthenextinstructiononthestackandtheprogramistransferredtocalllocation (ISR Call) specified by the RST instructionlocation(ISRCall)specifiedbytheRSTinstruction

MicroprocessorPerformstheISR ISR must include the EI instruction to enable theISRmustincludethe EI instructiontoenablethefurtherinterruptwithintheprogram

RETinstructionattheendoftheISRallowstheMP i h dd f h kMPtoretrievethereturnaddressfromthestackandtheprogramistransferredbacktowheretheprogramwasinterruptedp g p


The8085recognizes8RESTARTinstructions:RST0 RST7g eachofthesewouldsendtheexecutiontoapredeterminedhard

wiredmemorylocation:

RestartInstruction Equivalentto

RST0 CALL0000H

RST1 CALL 0008HRST1 CALL0008H

RST2 CALL0010H

RST3 CALL0018H

RST4 CALL0020H

RST5 CALL0028H

RST6 CALL0030H

RST7 CALL0038H

Restart SequenceRestartSequence

Therestartsequenceismadeupofthreee esta t seque ce s ade up o t eemachinecycles Inthe1stmachinecycle:

ThemicroprocessorsendstheINTAsignal WhileINTAisactivethemicroprocessorreadsthedatalinesexpectingtoreceive,fromtheinterruptingdevice,thep g p gopcode forthespecificRSTinstruction

Inthe2ndand3rdmachinecycles: the 16 bit address of the next instruction is saved on the the16bitaddressofthenextinstructionissavedonthestack

Thenthemicroprocessorjumpstotheaddressassociatedwith the specified RST instructionwiththespecifiedRSTinstruction

Timing Diagram of Restart SequenceTimingDiagramofRestartSequence

Hardware Generation of RST OpcodeHardwareGenerationofRSTOpcode

How does the external device produce theHowdoestheexternaldeviceproducetheopcode fortheappropriateRSTinstruction? The opcode is simply a collection of bits Theopcode issimplyacollectionofbits So,thedeviceneedstosetthebitsofthedatabusto the appropriate value in response to an INTAtotheappropriatevalueinresponsetoanINTAsignal


The following is anThe following is an example of generating RST 5:

RST 5s opcode is EF p

D7D6D5D4D3D2D1D07 6 5 4 3 2 1 01 1 1 0 1 1 1 1


Duringtheinterruptacknowledgemachinecycle,u g t e te upt ac o edge ac e cyc e,(the1stmachinecycleoftheRSToperation): TheMicroprocessoractivatestheINTAsignal ThissignalwillenabletheTristatebuffers,whichwillplacethevalueEFHonthedatabusTherefore sending the Microprocessor the RST 5 Therefore,sendingtheMicroprocessortheRST5instruction

TheRST5instructionisexactlyequivalenttoCALL0028H

Issues in Implementing INTR InterruptsIssuesinImplementingINTRInterrupts

HowlongmustINTRremainhigh? ThemicroprocessorcheckstheINTRlineoneclockcyclebeforethe

lastTstateofeachinstruction The INTR must remain active long enough to allow for the longestTheINTRmustremainactivelongenoughtoallowforthelongest

instruction Thelongestinstructionforthe8085istheconditionalCALLinstruction

which requires 18 Tstateswhichrequires18T states Therefore,theINTRmustremainactivefor17.5Tstates Iff=3MHZthenT=1/fandso,INTRmustremainactivefor[

(1/3MHZ) * 17 5 5 8 i d ](1/3MHZ)*17.55.8microseconds]


How long can the INTR remain high?HowlongcantheINTRremainhigh? TheINTRlinemustbedeactivatedbeforetheEIisexecuted Otherwise the microprocessor will beexecuted.Otherwise,themicroprocessorwillbeinterruptedagain

Once the microprocessor starts to respond to anOncethemicroprocessorstartstorespondtoanINTRinterrupt,INTAbecomesactive(=0)

Therefore,INTRshouldbeturnedoffassoonas the INTA signal is receivedastheINTAsignalisreceived


CanthemicroprocessorbeinterruptedagainCa t e c op ocesso be te upted agabeforethecompletionoftheISR? Assoonasthe1stinterruptarrives,allmaskableinterruptsaredisabled

TheywillonlybeenabledaftertheexecutionoftheEIinstructioninstruction

Therefore,theansweris:onlyifweallowitto., yIftheEIinstructionisplacedearlyintheISR,other

interruptmayoccurbeforetheISRisdone

Multiple Interrupts & PrioritiesMultipleInterrupts&Priorities

How do we allow multiple devices to interruptHowdoweallowmultipledevicestointerruptusingtheINTRline? The microprocessor can only respond to one ThemicroprocessorcanonlyrespondtoonesignalonINTRatatime

Therefore we must allow the signal from only oneTherefore,wemustallowthesignalfromonlyoneofthedevicestoreachthemicroprocessor

Wemust assign some priority to the differentWemustassignsomeprioritytothedifferentdevicesandallowtheirsignalstoreachthemicroprocessoraccordingtothepriority

The Priority EncoderThePriorityEncoder

The solution is to use a circuit called theThesolutionistouseacircuitcalledthepriorityencoder(74LS148) This circuit has 8 inputs and 3 outputs Thiscircuithas8inputsand3outputs Theinputsareassignedincreasingprioritiesaccording to the increasing index of the inputaccordingtotheincreasingindexoftheinput

Input7hashighestpriorityandinput0hasthelowest The 3 outputs carry the index of the highestThe3outputscarrytheindexofthehighestpriorityactiveinput

RST instructions opcodesRSTinstruction sopcodes

Instruction Opcode

RST0 C7(11000111)

RST1 CF(11001111)( )

RST2 D7(11010111)

RST3 DF(11011111)

( )RST4 E7(11100111)

RST5 EF(11101111)

RST6 F7(11110111)

RST7 FF(11111111)

The Priority EncoderThePriorityEncoder Opcodes forthedifferentRSTinstructionsfollowpasetpattern

BitD5,D4andD3oftheopcodes changeinabinarysequencefromRST7downtoRST0.q

Theotherbitsarealways1. Thisallowsthecodegeneratedbythe74366tobeuseddirectlytochoosetheappropriateRSTinstruction.

Theonedrawbacktothisschemeisthattheonlyt h th i it f th d iwaytochangethepriorityofthedevices

connectedtothe74366(Tristatedbuffer)istoreconnectthehardware

The Priority EncoderThePriorityEncoder

Priority Encoder TruthTablePriorityEncoderTruth Table

I7 I6 I5 I4 I3 I2 I1 I0 A2 A1 A0

1 X X X X X X X 1 1 1

0 1 X X X X X X 1 1 0

0 0 1 X X X X X 1 0 1

0 0 0 1 X X X X 1 0 0

0 0 0 0 1 X X X 0 1 1

0 0 0 0 0 1 X X 0 1 0

0 0 0 0 0 0 1 X 0 0 10 0 0 0 0 0 1 X 0 0 1

0 0 0 0 0 0 0 X 0 0 0

The8085Maskable/VectoredInterrupts

The8085has3Maskable/Vectoredinterruptinputs/ p p RST5.5,RST6.5,RST7.5

Theyareallmaskable They are automatically vectored according to the following table: Theyareautomaticallyvectoredaccordingtothefollowingtable:

Interrupt Vector

RST5.5 002CH

RST6.5 0034H

RST7.5 003CH

ThevectorsfortheseinterruptfallinbetweenthevectorsfortheRSTinstructions.ThatswhytheyhavenameslikeRST5.5(RST5andahalf)

Masking RST 5.5, RST 6.5 and RST 7.5MaskingRST5.5,RST6.5andRST7.5

These three interrupts are masked at twoThesethreeinterruptsaremaskedattwolevels: Through the Interrupt Enable flip flop and the ThroughtheInterruptEnableflipflopandtheEI/DIinstructions

The Interrupt Enable flip flop controls the wholeTheInterruptEnableflipflopcontrolsthewholemaskable interruptprocess

Throughindividualmaskflipflopsthatcontroltheavailabilityoftheindividualinterrupts

Theseflipflopscontroltheinterruptsindividually

Maskable Interruptsandvectorllocations

The8085Maskable/VectoredInterruptProcess

Theinterruptprocessshouldbeenabledusingp p gtheEIinstruction

The8085checksforaninterruptduringtheexecution of every instructionexecutionofeveryinstruction

Ifthereisaninterrupt,andiftheinterruptisenabled using the interrupt mask, theenabledusingtheinterruptmask,themicroprocessorwillcompletetheexecutinginstruction,andresettheinterruptflipflopTh i h ll Themicroprocessorthenexecutesacallinstructionthatsendstheexecutiontotheappropriatelocationintheinterruptvectortablepp p p

The8085Maskable/VectoredInterruptProcess

Whenthemicroprocessorexecutesthecalle t e c op ocesso e ecutes t e cainstruction,itsavestheaddressofthenextinstructiononthestack

Themicroprocessorjumpstothespecificserviceroutine

TheserviceroutinemustincludetheinstructionEItoreenabletheinterruptprocessAt th d f th i ti th RET Attheendoftheserviceroutine,theRETinstructionreturnstheexecutiontowheretheprogram was interruptedprogramwasinterrupted

Manipulating the MasksManipulatingtheMasks

The Interrupt Enable flip flop is manipulatedTheInterruptEnableflipflopismanipulatedusingtheEI/DIinstructions

The individual masks for RST 5 5 RST 6 5 and TheindividualmasksforRST5.5,RST6.5andRST7.5aremanipulatedusingtheSIMinstructioninstruction ThisinstructiontakesthebitpatternintheAccumulator and applies it to the interrupt maskAccumulatorandappliesittotheinterruptmaskenablinganddisablingthespecificinterrupts

How SIM Interprets the AccumulatorHowSIMInterpretstheAccumulator

SIM and the Interrupt MaskSIMandtheInterruptMask Bit0isthemaskforRST5.5,bit1isthemaskforRST6.5

andbit2isthemaskforRST7.5 Ifthemaskbitis0,theinterruptisavailable Ifthemaskbitis1,theinterruptismasked

Bit3(MaskSetEnable MSE)isanenableforsettingthemask Ifitissetto0themaskisignoredandtheoldsettingsremaing g Ifitissetto1,thenewsettingareapplied TheSIMinstructionisusedformultiplepurposesandnotonly

forsettinginterruptmasks ItisalsousedtocontrolfunctionalitysuchasSerialDataTransmission Therefore,bit3isnecessarytotellthemicroprocessorwhetherornottheinterruptmasksshouldbemodified

SIM and the Interrupt MaskSIMandtheInterruptMask TheRST7.5interruptistheonly8085interruptthathasmemory

IfasignalonRST7.5arriveswhileitismasked,aflipflopwillrememberthesignal

When RST7.5 is unmasked, the microprocessor will be interruptedWhenRST7.5isunmasked,themicroprocessorwillbeinterruptedevenifthedevicehasremovedtheinterruptsignal

Thisflipflopwillbeautomaticallyresetwhenthemicroprocessorresponds to an RST 7.5 interruptrespondstoanRST7.5interrupt

Bit4oftheaccumulatorintheSIMinstructionallowsexplicitlyresettingtheRST7.5memoryevenifthemicroprocessordidnotrespond to itrespondtoit

Bit5isnotusedbytheSIMinstruction

UsingtheSIMInstructiontoModifyh ktheInterruptMasks

Example: Set the interrupt masks so thatExample:SettheinterruptmaskssothatRST5.5isenabled,RST6.5ismasked,andRST7 5 is enabledRST7.5isenabled First,determinethecontentsoftheaccumulator

Triggering LevelsTriggeringLevels

RST 7.5 is positive edge sensitiveRST7.5ispositiveedgesensitive WhenapositiveedgeappearsontheRST7.5line,alogic1isstoredintheflipflopasapendinginterrupt

h l h b d h fl fl h l Sincethevaluehasbeenstoredintheflipflop,thelinedoesnothavetobehighwhenthemicroprocessorchecksfortheinterrupttoberecognized

Thelinemustgotozeroandbacktoonebeforeanewinterruptisrecognized

RST 6 5 and RST 5 5 are level sensitive RST6.5andRST5.5arelevelsensitive Theinterruptingsignalmustremainpresentuntilthemicroprocessorchecksforinterrupts

Determining the Current Mask SettingsDeterminingtheCurrentMaskSettings

RIM instruction: Read Interrupt MaskRIMinstruction:ReadInterruptMask Loadtheaccumulatorwithan8bitpatternshowing the status of each interrupt pin and maskshowingthestatusofeachinterruptpinandmask

HowRIMsetstheAccumulatorsd ff bdifferentbits

The RIM Instruction and the MasksTheRIMInstructionandtheMasks

Bits02showthecurrentsettingofthemaskforts 0 s o t e cu e t sett g o t e as oeachofRST7.5,RST6.5andRST5.5

Theyreturnthecontentsofthethreemaskflipflops Theycanbeusedbyaprogramtoreadthemasksettingsinordertomodifyonlytherightmask

Bit3showswhetherthemaskable interruptprocessisenabledornot

ItreturnsthecontentsoftheInterruptEnableFlipFlop Itcanbeusedbyaprogramtodeterminewhetherornotinterrupts are enabledinterruptsareenabled

The RIM Instruction and the MasksTheRIMInstructionandtheMasks

Bits 46 show whether or not there are pendingBits4 6showwhetherornottherearependinginterruptsonRST7.5,RST6.5,andRST5.5

Bits4and5returnthecurrentvalueoftheRST5.5andRST6.5pins

Bit6returnsthecurrentvalueoftheRST7.5memoryflipflopflop

Bit 7 is used for Serial Data InputBit7isusedforSerialDataInput TheRIMinstructionreadsthevalueoftheSIDpinonthemicroprocessorandreturnsitinthisbit

Pending InterruptsPendingInterrupts

Since the 8085 has five interrupt linesSincethe8085hasfiveinterruptlines,interruptsmayoccurduringanISRandremainpendingpending UsingtheRIMinstruction,itispossibletoreadthestatus of the interrupt lines and find if there arestatusoftheinterruptlinesandfindifthereareanypendinginterrupts

TRAPTRAP

TRAPistheonlynonmaskable interrupts t e o y o as ab e te upt Itdoesnotneedtobeenabledbecauseitcannotbedisabled

Ithasthehighestpriorityamongstinterrupts Itisedgeandlevelsensitive

Itneedstobehighandstayhightoberecognized Onceitisrecognized,itwontberecognizedagainuntil it goes low then high againuntilitgoeslow,thenhighagain

TRAPisusuallyusedforpowerfailureandemergency shutoffemergencyshutoff


InterruptName Maskable

MaskingMethod Vectored Memory

TriggeringMethod

INTR Yes DI / EI No No LevelS i iINTR Yes DI/EI No No Sensitive

RST5.5/RST6.5 Yes

DI/EISIM

Yes No LevelSensitive

RST7.5 YesDI/EISIM

Yes Yes EdgeSensitive

TRAP No None Yes No Level&EdgeTRAP No None Yes No Sensitive

1 interrupts

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