1

Introduction• Chapters 2 & 3: Introduced increasingly complex digital building

blocks– Gates, multiplexors, decoders, basic registers, and controllers

• Controllers good for systems with control inputs/outputs– Control input: Single bit (or just a few), representing environment event or

state• e.g., 1 bit representing button pressed

– Data input: Multiple bits collectively representing single entity• e.g., 7 bits representing temperature in binary

• Need building blocks for data– Datapath components, aka register-transfer-level (RTL) components,

store/transform data• Put datapath components together to form a datapath

• This chapter introduces numerous datapath components, and simple datapaths– Next chapter will combine controllers and datapaths into “processors”

2

Registers• Can store data, very common in datapaths• Basic register of Ch 3: Loaded every cycle

– Useful for implementing FSM -- stores encoded state

– For other uses, may want to load only on certain cycles

Combinationallogic

State register

s1 s0

n1

n0

xb

clk

I3 I2 I1 I0

Q3Q2Q1Q0

reg(4)

Basic register loads on every clock cycle

load

How extend to only load on certain cycles?

a

DQ

DQ

DQ

DQ

I2I3

Q2Q3 Q1 Q0

I1 I0

clk

4-bit register

3

Register with Parallel Load• Add 2x1 mux to front of each flip-flop• Register’s load input selects mux input to pass

– Either existing flip-flop value, or new value to load

1 0

D

Q

Q3

I3

1 0

D

Q

Q2

I2

1 0

Q

Q1

I1

1 0

D

Q

Q0

I0

load

= 0

1 02×1

D

Q

Q3

I3

loadload

1 0

D

Q

Q2

I2

1 0

D

Q

Q1

I1

1 0

D

Q

Q3

I3

1 0

D

Q

Q2

I2

1 0

D

Q

Q1

I1

1 0

D

Q

Q0

I0

load

= 1

(b)

(c)(a)

1 0

D

Q

Q0

I0

I3 I2 I1 I0

Q3 Q2 Q1 Q0

D

4

Register Example using the Load Input: Weight Sampler

• Scale has two displays– Present weight

– Saved weight

– Useful to compare present item with previous item

• Use register to store weight– Pressing button causes

present weight to be stored in register

• Register contents always displayed as “Saved weight,” even when new present weight appears

Scale

Saved weight

Weight Sampler

Present weight clk

bSave

I3 I2 I1 I0

Q3 Q2Q1 Q0

load3 pounds

0 0 1 1

0 0 1 1

3 pounds

0 0 1 0

2 pounds 1 a

5

Shift Register• Shift right

– Move each bit one position right– Shift in 0 to leftmost bit

1 1 0 1 Register contentsbefore shift right

0 1 1 0

0

Register contentsafter shift right

a

Q: Do four right shifts on 1001, showing value after each shifta

A: 1001 (original)

0100

0010

0001

0000 shr_in

• Implementation: Connect flip-flop output to next flip-flop’s input

a

6

Shift Register• To allow register to either shift or retain, use 2x1 muxes

– shr: 0 means retain, 1 shift– shr_in: value to shift in

• May be 0, or 1

• Note: Can easily design shift register that shifts left instead

1 02×1

D

Q

Q3

1 0

D

Q

Q2

1 0

D

Q

Q1

1 0

D

Q

Q0

shr=

11 02×1

D

Q

Q3

shr

shr_in

shrshr_in

1 0

D

Q

Q2

1 0

D

Q

Q1 (b)

(c)

(a)

1 0

D

Q

Q0

Q3 Q2 Q1 Q0

7

Multifunction Registers• Many registers have multiple functions

– Load, shift, clear (load all 0s)– And retain present value, of course

• Easily designed using muxes– Just connect each mux input to achieve

desired function

s1

shr_in

s0

3 2 1

I3

0

D

Q

Q3

Q2 Q1 Q0Q3

I2 I1 I0I3

Q2

03 2 1

I2

0

D

Q

0

Q1

3 2 1

I1

0

D

Q

0

Q0

3 2 1

I0

0

D

Q

0

4×1 shr_ins1s0

(a)

(b)

Functions:Operation

Maintain present valueParallel loadShift right(unused - let's load 0s)

s00101

s10011

8

Multifunction Registers

shr_inshl_in

3 2 1

I3

0

D

Q

Q3

Q2 Q1 Q0Q3

I2 I1 I0I3

Q2

3 2 1

I2

0

D

Q

Q1

3 2 1

I1

0

D

Q

Q0

3 2 1

I0

0

D

Q

shl_inshr_ins1s0

(a) (b)

OperationMaintain present valueParallel loadShift rightShift left

s00101

s10011

9

Maintain valueShift leftShift rightShift rightParallel loadParallel loadParallel loadParallel load

NoteOperations0s1

01110000

01001111

OutputsInputs

01010101

00110011

00001111

ld shr shl

Truth table for combinational circuit

Multifunction Registers with Separate Control Inputs

Maintain present valueShift leftShift right

Shift right – shr has priority over shlParallel load

Parallel load – ld has priorityParallel load – ld has priorityParallel load – ld has priority

Operationshlshrld

00001111

00110011

01010101

Q2 Q1 Q0Q3

Q2 Q1 Q0Q3

I2 I1 I0I3

I2 I1 I0I3

s1shr_in

shr_in

shr

shl

ld

s0shl_in

shl_in

a

a

?combi-nationalcircuit

a

s1 = ld’*shr’*shl + ld’*shr*shl’ + ld’*shr*shl

s0 = ld’*shr’*shl + ld

10

Register Operation Table• Register operations typically shown using compact version of table

– X means same operation whether value is 0 or 1• One X expands to two rows• Two Xs expand to four rows

– Put highest priority control input on left to make reduced table simple

Maintain valueShift left

NoteOperations0s1

01

01

OutputsInputs

01

00

00

Shift rightShift right

11

00

01

11

00

Parallel loadParallel loadParallel loadParallel load

0000

1111

0101

0011

1111

ld shr shl

MaintainvalueShift left

Operationld shr shl

01

00

00

Parallel loadXX1Shift rightX10

11

Register Design Process• Can design register with desired operations using simple

four-step process

12

Register Design Example• Desired register operations

– Load, shift left, synchronous clear, synchronous set

Step 1: Determine mux size

5 operations: above, plus maintain present value (don’t forget this one!) --> Use 8x1 mux

Step 2: Create mux operation table

Step 3: Connect mux inputs

Step 4: Map control lines

OperationMaintain present valueParallel loadShift leftSynchronous clearSynchronous setMaintain present valueMaintain present valueMaintain present value

s001010101

s100110011

s200001111

D

Q

Qn

7 6 3 2 1

In

05 4

1 0

s2s1s0

fromQn-1

OperationMaintain present valueShift leftParallel loadSet to all 1sClear to all 0s

s000101

s101001

s200010

shl01XXX

ld001XX

clr00001

Inputs Outputsset0001X

a

a

s2 = clr’*sets1 = clr’*set’*ld’*shl + clrs0 = clr’*set’*ld + clr

13

Register Design Example

Step 4: Map control linesOperation

Maintain present valueShift leftParallel loadSet to all 1sClear to all 0s

s000101

s101001

s200010

shl01XXX

ld001XX

clr00001

Inputs Outputsset0001X

s2 = clr’*sets1 = clr’*set’*ld’*shl + clrs0 = clr’*set’*ld + clr

Q2 Q1 Q0Q3

Q2 Q1 Q0Q3

I2 I1 I0I3

I2 I1 I0I3

s1ld

shl

s0shl_in

shl_incombi-nationalcircuitset

clr

s2

14

Adders• Adds two N-bit binary numbers

– 2-bit adder: adds two 2-bit numbers, outputs 3-bit result

– e.g., 01 + 11 = 100 (1 + 3 = 4)

• Can design using combinational design process of Ch 2, but doesn’t work well for reasonable-size N– Why not?

01011010

11001001

00110111

01010101

00110011

11111111

00001111

s001011010

s100110110

c00000001

b001010101

b100110011

a100000000

Inputs Outputsa000001111

15

Why Adders Aren’t Built Using Standard Combinational Design Process

• Truth table too big– 2-bit adder’s truth table shown

• Has 2(2+2) = 16 rows

– 8-bit adder: 2(8+8) = 65,536 rows– 16-bit adder: 2(16+16) = ~4 billion rows– 32-bit adder: ...

• Big truth table with numerous 1s/0s yields big logic– Plot shows number of transistors for N-bit adders, using

state-of-the-art automated combinational design tool

01011010

11001001

00110111

01010101

00110011

11111111

00001111

s001011010

s100110110

c00000001

b001010101

b100110011

a100000000

Inputs Outputsa000001111

Q: Predict number of transistors for 16-bit adderA: 1000 transistors for N=5, doubles for each

increase of N. So transistors = 1000*2(N-5). Thus, for N=16, transistors = 1000*2(16-5) = 1000*2048 = 2,048,000. Way too many!

a

10000

8000

6000

4000

2000

01 2 3 4 5

N6 7 8

Tra

nsis

tors

16

Alternative Method to Design an Adder: Imitate Adding by Hand

• Alternative adder design: mimic how people do addition by hand

• One column at a time– Compute sum,

add carry to next column

1 1 1 1

10

+ 0 1 1 0

01

1 1 1 1

101

+ 0 1 1 0

11

1 1 1 1

101

+ 0 1 1 0

1

01

1 1 1 1

+ 0 1 1 0

0

1

A:B:

a

17

Alternative Method to Design an Adder: Imitate Adding by Hand

• Create component for each column– Adds that

column’s bits, generates sum and carry bits

0

1 1 1 1

+ 0 1 1 0

1

10101

b

co s

0

a ci

A:

B:+ 0

1 1 1 1

1

b

co s

1

a ci

1

b

co s

0

a ci

1

1 1 0

b

co s

1 SUM

a

0

A:B:

1

Half-adderFull-adders

a

18

Half-Adder• Half-adder: Adds 2 bits, generates sum and carry• Design using combinational design process from Ch

2

bco s

0

a ci

A:

B:+ 0

1 1 1 1

1

1

bco s

1

a ci

1

1

bco s

0

a ci

1

0

bco s

1 SUM

a

0

s0110

co0001

b0101

a0011

Inputs Outputs

Step 1: Capture the function

Step 2: Convert to equations

Step 3: Create the circuit

co = ab s = a’b + ab’ (same as s = a xor b) a b

co

co s

a b

s

Half-adder

19

Full-Adder• Full-adder: Adds 3 bits, generates sum and carry• Design using combinational design process from Ch

2

bco s

0

a ci

A:

B:+ 0

1 1 1 1

1

1

bco s

1

a ci

1

1

bco s

0

a ci

1

0

bco s

1 SUM

a

0

Step 1: Capture the function

s01101001

co00010111

ci01010101

b00110011

a00001111

Inputs OutputsStep 2: Convert to equationsco = a’bc + ab’c + abc’ + abc

co = a’bc +abc +ab’c +abc +abc’ +abcco = (a’+a)bc + (b’+b)ac + (c’+c)abco = bc + ac + ab

s = a’b’c + a’bc’ + ab’c’ + abcs = a’(b’c + bc’) + a(b’c’ + bc)s = a’(b xor c)’ + a(b xor c)s = a xor b xor c

Step 3: Create the circuit

co

ciba

s

Full adder

20

Carry-Ripple Adder• Using half-adder and full-adders, we can build adder that adds like we would by hand• Called a carry-ripple adder

– 4-bit adder shown: Adds two 4-bit numbers, generates 5-bit output• 5-bit output can be considered 4-bit “sum” plus 1-bit “carry out”

– Can easily build any size adder

a3

co s

FA

co

b3 a2b2

s3 s2 s1

ciba

co s

FA

ciba

a1b1

co s

FA

ciba

s0

a0b0

co s

HA

ba

(a)

a3a2a1a0 b3

s3s2s1s0co

b2b1b0

(b)

4-bit adder

21

Carry-Ripple Adder• Using full-adder instead of half-adder for first bit, we can

include a “carry in” bit in the addition– Will be useful later when we connect smaller adders to form bigger

adders

a3

co s

FA

co

b3 a2b2

s3 s2 s1

ciba

co s

FA

ciba

a1b1

co s

FA

ciba

s0

a0b0 ci

co s

FA

ciba

(a)

a3a2a1a0 b3

s3s2s1s0co

ci

b2b1b0

(b)

4-bit adder

22

Carry-Ripple Adder’s Behavior

0 1 1 10 0 0 1 0111+0001(answer should be 01000)

0

co s

FA

0 0

0 0 0

0 0 00 0 0

0 0

ciba

co s

FA

ciba

0 0

co s

FA

ciba

0

0 0

co s

FA

ciba

0

Assume all inputs initially 0

Output after 2 ns (1FA delay)0 0 1 1 0

co s

FA

0 0

0 0 0

co2 co1 co0

ciba

co s

FA

ciba

co s

FA

ciba

co s

FA

ciba

0

01

Wrong answer -- something wrong? No -- just need more time for carry to ripple through the chain of full adders.

a

23

0 00

co s

FA

1 1 1

1 10 1 0

ciba

co s

FA

ciba

1 0

co s

FA

ciba

0 0 0

1 1

co s

FA

ciba

(d)Output after 8ns (4 FA delays)

Carry-Ripple Adder’s Behavior0

co s

FA

0 0 1

co1

0 1 0

ciba

co s

FAciba

1 0

co s

FAciba

0 0 1 0 0

1 1

co s

FAciba

(b)

10 1

0 0 0

0

1

0 1

1

Outputs after 4ns (2 FA delays)

00

co s

FA

1 1

0 1

co2

0 1 0

ciba

co s

FA

ciba

1 0

co s

FA

ciba

0 0

1 10

co s

FA

ciba

(c)Outputs after 6ns (3 FA delays)

a

0111+0001(answer should be 01000)

1

Correct answer appears after 4 FA delays

24

Cascading Adders

a3a2a1a0 b3

s3s2s1s0co

s7s6s5s4co

ci

b2b1b0

a7a6a5a4 b7b6b5b4

(a) (b)

4-bit adder

a3a2a1a0 b3

s3s2s1s0

s3s2s1s0

co

ci

b2b1b0

a3a2a1a0 b3b2b1b0

4-bit adder

a7.. a0 b7.. b0

s7.. s0co

ci8-bit adder

25

Shifters• Shifting (e.g., left shifting 0011 yields 0110) useful for:

– Manipulating bits– Converting serial data to parallel– Shift left once is same as multiplying by 2 (0011 (3) becomes 0110 (6))

• Why? Essentially appending a 0 -- Note that multiplying decimal number by 10 accomplished just be appending 0, i.e., by shifting left (55 becomes 550)

– Shift right once same as dividing by 2

i2

q3 q2 q1 q0

in

i3 i1 i0

Left shifter

0 1 0 1 0 1 0 1

in

sh

i3

q3 q2 q1 q0

i2 i1 i0

Shifter with left shift or no shift

inL

i3

q3 q2 q1 q0

i2 i1 i0

inR

2 0s0s1

shLshR

1 2 01 2 01 2 01

Shifter with left shift, right shift, and no shift

<<1

Symbol

a

26

Shifter Example: Approximate Celsius to Fahrenheit Converter

• Convert 8-bit Celsius input to 8-bit Fahrenheit output– F = C * 9/5 + 32– Approximate: F = C*2 + 32 – Use left shift: F = left_shift(C) + 32

C800001100 (12)

00011000 (24)

00111000 (56)

<<1 0 (shift in 0)

8F

8-bit adder

8 800100000 (32)

* 2

a

27

Comparators• N-bit equality comparator: Outputs 1 if two N-bit numbers are equal

– 4-bit equality comparator with inputs A and B• a3 must equal b3, a2 = b2, a1 = b1, a0 = b0

– Two bits are equal if both 1, or both 0

– eq = (a3b3 + a3’b3’) * (a2b2 + a2’b2’) * (a1b1 + a1’b1’) * (a0b0 + a0’b0’)

• Recall that XNOR outputs 1 if its two input bits are the same– eq = (a3 xnor b3) * (a2 xnor b2) * (a1 xnor b1) * (a0 xnor b0)

a3b3 a2b2 a1b1 a0b0

eq(a)

(b)

a3a2a1a0 b3

eq

b2b1b0

4-bit equality comparator

a

0110 = 0111 ? 0 1 1 00 1 1 1

01 1 1

0

28

Magnitude Comparator• N-bit magnitude comparator:

Indicates whether A>B, A=B, or A<B, for its two N-bit inputs A and B– How design? Consider how compare

by hand. First compare a3 and b3. If equal, compare a2 and b2. And so on. Stop if comparison not equal -- whichever’s bit is 1 is greater. If never see unequal bit pair, A=B.

A=1011 B=1001

1011 1001

a

Equal

1011 1001 Equal

1011 1001 Unequal

So A > B

29

Magnitude Comparator• By-hand example leads to idea for design

– Start at left, compare each bit pair, pass results to the right

– Each bit pair called a stage

– Each stage has 3 inputs indicating results of higher stage, passes results to lower stage

IgtIeqIlt

a3a2a1a0 b3b2b1b0 AgtBAeqBAltB

in_gtin_eqin_lt

out_gtout_eqout_lt

IgtIeqIlt

Stage 3

a3 b3

a b

in_gtin_eqin_lt

out_gtout_eqout_lt

Stage 2

a2 b2

a b

in_gtin_eqin_lt

out_gtout_eqout_lt

Stage 1

a1 b1

a b

in_gtin_eqin_lt

out_gtout_eqout_lt

AgtBAeqBAltB

Stage 0

a0 b0

a b

(a)

(b)

0

01 4-bit magnitude comparator

30

Magnitude Comparator

• Each stage:– out_gt = in_gt + (in_eq * a * b’)

• A>B (so far) if already determined in higher stage, or if higher stages equal but in this stage a=1 and b=0

– out_lt = in_lt + (in_eq * a’ * b)• A<B (so far) if already determined in higher stage, or if higher stages equal but in

this stage a=0 and b=1

– out_eq = in_eq * (a XNOR b)• A=B (so far) if already determined in higher stage and in this stage a=b too

– Simple circuit inside each stage, just a few gates (not shown)

in_gtin_eqin_lt

out_gtout_eqout_lt

IgtIeqIlt

Stage 3

a3 b3

a b

in_gtin_eqin_lt

out_gtout_eqout_lt

Stage 2

a2 b2

a b

in_gtin_eqin_lt

out_gtout_eqout_lt

Stage 1

a1 b1

a b

in_gtin_eqin_lt

out_gtout_eqout_lt

AgtBAeqBAltB

Stage 0

a0 b0

a b

31

Magnitude Comparator

• How does it work?

in_gtin_eq

in_lt

out_gtout_eq

out_lt

IgtIeq

Ilt

Stage3

a3 b3

a b

in_gtin_eq

in_lt

out_gtout_eq

out_lt

Stage2

a2 b2

a b

in_gtin_eq

in_lt

out_gtout_eq

out_lt

Stage1

a1 b1

a b

in_gtin_eq

in_lt

out_gtout_eq

out_lt

AgtBAeqB

AltB

Stage0

a0 b01 1 0 0 1 0 1 1

a b

(a)

=

0

1

0

in_gt

in_eqin_lt

out_gt

out_eqout_lt

Igt

Ieq

Ilt

Stage3

a3 b3

a b

in_gt

in_eqin_lt

out_gt

out_eqout_lt

Stage2

a2 b2

a b

in_gt

in_eqin_lt

out_gt

out_eqout_lt

Stage1

a1 b1

a b

in_gt

in_eqin_lt

out_gt

out_eqout_lt

AgtB

AeqBAltB

Stage0

a0 b01 1 0 0 1 0 1 1

a b

(b)

0

1

0

=

0

1

0

1011 = 1001 ?

0

1

0Ieq=1 causes this stage to compare

a

32

Magnitude Comparator

• Final answer appears on the right

• Takes time for answer to “ripple” from left to right

• Thus called “carry-ripple style” after the carry-ripple adder– Even though

there’s no “carry” involved

1011 = 1001 ?

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

Igt

Ieq

Ilt

Stage3

a3 b3

a b

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

Stage2

a2 b2

a b

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

Stage1

a1 b1

a b

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

AgtB

AeqB

AltB

Stage0

a0 b0

1 1 0 0 1 0 1 1

a b

(c)

0

1

0

1

0

0

>

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

Igt

Ieq

Ilt

Stage3

a3 b3

a b

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

Stage2

a2 b2

a b

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

Stage1

a1 b1

a b

in_gt

in_eq

in_lt

out_gt

out_eq

out_lt

AgtB

AeqB

AltB

Stage0

a0 b0

1 1 0 0 1 0 1 1

a b

(d)

0

1

0

0

1

0

a

33

Magnitude Comparator Example: Minimum of Two Numbers

• Design a combinational component that computes the minimum of two 8-bit numbers– Solution: Use 8-bit magnitude comparator and 8-bit 2x1 mux

• If A<B, pass A through mux. Else, pass B.

MIN

IgtIeqIlt

AgtBAeqBAltB

010

A

A B

B

8-bit magnitude comparators I1 I0

2x1 mux8-bit

C

8

88 8 8

8

8

8

C

A BMin

(a)

(b)

11000000 01111111

0

01

01111111

a