1

第四章

I/O Organization

2

Agenda

Single bus architecture I/O Bus

Address linesData linesControl lines

I/O addressing Memory-mapped I/O Isolated I/O

3

處理器 記憶體

I/O 裝置 1 I/O 裝置 n

匯流排

圖 4.1 一個單一匯流排結構

4

System resources

Every I/O device will use some system resources IRQ

Hardware interrupt DMA Channels

For direct memory access I/O ports (I/O addresses)

Low memory area For communication between devices and cpu

I/O memory Upper memory area(384K) For device driver mapped from BIOS For temporary data storage

5

I/O BUS

Address linesAddress the I/O devices

Data linesData put from device or cpu

Control linesRead/writeWhen data is ready

6

I/O addressing

Memory-mapped I/O I/O device share the same address space with

memory Isolated I/O

Special Instruction I/O the 8086 used IN and OUT to read and write to I/O

devicesA output pin of CPU differentiate the address to

memory or devices

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I/O 介面

匯流排位址線資料線控制線

圖 4.2 輸入設備的 I/O 介面

位址解碼器 資料與狀態暫存器

控制電路

輸入設備

8

KEN

SOUT

控制

資料傳入

圖 4.3 鍵盤和顯示介面中的暫存器

DEN

資料傳出

7

KIRQ SIN狀態

6 5 4 3 2 1 0

DIRQ

9

Input Output Techniques

Program-controlled I/O Interrupt driven I/O DMA (Direct Memory Access)

10

圖 4.4 程式會從鍵盤讀取一行資料，將它存到記憶體緩衝區中，並且回應到顯示裝置上

  Move #LINE,R0 初始化記憶體指標器。WAITK TestBit #0,STATUS 測試 SIN 旗標。  Branch=0 WAITK 等待字元被輸入。

  Move DATAIN,R1 讀取字元。WAITD TestBit #1,STATUS 測試 SOUT 旗標。  Branch=0 WAITD 等待顯示裝置就緒。

  Move R1,DATAOUT 送出字元到顯示裝置。  Move R1,(R0)+ 儲存字元並且前進指標器位置。  Compare #$0D,R1 檢查是否為 Carriage Return。

  Branch0 WAITK 如果不是，讀取另一個字元。

  Move #$0A,DATAOUT 否則，送出換行 Line Feed。

  Call Process 呼叫一個子常式來處理輸入的一行資料。

Program-controlled I/O

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Interrupt driven I/O

Refer to Page 4-22 圖 4.9

12

圖 4.5 中斷發生時控制權的轉換

中斷發生於此

M

i

2

1

PRINT 常式

程式 2程式 1

COMPUTE 常式

i 1+

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Avoid infinite interrupt

Mask interrupt Ignore interrupt until entering first instruction

of interrupt service routineThen disable interrupt in the first instruction of

interrupt service routineEnable interrupt in the last instruction of

interrupt service routine

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Multiple devices interrupt

Prioritize the devicesEq irq0 > irq 1> irq 2 ..

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Interrupt Vectors

16

優先等級仲裁電路

設備 1 設備 2 設備 p

處理

器

INTA1

INTR 1 I NTRp

INTAp

圖 4.7 使用個別的中斷請求和確認線路的中斷優先等級實作

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圖 4.8 中斷優先等級方案

(b) 優先等級群組的佈置

設備 設備

優先等級仲裁電路

處理

器

設備 設備

(a) 菊花鏈

處理

器

設備 2

I N T R

INTA

I N T R 1

I N T R p

INTA1

INTA p

設備 n 設備 1

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Software interrupt

System call from applications A interrupted by scheduler (via clock) Context switching Scheduler selects B Before A’s time slice due, A requests I/O

(eg. Keyboard input), A will issue system call to OS and OS will finally call I/O routine

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(a) OS 初始化、服務和排程程式

(b) I/O 常式

(c) 鍵盤驅動程式圖 4.10 一些作業系統常式。

OSINIT 設定中斷向量：  Time-slice clock SCHEDULER

  Software interrupt OSSERVICES

  Keyboard interrupt IOData

  …

OSSERVICES 檢查堆疊來決定被要求的操作。  呼叫適當的常式。SCHEDULER 儲存程式狀態。  選擇一個可以執行的處理程序。  還原新處理程序被儲存的 context。  推進 PS 和 PC 的新值到堆疊中。  從中斷返回。

IOINIT 設定處理程序的狀態為 Blocked。  初始化記憶體緩衝區位址指標和計數器。  呼叫設備驅動程式來初始化設備  並且許可在設備介面中的中斷。  從子常式返回。   IODATA 探詢設備來決定中斷的來源  呼叫適當的驅動程式。  如果 END=1 ，那麼設定處理程序狀態為可執行的。  從中斷返回。

KBDINIT 許可中斷。  從子常式返回。   KBDDATA 檢查設備狀態。  如果是就緒的，那麼傳送字元。  如果字元 =CR ，那麼 { 設定 END=1 ；禁止中斷 }  否則設定 END=0。  從子常式返回。

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Direct Memory Access (DMA)

CPU doesn’t involve data transferring except and the beginning and the end

DMAC(DMA Controller) in charge of data transferring CPU tells DMAC

The starting address of word to be transferred Work counts Direction (read or write)

When DMA is transferring data, the request AP is blocked by OS, at the same time CPU can execute other programs

When DMAC done work, it will interrupt CPU and OS will resume the blocked AP then the scheduler can schedule it

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完成

IE

IRQ

狀態與控制

起始位址

字組計數

WR/

31 30 1 0

圖 4.18 在一個 DMA 介面中的暫存器

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處理器

鍵盤

系統匯流排

主記憶體

網路介面

磁碟 /DMA控制器 印表機DMA

控制器

磁碟磁碟

圖 4.19 在一個計算機系統中 DMA控制器的使用

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24

CPU involved

25

26

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DMA mode

Burst Mode DMA– Here the DMA machine simply takes over control of the Bus makes the data transfer at top speed hands control back to the CPU. This is fast, but the CPU is stopped dead for the duration of the transfer.

SUMMARY: Take control of BUS. Stop the CPU Send all the data to Memory Restore BUS control to CPU

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DMA mode

Cycle Stealing In the course of a normal program the CPU spends a lot of time executing int

ernal CPU instructions (e.g. add ax,bx, inc bx, jnz fred) During the execute phase of these instructions the CPU does not need contro

l of the Bus or access to memory. In cycle stealing mode the DMA machine has the ability to “steal” bus cycles for its own data transfer, stopping the CPU. But it can also use those bus cycles that the CPU doesn’t need.

This cycle stealing approach slows down both the CPU and the DMA, but is more efficient overall.

Not an interrupt, CPU does not switch context CPU suspended just before it accesses bus

i.e. before an operand or data fetch or a data write SUMMARY: Take every second cycle off the CPU to use the BUS Also take any cycle where the CPU is not using the BUS (also known as

Hidden DMA)

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DMA Bus Line? Typical Default Use Other Common Uses

0 no Memory Refresh None

1 8/16-bit Sound card (low DMA)SCSI host adapters, ECP parallel ports, tape accelerator cards, network cards, voice

modems

2 8/16-bit Floppy disk controller Tape accelerator cards

3 8/16-bit NoneECP parallel ports, SCSI host adapters, tape accelerator cards, sound card (low

DMA), network cards, voice modems, hard disk controller on old PC/XT

4 noNone; cascade for DMAs

0-3None

5 16-bit only Sound card (high DMA) SCSI host adapters, network cards

6 16-bit only None Sound cards (high DMA), network cards

7 16-bit only None Sound cards (high DMA), network cards

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BUS Arbiter

Who becomes bus master? Centralized distributed

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處理器

DMA控制器 1

DMA控制器 2BG1 BG2

B R

B BSY

圖 4.20 一個使用菊花鏈作為匯流排仲裁的簡易佈置

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BBSY

BG1

BG2

主匯流排

BR

處理器 DMA 控制器 2 處理器

時間

圖 4.21 圖 4.20中裝置的匯流排主控權轉移期間的訊號序列

此例表示 DMAC2 成為 bus master 的時序圖

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圖 4.22一個分散式仲裁方案

設備 A 的介面電路

0 1 0 1 0 1 1 1

O.C.

Vcc

Start-Arbitration

ARB 0

ARB 1

ARB 2

ARB 3

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Free Arbitration Selection

目標檢驗 ID

DB2

DB5

DB6

BSY

SEL

圖 4.42 在 SCSI 匯流排上的仲裁和選擇。裝置 6 贏得仲裁結果並選擇裝置 5

分散式仲裁以 SCSI 為例

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BUS timing

Synchronous bus Includes a clock in the control lines A fixed protocol for communication that is relative to the clock Advantage: involves very little logic and can run very fast Disadvantages:

Every device on the bus must run at the same clock rate To avoid clock skew, they cannot be long if they are fast

Asynchronous It is not clocked (using master-ready and slave-ready instead) It can accommodate a wide range of devices It can be lengthened without worrying about clock skew It requires a handshaking protocol

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圖 4.23 一個同步匯流排上的輸入傳送時序圖

匯流排週期

資料

匯流排時脈

定址與命令

t0 t1 t2

時間

Synchronous bus (ideal)

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圖 4.24 圖 4.23 的輸入傳送的詳細時序圖

資料

匯流排時脈

定址與命令

t0 t1t2

定址與命令

資料

被主控裝置偵測到

被從動裝置偵測到

tAM

tAS

tDS

tDM

時間Synchronous bus (consider delay)

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圖 4.26 在輸入操作期間資料傳遞的信號交換控制

從動裝置就緒

資料

主控裝置就緒

定址與命令

匯流排週期

t1 t2 t3 t4 t5t0

時間

Asynchronous bus

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圖 4.27 在輸出作業期間資料傳遞的信號交換控制

匯流排週期

資料

主控裝置就緒

從動裝置就緒

定址與命令

t1 t2 t3 t4 t5t0

時間

Asynchronous bus

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Parallel port vs serial port

serial port Information is transferred in or out one bit at a time RS232 USB Firewire (IEEE 1394) Serial ATA (Disk)

parallel port data is transferred in or out in parallel Printer port microprocessor to communicate with peripherals PCI SCSI Parallel ATA (Disk)

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Types of Buses

Processor-Memory Bus (design specific) Short and high speed Only need to match the memory system

Maximize memory-to-processor bandwidth Connects directly to the processor Optimized for cache block transfers

I/O Bus (industry standard) Usually is lengthy and slower Need to match a wide range of I/O devices Connects to the processor-memory bus or backplane bus

Backplane Bus (standard or proprietary) Backplane: an interconnection structure within the chassis Allow processors, memory, and I/O devices to coexist Cost advantage: one bus for all components

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處理器

橋接器

處理器匯流排

PCI 匯流排

主記憶體

額外的記憶體

光碟機控制器

磁碟控制器

磁碟 1 磁碟 2 光碟機

SCSI控制器

USB控制器

影像

鍵盤 遊戲

磁碟IDE

SCSI 匯流排

圖 4.38 一部計算機使用不同介面標準的範例

ISA介面乙太介面

Standard I/O interfaces

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A Computer System with One Bus:

Backplane Bus

A single bus (the backplane bus) is used for: Processor to memory communication Communication between I/O devices and memory

Advantages: Simple and low cost Disadvantages: slow and the bus can become a major bottleneck Example: IBM PC - AT

Processor Memory

I/O Devices

Backplane Bus

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Buses in PC-XT and PC-AT

ISA (Industry Standard Architecture) IBM-PC and PC-XT: 8 bits at 4.77MHz, directly connect to 8088, 2-stage bus

cycle (2.38Mbyte/sec bus bandwidth) AT bus: extension slot + 8 bit ISA

16 bits at 8.33MHz for 80286

CPU

BIOS

DRAMcontrl.

DRAM

timer, int. contl.

DMA contrl.

bus buffer

ISA bus

expansion slots

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A Two-Bus System

I/O buses tap into the processor-memory bus via bus adaptors: Processor-memory bus: mainly for processor-memory traffic I/O buses: provide expansion slots for I/O devices

Apple Macintosh-II NuBus: Processor, memory, and a few selected I/O devices SCCI Bus: the rest of the I/O devices

Processor Memory

I/OBus

Processor Memory Bus

BusAdaptor

BusAdaptor

BusAdaptor

I/OBus

I/OBus

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Buses in PC(486)

16-bit ISA cannot support Window applications --- video data VESA LB (local bus) -- linked to 486 local bus, 33MHZ, 32 bits

ISA bus

expansion slots

486 CPU

local bus L2cache

DRAM

ISA bridge

bus buffer

video card

LANadapter

HDDcontrl.

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A Three-Bus System

A small number of backplane buses tap into the processor-memory bus Processor-memory bus is only used for processor-memory traffic I/O buses are connected to the backplane bus

Advantage: loading on the processor bus is greatly reduced

Processor Memory

Processor Memory Bus

BusAdaptor

BusAdaptor

BusAdaptor

I/O BusBackplane Bus

I/O Bus

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Buses in PC (Pentium)

A three-bus system

Pentium CPU

L2 Cache

host bus

Memory

PCI chipset

PCIbridge

Data bus

PCI bus

ISA bus

PCI/ISA bridge

Video card

LANadapter

SCSIadapter

IDEcontroller

SuperIO chip Modem sound

card

HDDCD-ROM

monitor

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51

Processor/MemoryBus

PCI Bus

I/O Busses

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PCI Bus

1992 by Intel Support PnP (plug and play), but is not popular until windows 95 rel

ease Support memory, I/O and configuration addressing, where configura

tion address is for PnP PCI is a 64-bit bus, though it is usually implemented as a 32-bit bus.

It can run at clock speeds of 33 or 66 MHz. At 32 bits and 33 MHz, it yields a throughput rate of 133 MBps.

PCI-Express 3GIO, 2.5Bb/s 1394b, USB 2.0, InfiniBand and Gigabit Ethernet

PCI-X (PCI extended) 133 MBps to as much as 1 GBps.

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Requirements for Plug and Play

System Hardware system chipset and system bus controllers, must be capable of

handling PnP devices Peripheral Hardware

These devices must be PnP-aware so that they are capable of identifying themselves when requested, and able to accept resource assignments from the system when they are made.

The System BIOS Routines built into the BIOS perform the actual work of collecting

information about the different devices and determining what should use which resources. The BIOS also communicates this information to the operating system, which uses it to configure its drivers and other software to make the devices work correctly.

The Operating System Finally, the operating system must be designed to work with the BIOS

(and thus indirectly, with the hardware as well). support is Windows 95.

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SCSITransfer Mode

Defining Standard

Bus Width (bits)

Bus Speed (MHz)

Through- put (MB/s)

Special Features

CablingSignaling Method

Maximum Devices Per

Bus

Maximum Cable

Length (m)

"Regular" SCSI

(SCSI-1)SCSI-1 8 5 5 　 50-pin

SE 8 6

HVD 8 25

Wide SCSI SCSI-2 16 5 10 　 68-pinSE 16 6

HVD 16 25

Fast SCSI SCSI-2 8 10 10 　 50-pinSE 8 3

HVD 8 25

Fast Wide SCSI

SCSI-2 16 10 20 　 68-pinSE 16 3

HVD 16 25

Ultra SCSISCSI-3 /

SPI8 20 20 　 50-pin

SE8 1.5

4 3

　 HVD 8 25

Wide Ultra SCSI SCSI-3 /

SPI16 20 40 　 68-pin

SE8 1.5

4 3

　 HVD 16 25

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SCSITransfer Mode Defining St

andardBus Width (bits)

Bus Speed (MHz)

Through- put (MB/s)

Special Features

CablingSignaling Method

Maximum Devices Per

Bus

Maximum Cable

Length (m)

Ultra2 SCSISCSI-3 /

SPI-28 40 40 　 50-pin

LVD8 12

2 25

HVD 8 25

Wide Ultra2 SCSI

SCSI-3 / SPI-2

16 40 80 　 68-pin

LVD16 12

2 25

HVD 16 25

Ultra3 SCSISCSI-3 /

SPI-316 40 (DT) 160

At least one of Fast-80, CRC, DV,

QAS, Packet

68-pin LVD

16 12

2 25

Ultra160(/m) SCSI

SCSI-3 / SPI-3

16 40 (DT) 160Fast-80,

CRC, DV 68-pin LVD16 12

2 25

Ultra160+ SCSI

SCSI-3 / SPI-3

16 40 (DT) 160

Fast-80, CRC, DV,

QAS, Packet

68-pin LVD

16 12

2 25

Ultra320 SCSI

SCSI-3 / SPI-4

16 80 (DT) 320Fast-160, ?

68-pin LVD16 12

2 25

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USB

Data rate USB 1.1

Low speed 1.5Mb/s Full speed 12Mb/s

USB 2.0 High speed 480Mb/s

127 devices ( 用 7 bits 表示連接的設備 ) PnP It is expected to completely replace serial and parallel

ports

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主電腦

根集線器

集線器

圖 4.43 通用序列匯流排樹狀結構

集線器 I/O 設備

集線器

I/O 設備 I/O 設備

I/O 設備 I/O 設備

I/O 設備

USB Tree architecture

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主電腦

根集線器

集線器 A

設備 D

圖 4.44 分開的匯流排運作

F/LS

HS HS

HSHS - 高速F/LS - 全速 / 低速

集線器 B

設備 C

支援不同的速度連線

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PID 0 PID 1 PID 2 PID 3 PID 0PID 0 PID 1 PID 2 PID 3

(a) 封包辨識字欄位

PID ADDR ENDP CRC16

8 7 4 5位元

(b) 標記封包 IN或是 OUT

PID DA T A CRC16

8 0 到 8192 16位元

(c) 資料封包

圖 4.45 USB封包型式

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A CK

權杖資料 0

權杖資料 1

圖 4.46 一個輸出傳輸

主機 集線器 I/O 裝置

權杖資料 0

A CK

A CK

權杖資料 1

A CK

時間