1Luis A. BathenUniversity of California, Irvine

E-RoC: Embedded RAIDs-on-Chip for Low Power Distributed Dynamically Managed Reliable Memories*

Luis Bathen, Nikil DuttUniversity of California, Irvine

* This work was presented at DATE 2011

2Luis A. BathenUniversity of California, Irvine

Distributed Memories and Voltage Scaling

• Trend towards multicore platforms• Distributed on-chip memories

• By 2014 up to 94% chip area may be memories• Saving Power?

• Voltage Scaling

x

y

Process Variations

Nominal Vdd

AggressivelyLow Vdd

ParametricManufacturingErrors

Errors intentionallyIntroduced by aggressive Vdd scaling

Low Vdd

Overdriven Vdd

Memory Array

[Kurdahi, Eltawil 2008]

Technology scaling + environment

+ +

+

Increased vulnerability to soft-errors!

Voltage

Reduced power consumption at the cost of introducing errors!

3Luis A. BathenUniversity of California, Irvine

Related Work in Memory Reliability

• BIST/ECC• Makhzan et al. [ICCD 2007], Kim et al. [DATE’06], Lee et al.

[CASES ’06], Ghosh et al. [ITC 2004]• Redundancy

• Lucente et al. [CICC ‘90] , Zhang et al. [ICS ‘04]• ECC/replication hybrids

• Zhang et al. [DSN ’03], Li et al. [ICCAD ‘05]

• RAID: very successful for reliable distributed data storage• Can we exploit RAID notions for on-chip memories?

Memory characterization/BIST is very

expensive !

ECC/hybrids incur high performance and power consumption overheads

4Luis A. BathenUniversity of California, Irvine

Towards Embedded RAIDs (E-RAIDs)

• Guarantee 24/7 uptime under heavy IO loads

• Software/Hardware RAID controllers

• Different RAID levels• For performance/reliability

(RAID0, RAID1, RAID5…)

Traditional RAID – Storage Sytems Embedded RAID - SoCs

SPM SPM SPM SPM

CPU CPU CPU CPURAID

Controller

HD HD HD HD

HDCPU

RAID 1(Mirroring)

RAID 5 (Stripe + Mirroring)

System Bus On-Chip Bus

System Bus

ERoC

Introduce HW/SW E-RAID Manager

DSPAM Allocation Policies

Logical SPMs(Virtual Address Space)

Aggressive Voltage Scaling

Different PlatformConfigurations

(CMP, NoC, etc.)

E-RoC Manager

Embedded RAIDs-on-

Chip

Embedded RAID Levels

E-RoC Framework

SPM SPM SPM SPM

CPU CPU CPU CPU

On-Chip Bus

System Bus

ERoC

E-RoC Manager

5Luis A. BathenUniversity of California, Irvine

Case for E-RAIDs

1.00E-201.00E-181.00E-161.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02

1.00E+00

-20

-10

0

10

20

30

40

50

60

Power reduction through aggressive voltage scaling

VddPro

bab

ilig

y o

f F

ailu

re (

SE

U) P

ow

er Red

uctio

n P

ercentag

e

- Provide Same Memory Space

- Parallel IOs

- Voltage scaled

Vs. 512 BSPM

512 BSPM

512 BSPM

512 BSPM

512 BSPM

512 BSPM

512 BSPM

512 BSPME-RAID 0

(1 Byte stripping)E-RAID 0

(1 Byte stripping)

E-RAID 1 (Mirroring)

E-RoC Manager IF

8bit

4 x 8bit

Byte 0 Byte 1 Byte 2 Byte 332bit

2KB SPM@ Nominal Vdd

14% increase@ 2e-20 SEU

8% savings@ 1e-15 SEU

19% savings@ 6e-12 SEU

46% savings@ 7e-2 SEU

Incurs power consumption overhead at high Vdd

Saves power at low VddVoltage scale induced errors handled automatically by E-RAID levels!

ERAID Levels

6Luis A. BathenUniversity of California, Irvine

4K 4K 4K 4K 4K

4K 4K 4K 4K 4K

Embedded RAID Levels and Logical SPMs

Traditional RAIDs• Statically defined

• Create and use for entire app run• Allocate an entire SPM to a RAID level

• Greatly limits SPM utilization

Embedded RAIDs• Customized E-RAID levels

• (Mirroring, Parity, No E-RAID, etc.)

• Logical SPMs (LSPMs)• Associated with an E-RAID level

• Expose LSPMs to the outside world • Managed as regular SPMs

• Efficient allocation policies

LSPM of 1K LSPM of 2K

Mirroring, 2x1K Parity, 3x2K

E-RoC Manager

Address Virtualization Layer

E-RAID Level Layer

Inefficient SPM utilization!

CPU0 CPU1 CPU2

App1: 1KB App2:2KB

Mirroring, 2x1K

1K 1K

Parity, 3x2K

1K 1K

ERoC SPM SPM SPM SPM

CPU CPU CPU CPUMM

1K

App2 is not successful in

creating Parity RAID

CPU0 CPU1 CPU2

App1: 1KB App2:2KB

Physical Level Layer 1K 1K

1K

1K 1K

1K 1K 1K

Transparent and efficient utilization of SPM space!

Successful allocation of both E-RAID levels!

7Luis A. BathenUniversity of California, Irvine

Sample Experimental Results: Power & Performance Comparison

0.9

0.95

1

1.05

1.1

1.15

1.2

1.25

Normalized Performance

JPEGENC JPEGDEC H263

Points of Comparison

Per

form

ance

Ove

rhea

d

Platform: 8 Core CMP with 8x4KB SPMs (32KB)Baseline: SPM @ Nominal VddAll others: Voltage Scaled (Vdd = 0.65)Benchmarks: JPEG Encoder/Decoder, H263 Encoder ERoC SPM SPM SPM SPMSPM SPM SPM SPM

CPU CPU CPU CPUCPU CPU CPU CPUMM

SPMECC

DUP

ERAID1

ERAID1

Partia

l

ERAID1P

ERAID1P

Par

tial

0

0.5

1

1.5

2

2.5

3

3.5

4

Normalized PowerJPEGENC JPEGDEC H263

Points of Comparison

Pow

er C

onsu

mp

tion

Ove

rhea

ds

E-RoC:Minimal overall performance overheadAVG: 2.3%

Traditional (ECC/DUP): High Performance OverheadAVG: 9.2%

E-RoC:AVG savings of

76%

Traditional (ECC/DUP): High Power Consumption Overhead AVG: 64% increase

Reduced power consumption with minimal performance overhead!

8Luis A. BathenUniversity of California, Irvine

Conclusion• Introduced Embedded RAIDs-on-Chip (E-RoC)

• Key ideas are: 1. Reliability via redundancy using E-RAID levels2. Custom E-RAID levels optimized for use in embedded SoCs3. Dynamic allocation of distributed SPMs4. Virtualization support (Logical SPMs)

• Use RAID-like policies to achieve a fully distributed low power and reliable on-chip memory subsystem

• Our experimental results show that E-RoC can attain• 76 % average power reduction over ECC based approaches• Minimal performance overhead (2.3% AVG)

• To learn more come to my poster!