1 modeling and specification introduction models of computation specification languages state...
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Modeling and SpecificationModeling and Specification Introduction Models of Computation Specification Languages
State Charts SDL Petri Nets UML, MSC VHDL, Verilog SpecC, SystemC, SystemVerilog
Levels of Hardware Modeling ConclusionCDA 4630/5636 – Spring 2016 Copyright © 2016 Prabhat Mishra
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Embedded Systems Design Flow
ConceptSpecification
HW/SWPartitioning
Hardware Components
Software Components
Estimation -Exploration
Hardware
Software
Synthesis
Compilation
Validation and Evaluation
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SpecificationProvide a clear and unambiguous description
of the system functionality
Support different models of computations Petri Nets, FSMs, Data Flow Models, …
Should not constrain implementation options
Enable computer-aided analysis techniques Estimation and exploration Partitioning Synthesis Validation
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Requirements for SpecificationHierarchy
Humans are not capable of understanding systems containing more than ~5 objects. Behavioral hierarchy
– states, processes, procedures.
Structural hierarchy
– processors, printed circuit boards
Timing behavior
State-oriented behavior Required for reactive systems
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Requirements for SpecificationEvent-handling
external or internal events
Support for the design of dependable systems Unambiguous semantics
Exception-oriented behavior Not acceptable to describe exception in each state
.
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Requirements for SpecificationConcurrency
Real-life systems are concurrent
Synchronization and communication Components needs to communicate
Presence of programming elements Arithmetic operations, loops, and function calls
Executability No algebraic specification
Support for the design of large systemsDomain-specific support
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Requirements for SpecificationReadabilityPortability and flexibilityTermination
It should be clear, at which time all computations are completed
Support for non-standard I/O devices Direct access to switches, displays, ...
Non-functional properties fault-tolerance, disposability, EMC-properties,
weight, size, user friendliness, extendibility, expected life time, power consumption...
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OutlineOutline Introduction Models of Computation Specification Languages
State Charts SDL Petri Nets UML, MSC VHDL, Verilog SpecC, SystemC, SystemVerilog
Levels of Hardware Modeling Conclusion
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Modeling versus SpecificationModeling (or models of computation) is the
underlying formalism to represent the system. For example: FSM, Graph Model, ….
Specification is performed using a language that supports the model of computation. Specification language is only a syntactic sugar,
does not add any new representation capability. For example, a language that is designed for capturing
graph-based models, can only capture nodes & edges.
Sequential computation supported by C/C++/Java Parallel computation supported by VHDL/Verilog
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Finite State Machine (FSM)Traffic light controller
Traffic sensors: TA, TB (TRUE when there’s traffic)
Lights: LA, LB
TA
LA
TA
LB
TB
TB
LA
LB
Academic Ave.
Bravado
Blvd.
Dorms
Fields
DiningHall
Labs
Copyright © 2012 Prof. Montek Singh, University North Carolina, Chapel Hill
S0LA: greenLB: red
S1LA: yellow
LB: red
S3LA: red
LB: yellow
S2LA: red
LB: green
TA
TA
TB
TB
Reset
Circles: StatesArcs: Transitions
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FSM Timing Diagram
CLK
Reset
TA
TB
S'1:0
S1:0
LA1:0
LB1:0
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10
S1 (01) S2 (10) S3 (11) S0 (00)
t (sec)
??
??
S0 (00)
S0 (00) S1 (01) S2 (10) S3 (11) S1 (01)
??
??
0 5 10 15 20 25 30 35 40 45
Green (00)
Red (10)
S0 (00)
Yellow (01) Red (10) Green (00)
Green (00) Red (10)Yellow (01)
S0LA: greenLB: red
S1LA: yellow
LB: red
S3LA: red
LB: yellow
S2LA: red
LB: green
TA
TA
TB
TB
Reset
S1
S0
S'1
S'0
CLK
next state logic output logicstate register
Reset
LA1
LB1
LB0
LA0
TA
TB
inputs outputs
S1 S0
r
Current State Inputs Next State
S1 S0 TA TB S'1 S'00 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1
1 0 X 1 1 0
1 1 X X 0 0
Copyright © 2012 Prof. Montek Singh, University North Carolina, Chapel Hill
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Control and Data Flow Graph (CDFG)Commonly used to model
program structure.
X = A + B
i = 0?
Y = C – D
Z = 0
+ -
*
Data Flow Graph (DFG)Z = (A + B) * (C – D)
A DB C
Z
Z = X * Y
X Y
Control Flow Graph (CFG)if (i == 0) … else …
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© 2006 Elsevier
Task Graph
Used to model multi-rate systems.
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P1 P2
P3
P4
P5
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More Examples
Discrete event modelDiscrete event model
abc
timeactiona:=5 b:=7 c:=8 a:=6 a:=9
queue
5 10 13 15 19
Communicating finite state machines (CFSMs):Communicating finite state machines (CFSMs):
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Models of Computation: Examples
Differential equationsDifferential equations
Synchronous message passingSynchronous message passing
bt
x
2
2
Asynchronous message passingAsynchronous message passing
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OutlineOutline Introduction Models of Computation Specification Languages
State Charts SDL Petri Nets UML, MSC VHDL, Verilog SpecC, SystemC, SystemVerilog
Levels of Hardware Modeling Conclusion
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StateCharts: D. Harel, 1987
superstate
substates
FSM will be in exactly one of the substates of S if S is active(either in A or in B or ..)
FSM will be in exactly one of the substates of S if S is active(either in A or in B or ..)
Hierarchy
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Concurrency
Convenient way of describing concurrency. AND-super-states: FSM is in all (immediate)
sub-states of a super-state.
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Timers
Timer needs to be modeled.StateCharts uses special edges for timeouts.
If event a does not happen while the system is in the left state for 20 ms, a timeout will take place.
If event a does not happen while the system is in the left state for 20 ms, a timeout will take place.
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Timers in Answering Machine
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StateCharts: Simulation Phases
Three phases:
1. Effect of external changes on events and conditions
is evaluated,
2. The set of transitions to be made in the current step
and right hand sides of assignments are computed,
3. Transitions become effective, variables obtain new
values.
Separation into phases 2 and 3 guarantees
deterministic and reproducible behavior.
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Example
In phase 2, variables a and b are assigned to temporary variables. In phase 3, these are assigned to a and b. As a result, variables a and b are swapped.
In a single phase environment, executing the left state first would assign the old value of b (=0) to a and b. Executing the right state first would assign the old value of a (=1) to a and b. The execution would be non-deterministic.
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Reflects Model of Clocked Hardware
In an actual clocked (synchronous) hardware system, both registers should be swapped.
Same separation into phases found in other languages as well, especially those that are intended to model hardware.
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Broadcast Mechanism
Values of variables are visible to all parts of the StateCharts model.
New values become effective in phase 3 of the current step and are obtained by all parts of the model in the following step.
StateCharts implicitly assumes a broadcast mechanism for variables.
StateCharts is appropriate for local control systems, but not for distributed applications for which updating variables may take some time.
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Evaluation of StateChartsPros:
Hierarchy allows nesting of AND/OR-superstates.Large number of commercial simulation tools
available (StateMate, StateFlow, BetterState, ...)Back-end tools translate StateCharts into C or
VHDL – enabling hw/sw implementations
Cons: Generated C programs frequently inefficient, Not useful for distributed applications, No program constructs, No description of structural hierarchy.
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OutlineOutline Introduction Models of Computation Specification Languages
State Charts General Language Characteristics SDL, UML, MSC Petri Nets VHDL, Verilog SpecC, SystemC, SystemVerilog
Levels of Hardware Modeling Conclusion
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Synchronous vs. Asynchronous Languages
Synchronous languages describe concurrently operating automata.
Synchronous languages aim at providing high level, modular constructs, to make the design of such an automaton easier [Halbwachs].
Synchronous languages implicitly assume the presence of a (global) clock. Each clock tick, all inputs are considered, new outputs and states are calculated and the transitions are made.
Requires a broadcast mechanism.StateCharts is a synchronous language.
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Communication ParadigmsMessage passing
Non-blocking communication Sender does not have to wait until message has
arrived; potential problem: buffer overflow
Blocking communication Sender will wait until receiver has received message Explicit acknowledge from receiver required. Receiver
can do checking before sending acknowledgement.
Shared memoryCritical sections = sections at which exclusive
access to some resource r must be guaranteed.StateCharts uses shared memory.
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Timing Specification Four types of timing specs required: Burns’90
Measure elapsed time Check, how much time has elapsed since last call
Means for delaying processes Possibility to specify timeouts
We would like to be in a certain state only a certain maximum amount of time.
Methods for specifying deadlines With current languages not available or specified in separate control file.
StateCharts comprises a mechanism for specifying timeouts. Other types of timing specs are not supported.
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OutlineOutline Introduction Models of Computation Specification Languages
State Charts SDL Petri Nets UML, MSC VHDL, Verilog SpecC, SystemC, SystemVerilog
Levels of Hardware Modeling Conclusion
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SDLSpecification and Description Language
Designed for specification of distributed systems.
Defined by International Telecommunication Union (ITU): Z.100 recommendation in 1980
Provides textual and graphical formats.
Like StateCharts, it is based on CFSM model of computation; each FSM is called a process
It uses message passing for communications, and supports operations on data.
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FSMs/Processes in SDL
output
input
state
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Operations on Data
Variables can be declared locally for processes.
Their type can be predefined or defined in SDL
SDL supports abstract data types (ADTs).
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Communication in SDLCommunication between FSMs (processes) is based on message-passing, assuming a
potentially indefinitely large FIFO-queue. Each process fetches next entry from FIFO, Checks if input enables transition,
if yes: transition takes place, if no: input is ignored (exception: SAVE-mechanism).
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Process Interaction DiagramsInteraction between processes can be
described in process interaction diagram Special case of block diagrams.
In addition to processes, the diagrams contain channels and declarations of local signals.
,
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Designation of RecipientsThrough process
identifiers: OFFSPRING represents
identifiers of processes generated dynamically.
Explicitly: By including the channel
name.
Implicitly: If signal names imply
channel names B Sw1
CounterVia Sw1
CounterTO OFFSPRING
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Hierarchy in SDLProcess interaction diagrams can be included
in blocks. The root block is called system.
Processes cannot contain other processes, unlike in StateCharts.
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Timers
Timers can be declared locally. Elapsed timers put signal into queue.
RESET also removes timer signal from queue.
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Description of Network Protocols
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Vending Machine
Machine selling pretzels, (potato) chips, cookies, and doughnuts:
accepts nickels, dime, quarters, and half-dollar coins.
Not a distributed application.
[J.M. Bergé, O. Levia, J. Roullard: High-Level System Modeling, Kluwer Academic Publishers, 1995]
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Overall view of vending machine
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DecodeRequests
p
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ChipHandler
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SDL: SummaryExcellent for distributed applications
Used to specify ISDN
Commercial tools available from SINTEF, Telelogic, Cinderella (//www.cinderella.dk).
Not necessarily deterministic Order in which FSMs are reading input is unknown Not a synchronous language
Implementation requires bound for the maximum length of FIFOs; may be very difficult to compute,
Timer concept adequate for soft deadlines,Limited programming language support,No description of non-functional properties.
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OutlineOutline Introduction Models of Computation Specification Languages
State Charts SDL Petri Nets UML, MSC VHDL, Verilog SpecC, SystemC, SystemVerilog
Levels of Hardware Modeling Conclusion
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Token in Single-Track Rail
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© 2006 Elsevier
Petri netParallel and nondeterministic model of computation.
place
arc
token transition
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Petri NetsCarl Adam Petri, PhD thesis, 1962.
Focus on modeling causal dependencies; no global synchronization assumed (message passing only).
Applications:Modeling of resources, mutual exclusion, synchronization.
Key elements:Conditions: Either met or not met.
Events: May take place if certain conditions are met.
Flow relations: Relates conditions and events.
Conditions, events and the flow relation form a bipartite graph (graph with two kinds of nodes).
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Synchronization at Single Track Rail
Preconditions
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Playing the Token Game
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Playing the Token Game
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Playing the Token Game
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Conflict for Resource Track
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Condition/Event Nets
N=(C,E,F) is called a net, iff the following holds C and E are disjoint sets F (C E) (E C); is a binary relation
Definition: Let N be a net and let x (C E) x := {y | y F x} is called the set of preconditions. x := {y | x F y} is called the set of postconditions.
xx x
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Loops and Pure Nets
Def.: Let (c,e) C E. (c,e) is called a loop iff cFe eFc.
Definition: Net N = (C,E,F) is called pure, if F does not contain any loops.
Definition: Net N = (C,E,F) is called pure, if F does not contain any loops.
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Simple nets
A net is called simple if disjoint elements have disjoint pre- and postcondition sets.
Example (not a simple net):
Definition: Simple nets with no isolated elements meeting some additional restrictions are called condition/event nets
Definition: Simple nets with no isolated elements meeting some additional restrictions are called condition/event nets
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Place/Transition Nets
(P, T, F, K, W, M0) is called a place/transition net iff
1. N=(P,T,F) is a net with places p P and transitions t T
2. K: P (N0 {}) \{0} denotes the capacity of places( symbolizes infinite capacity)
3. W: F (N0 \{0}) denotes the weight of graph edges
4. M0: P N0 {} represents the initial marking of places
W
M0
(Segment of some net)
defaults:K = W = 1
defaults:K = W = 1
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Dining Philosophers Problem n>1 philosophers sitting at a round table; n forks, n plates with spaghetti; philosophers either thinking or eating spaghetti (using left and right fork).
How to model conflict for forks?How to guarantee avoiding starvation?
2 forks needed!
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Condition/event net model
Let x {1..3}tx: x is thinking
ex: x is eating
fx: fork x is available
Model quite clumsy.
Difficult to extend to more philosophers.
Model quite clumsy.
Difficult to extend to more philosophers.
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Predicate/Transition NetsCompact representation of complex systems.
Key changes:Tokens are becoming individuals;
Transitions enabled if functions at incoming edges are true;
Individuals generated by firing transitions defined through functions
Changes can be explained by folding and unfolding C/E nets, semantics can be defined by C/E nets.
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Predicate/Transition ModelTokens: individuals.
Let x be one of the philosophers,Let l(x) be the left spoon of x,Let r(x) be the right spoon of x.
Model can be extended to arbitrary numbers of people
p1p3
p2
f1f2
f3
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SummaryPros:
Appropriate for distributed applications,
Well-known theory for formally proving properties,
Cons (for the nets presented) :problems with modeling timing,
no programming elements,
no hierarchy.
Extensions:Extensive efforts on removing limitations.
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63
OutlineOutline Introduction Models of Computation Specification Languages
State Charts SDL Petri Nets UML, MSC VHDL, Verilog SpecC, SystemC, SystemVerilog
Levels of Hardware Modeling Conclusion
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Message Sequence Charts (MSC)Graphical means for representing schedules;
time used vertically, geographical distribution horizontally.
No distinction between accidental overlap and synchronization
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Time/Distance Diagrams©
ww
w.o
pen
trac
k.c
h
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Establishing a Modem Connection
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Life Sequence Charts (LSC)
W. Damm, D. Harel: LSCs: Breathing Life into Message Sequence Charts, Formal Methods in System Design, 19, 45–80, 2001
Distinction between Universal and Existential Charts
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UML (Unified Modeling Language)
Fro
m:
ww
w.s
dm
agaz
ine.
com
/do
cum
ents
/s=
815/
sdm
0012
c/
Designing with a sequence of refinements
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MSC/LSC used in UML
Heavy usage in UML (known as sequence diagram);
No precise timing.
Many kinds of additional elements
http://www.gentleware.com/products/documentation/PoseidonUsersGuide/x1462.html
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State Machine DiagramsState machine diagrams/State diagrams:
UML includes variant of StateCharts
© Scott Ambler, Agile Modeling, www.agilemodeling.com, 2003
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Activity Diagram
© Cris Kobryn: UML 2001: A Standardization Odyssey, CACM, October, 1999
Extended Petri nets include decisions (like in flow charts).
Graphical notation similar to SDL.
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Deployment Diagram
Describe execution architecture of systems (HW or SW).
Important for embedded systems.
© Scott Ambler, Agile Modeling, www.agilemodeling.com, 2003
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Use Case Diagram
Captures typical application scenarios
© Scott Ambler, Agile Modeling, www.agilemodeling.com, 2003
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Package diagramRepresents the partitioning into packages. Introduces hierarchy.
Example: Use case package diagram.
© Scott Ambler, Agile Modeling, www.agilemodeling.com, 2003
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Class DiagramsDescribe object classes.
Example:
© Scott Ambler, Agile Modeling, www.agilemodeling.com, 2003
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Timing DiagramsCan be used to show the change of the state of an object over time.
© Scott Ambler, Agile Modeling, www.agilemodeling.com, 2003
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Component DiagramRepresent components used in applications:
© Scott Ambler, Agile Modeling, www.agilemodeling.com, 2003
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OutlineOutline Introduction Models of Computation Specification Languages
State Charts SDL Petri Nets UML, MSC Verilog, VHDL SpecC, SystemC, SystemVerilog
Levels of Hardware Modeling Conclusion
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VerilogHW description language competing with VHDLStandardized:
IEEE 1364-1995 (Verilog version 1.0) IEEE 1364-2001 (Verilog version 2.0)
Features similar to VHDL: Designs described as connected entities Bit-vectors and time units are supported
Features that are different: Built-in support for 4-value logic and for logic with 8 strength
levels encoded in two bytes per signal. More features for transistor-level descriptions
Less flexible than VHDL.More popular in the US (VHDL common in Europe)
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Representation: Structural ModelsStructural models
Are built from gate primitives and/or other modulesThey describe the circuit using logic gates — much as you would see in an implementation of a circuit.
Identify:This is a multiplexor — it selects one of n inputs (2 here) and passes it on to the output
module mux (output f, input a, b, sel);
and #5 g1 (f1, a, nsel),g2 (f2, b, sel);
or #5 g3 (f, f1, f2);not g4 (nsel, sel);
endmodule
a
bf
sel
f = a • sel’ + b • sel
f1
f2
g1
g2
g3
g4
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An Example: Half AdderModule testAdd (test bench) generated inputs for module halfAdd (design) and displayed changes.
module tBench;wire su, co, a, b;
halfAdd ad(su, co, a, b);testAddtb(a, b, su, co);
endmodule
module halfAdd (sum, cOut, a, b); output sum, cOut;input a, b;
xor #2 (sum, a, b);and #2 (cOut, a, b);
endmodule
module testAdd(a, b, sum, cOut);input sum, cOut;output a, b;reg a, b;
initial begin$monitor ($time,, “a=%b, b=%b,
sum=%b, cOut=%b”, a, b, sum, cOut);a = 0; b = 0;#10 b = 1;#10 a = 1;#10 b = 0;#10 $finish;
endendmodule
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Inside the SimulatorA time-ordered list of events is maintained
Event — a value-change scheduled to occur at a given time All events for a given time are kept together
The scheduler removes events for a given time… …propagates values, and executes gate models, creates new events…
Scheduler
Gate Models
Network Connections (fanouts)
executeslooks at
schedules new event
remove current events
time-ordered event list
Gate Outputs
updatesti tj tk
•••tn
all the events for time tj
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Event-Driven Simulation
A=1 at 25 g2 #3
g1 #2
g3 #5
1
1
0
A=0
B=1
C=0
D=1
initial values as
shown
initial values as
shown
B=0 at27
A=1 at 25C=1 at30
g2 #3
g1 #2
g3 #5
1
1
0
A=1
B=0
C=0
D=1
the event list
(at 27)initial
values as shown
A=1 at 25B=0 at
27
g2 #3
g1 #2
g3 #5
1
1
0
A=1
B=0
C=1
D=1
final
(at 30)
Eval g1
Eval g2, g3
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One Modern Design Methodology
alwaysmumblemumbleblahblah
alwaysmumblemumbleblahblah
Synthesizable Verilog
Synthesis
Technology
Mapping
LE 1
LE 2
Place and Route
gates, gates, gates, …
Logic Elements in FPGA Chip
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VHDLHDL = hardware description languageTextual HDLs replaced graphical HDLs in the
1980s (better for complex behavior).In this course:
VHDL = VHSIC hardware description languageVHSIC = very high speed integrated circuit
1980: Definition started by DoD in 19801984: first version of the language defined,
based on ADA (based on PASCAL)1987: IEEE standard 1076; 1992 revision;Recently: VHDL-AMS models analog
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Entities and ArchitecturesEach design unit is called an entity.
Entities are comprised of entity declarations and one or several architectures.
Each architecture includes a model of the entity. By default, the most recently analyzed architecture is used. Another architecture can be requested in a configuration.
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Entity Declaration
entity full_adder is
port(a, b, carry_in: in Bit; -- input ports
sum,carry_out: out Bit); --output ports
end full_adder;
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Architectures
architecture behavior of full_adder is begin sum <= (a xor b) xor carry_in after 10 Ns; carry_out <= (a and b) or (a and carry_in) or (b and carry_in) after 10 Ns; end behavior;
architecture behavior of full_adder is begin sum <= (a xor b) xor carry_in after 10 Ns; carry_out <= (a and b) or (a and carry_in) or (b and carry_in) after 10 Ns; end behavior;
Architectural bodies can be- behavioral bodies or - structural bodies.
Bodies not referring to hardware components are called behavioral bodies.
Architectural bodies can be- behavioral bodies or - structural bodies.
Bodies not referring to hardware components are called behavioral bodies.
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Modeling BehaviorArchitecture body
describes an implementation of an entitymay be several per entity
Behavioral architecturedescribes the algorithm performed by the modulecontains
process statements, each containingsequential statements, includingsignal assignment statements andwait statements
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Behavior Example
architecture behav of reg4 isbegin
storage : process isvariable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
beginif en = '1' and clk = '1' then
stored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3;
end if;q0 <= stored_d0 after 5 ns;
q1 <= stored_d1 after 5 ns; q2 <= stored_d2 after 5 ns; q3 <= stored_d3 after 5 ns;
wait on d0, d1, d2, d3, en, clk;end process storage;
end architecture behav;
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Modeling StructureStructural architecture
implements the module as a composition of subsystems
containssignal declarations, for internal interconnections
– the entity ports are also treated as signals
component instances– instances of previously declared entity/architecture pairs
port maps in component instances– connect signals to component ports
wait statements
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Structure Example
int_clk
d0
d1
d2
d3
en
clk
q0
q1
q2
q3
bit0
d_latch
d
clk
q
bit1
d_latch
d
clk
q
bit2
d_latch
d
clk
q
bit3
d_latch
d
clk
q
gate
and2
a
b
y
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Structure ExampleFirst declare D-latch and and-gate entities and architectures
entity d_latch isport ( d, clk : in bit; q : out bit );
end entity d_latch;
architecture basic of d_latch isbegin
latch_behavior : process isbegin
if clk = ‘1’ thenq <= d after 2 ns;
end if;wait on clk, d;
end process latch_behavior;
end architecture basic;
entity and2 isport ( a, b : in bit; y : out bit );
end entity and2;
architecture basic of and2 isbegin
and2_behavior : process isbegin
y <= a and b after 2 ns;wait on a, b;
end process and2_behavior;
end architecture basic;
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Structure ExampleNow use them to implement a register
architecture struct of reg4 is
signal int_clk : bit;
begin
bit0 : entity work.d_latch(basic)port map ( d0, int_clk, q0 );
bit1 : entity work.d_latch(basic)port map ( d1, int_clk, q1 );
bit2 : entity work.d_latch(basic)port map ( d2, int_clk, q2 );
bit3 : entity work.d_latch(basic)port map ( d3, int_clk, q3 );
gate : entity work.and2(basic)port map ( en, clk, int_clk );
end architecture struct;
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Mixed Behavior and StructureAn architecture can contain both behavioral
and structural partsprocess statements and component instances
collectively called concurrent statements
processes can read and assign to signals
Example: register-transfer-level modeldata path described structurallycontrol section described behaviorally
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Mixed Example
shift_reg
reg
shift_adder
control_section
multiplier multiplicand
product
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Mixed Example
entity multiplier isport ( clk, reset : in bit;
multiplicand, multiplier : in integer;product : out integer );
end entity multiplier;
architecture mixed of mulitplier is
signal partial_product, full_product : integer;signal arith_control, result_en, mult_bit, mult_load : bit;
begin
arith_unit : entity work.shift_adder(behavior)port map ( addend => multiplicand, augend => full_product,
sum => partial_product,add_control => arith_control );
result : entity work.reg(behavior)port map ( d => partial_product, q => full_product,
en => result_en, reset => reset );
...
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Mixed Example
…
multiplier_sr : entity work.shift_reg(behavior)port map ( d => multiplier, q => mult_bit,
load => mult_load, clk => clk );
product <= full_product;
control_section : process is-- variable declarations for control_section-- …
begin-- sequential statements to assign values to control signals-- …wait on clk, reset;
end process control_section;
end architecture mixed;
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Test BenchesTesting a design by simulationUse a test bench model
an architecture body that includes an instance of the design under test
applies sequences of test values to inputsmonitors values on output signals
either using simulatoror with a process that verifies correct operation
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Test Bench Exampleentity test_bench isend entity test_bench;
architecture test_reg4 of test_bench is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(behav)port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );
stimulus : process isbegin
d0 <= ’1’; d1 <= ’1’; d2 <= ’1’; d3 <= ’1’; wait for 20 ns; en <= ’0’; clk <= ’0’; wait for 20 ns;en <= ’1’; wait for 20 ns;clk <= ’1’; wait for 20 ns;d0 <= ’0’; d1 <= ’0’; d2 <= ’0’; d3 <= ’0’; wait for 20 ns;en <= ’0’; wait for 20 ns;…wait;
end process stimulus;
end architecture test_reg4;
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VHDL: SummaryBehavioral hierarchy (procedures & functions)
Structural hierarchy but no nested processes
No specification of non-functional properties
No object-orientation
Static number of processes
Complicated simulation semantics
Too low level for initial specification
Good for intermediate language for hardware generation.
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102
OutlineOutline Introduction Models of Computation Specification Languages
State Charts SDL Petri Nets UML, MSC VHDL, Verilog SpecC, SystemC, SystemVerilog
Levels of Hardware Modeling Conclusion
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SystemC: MotivationMany standards (e.g. the GSM and MPEG-
standards) are published as C programs Standards have to be translated if special
hardware description languages have to be used
The functionalities of systems are provided by a mix of hardware and software components Simulations require an interface between
hardware and software simulators unless the same language is used for the description of hardware and software
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SystemC: Required FeaturesRequirements and solutions for modeling HW in a SW
language:C++ class library including required functions.Concurrency: via processes, controlled by sensitivity
lists and calls to wait primitives.Time: Floating point numbers in SystemC 1.0 and
Integer values in SystemC 2.0; Units ps, ns, µs etc*.Support of bit-datatypes: bitvectors of different lengths;
multiple-valued logic (2 and 4; resolution*)Communication: plug-and-play channel model, allowing
easy replacement of intellectual propertyDeterministic behavior not guaranteed.
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Hello World in SystemC#include <systemc .h>
#include <iostream>
SC _MODULE( hello ) {
void say_hello () {
cout << " hello " << name () << endl ;}
SC_CTOR( hello ) {
SC THREAD( say_hello );}
};
int sc_main ( int argc , char ** argv ) {
hello hello_inst (" world ");
sc_start ();
}105
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SystemVerilogCorresponds to Verilog versions 3.0 and 3.1.Includes:
Additional language elements to model behaviorC data types such as intType definition facilitiesDefinition of interfaces of hardware components as
separate entitiesMechanism for calling C/C++-functions from VerilogLimited mechanism for calling Verilog functions from C.
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SystemVerilog Enhanced features for describing the
testbench Classes can be used in testbenches. Dynamic process creation. Standardized inter-process communication
and synchronization including semaphores. Automatic memory allocation & deallocation. Language features providing interface for
formal verification.
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SpecC [Gajski, Dömer et. al. 2000] SpecC is based on the clear separation between
communication and computation. Enables plug-and-play for system components; models system as hierarchical networks of behaviors communicating through channels.
SpecC specifications consists of behaviors, channels and interfaces.
Behaviors include ports, locally instantiated components, private variables and functions and a public main function.
Channels encapsulate communication. They include variables and functions, used for the definition of a communication protocol.
Interfaces are linking behaviors and channels together. They declare the communication protocols which are defined in a channel.
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Example
channel
behavior
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SpecC Example
interface L {void Write(int x);};interface R {int Read (void);};channel C implements L,R { int Data; bool Valid; void Write(int x) { Data=x; Valid=true; } int Read(void) { while (!Valid) waitfor(10); return (Data); } behavior B1 (in int p1, L p2, in int p3) { void main(void) {/*...*/ p2.Write(p1);} }; behavior B2 (out int p1, R p2, out int p3) {
void main(void) {/*...*/ p3=p2.Read(); } }; behavior B(in int p1, out int p2) { int c1; C c2; B1 b1(p1,c2,c1); B2 b2 (c1,c2,p2); void main (void) { par {b1.main();b2.main(); }} };
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Other LanguagesMATLAB (Matrix Laboratory): facility for defining matrix-
based computations, extending numerical FORTRAN packages LINPACK and EISPACK with a GUI http://www.mathworks.com/academia/student_center/tutorials/
Simulink: GUI-based specification of control systems, uses MATLAB for solving these problems.
Esterel: reactive language; synchronous; all reactions are assumed to be in 0 time; communication based on instantenous broadcast; www.esterel-technologies.com
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Plot function sin(x) between 0≤x≤4π
Create an x-array of 100 samples between 0 and 4π.
Calculate sin(.) of the x-array
Plot the y-array
>>x=linspace(0,4*pi,100);
>>y=sin(x);
>>plot(y)
0 10 20 30 40 50 60 70 80 90 100-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
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Multiply sin(x) and e-x/3sin(x)
Multiply the arrays y1 and y2 correctly
Plot the y3-array
>>y3=y1.*y2;
>>plot(y3)
0 10 20 30 40 50 60 70 80 90 100-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
>>y2=exp(-x/3);
>>y1=sin(x);
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Display Facilities
plot(.)
stem(.)
Example:>>x=linspace(0,4*pi,100);>>y=sin(x);>>plot(y)>>plot(x,y)
Example:>>stem(y)>>stem(x,y)
0 10 20 30 40 50 60 70 80 90 100-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 10 20 30 40 50 60 70 80 90 100-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
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115
OutlineOutline Introduction Models of Computation Specification Languages
State Charts SDL Petri Nets UML, MSC VHDL, Verilog SpecC, SystemC, SystemVerilog
Levels of Hardware Modeling Conclusion
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Basic Design Methodology
Specification
SimulateRTL Model
Gate-levelModel
Synthesize
Simulate Test Bench
Implementation(ASIC or FPGA) Place & Route
TimingModel Simulate
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Levels of Hardware ModelingSystem levelAlgorithmic level Instruction set levelRegister-transfer level (RTL)Gate-level modelsSwitch-level modelsCircuit-level modelsDevice-level modelsLayout modelsProcess and device models
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System levelThe term system level is not clearly defined.
It is used here to denote the entire embedded system and possibly also the environment.
Such models may include mechanical as well as information processing aspects, and may be difficult to find appropriate simulators. Solutions include VHDL-AMS, SystemC or MATLAB. MATLAB and VHDL-AMS support modeling partial differential equations.
Challenge to model information processing parts of the system in such a way that the simulation model can also be used for the synthesis of the system.
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Algorithmic LevelSimulating the algorithms that we intend to use within
the embedded system.No reference is made to processors or instruction
sets.Data types may still allow a higher precision than the
final implementation.If data types have been selected such that every bit
corresponds to exactly one bit in the final implementation, the model is said to be bit-true. Translating non-bit-true into bit-true models should be done with tool support.
May consist of single processes or of sets of cooperating processes.
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MPEG-4 Full Motion Searchfor (z=0; z<20; z++) for (x=0; x<36; x++) {x1=4*x; for (y=0; y<49; y++) {y1=4*y; for (k=0; k<9; k++) {x2=x1+k-4; for (l=0; l<9; ) {y2=y1+l-4; for (i=0; i<4; i++) {x3=x1+i; x4=x2+i; for (j=0; j<4;j++) { y3=y1+j; y4=y2+j; if (x3<0 || 35<x3||y3<0||48<y3) then_block_1; else else_block_1; if (x4<0|| 35<x4||y4<0||48<y4) then_block_2; else else_block_2;}}}}}}
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Instruction LevelAlgorithms have already been compiled for the
instruction set of the processor(s) to be used.Simulations at this level allow counting the
executed number of instructions.Variations:
Simulation only the effect of instructions Transaction-level modeling: each read/write is one
transaction, instead of a set of signal assignments Cycle-true simulations: exact number of cycles Bit-true simulations: simulations using exactly the
correct number of bits
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Instruction Level: Example
Assembler (MIPS)
Simulated Semantics
and $1,$2,$3 Reg[1]:=Reg[2] Reg[3]
or $1,$2,$3 Reg[1]:=Reg[2] Reg[3]
andi $1,$2,100 Reg[1]:=Reg[2] 100
sll $1,$2,10 Reg[1]:=Reg[2] << 10
srl $1,$2,10 Reg[1]:=Reg[2] >> 10
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Register Transfer Level (RTL)At this level, we model all the components at the
register-transfer level, includingarithmetic/logic units (ALUs),
registers,
memories,
muxes and
decoders.
Models at this level are always cycle-true.
Automatic synthesis from such models is not a major challenge.
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Register transfer level: (MIPS)
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Gate-level ModelsModels contain gates as the basic componentsProvide accurate information about signal
transition probabilities and can therefore also be used for power estimations.
Delay calculations can be more precise than for the RTL. Typically no information about the length of wires (still estimates).
Term sometimes also used to denote Boolean functions (No physical gates; only considering the behavior of the gates). Such models should be called “Boolean function models”.
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Gate-level Models: Example
Source: http://geda.seul.org/screenshots/screenshot-schem2.png
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Switch Level Models
Switch level models use switches (transistors) as their basic components.
Switch level models use digital value models.In contrast to gate-level models, switch level
models are capable of reflecting bidirectional transfer of information.
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Switch Level Model: Example
Source: http://vada1.skku.ac.kr/ClassInfo/ic/vlsicad/chap-10.pdf
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Circuit Level Models: ExampleModels circuit theory and its components (current
and voltage sources, resistors, capacitances, inductances and possibly macro-models of semiconductors) form the basis of simulations.
Simulations involve partial differential equations. Linear if and only if the behavior of semiconductors is
linearized.Ideal MOSFET
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Circuit Level Models: SPICE
The most frequently used simulator at this level is SPICE [Vladimirescu, 1987] and its variants.
Example:
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Device Level
Simulation of a single device (such as a transistor).Example (SPICE simulation [IMEC]):
Measured and simulated currents
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Layout ModelsReflects the actual circuit layout, includes
geometric information,
Cannot be simulated directly: behavior can be deduced by correlating the layout model with a behavioral description at a higher level or by extracting circuits from the layout.
Length of wires and capacitances frequently extracted from the layout, back-annotated to descriptions at higher levels (more precision for delay and power estimations).
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Layout Models: Example
din
powlo
powhi
dout
© Mosis (http://www. mosis.org/Technical/Designsupport/polyflowC.html);Tool: Cadence
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Process ModelsModel of fabrication process; Example [IMEC]: Doping as a function of the distance from the surface
Simulated
Measured
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135
OutlineOutline Introduction Models of Computation Specification Languages
State Charts SDL Petri Nets UML, MSC VHDL, Verilog SpecC, SystemC, SystemVerilog
Levels of Hardware Modeling Conclusion
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Language Comparison
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Language Problems in Practice
Mixed Approaches: