Microprocessors & ApplicationsInstructor: Shaftab Ahmed

Module 8051 Microcontroller

Bahria University Islamabad CampusDepartment of Computer Science & Engineering

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Microcontroller 8051

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CPU Organization

CISC Machine

Registers

PSW PROGRAM STATUS WORD 8 BIT

A ACCUMULATOR 8 BIT

B EXTENSION REGISTER 8 BIT

SP STACK POINTER 8 BIT

DPTR DATA POINTER REGISTER 16 BIT

SFRs SPECIAL FUNCTION REGISTERS 8 BIT

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Features of 8051 Microcontroller

40 Pin Package

Clock Frequency 12 MHz (11.0592 MHz)Cycle Time 1MHzData word length 8 bitsInstruction word length 16 bits

ROM - 4k bytes (set at factory per user spec.)RAM - 128 bytes on chipAdd limit - 64KI/O lines - 32 (P0, P1, P2, P3)Timers - 2 x 16-bit, work in various modesInterrupt - 5 sources (2 External, 3 Internal)Serial - 1 duplex serial portBit Add. - 210 bit addressable locations

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8051 Control Pins Description

VPP /EA External Address enable. When tied to +5V internal program execution is

enabled. If tied to Low the program executes from external memory and

the \PSEN signal is used

/PSEN Program Strobe Enable to read code from external memory

ALE /PROG Address Latch Enable

RST Master Reset which should remain high for at least 2 machine cycles

I/O port specs Port1,2 support 4 TTL loads and Port 3 supports 3 TTL loads

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Block Diagram of 8051

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Data Flow and Internal structure of 8051

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Ports and Pin Description

Port 0 Dual purpose port i.e.

General purpose 8 bit I/O

Eight bit bus A/D multiplexed bus for memory addressing

Port 1 Dedicated I/O port solely used for I/O interfacing

Port 2 Dual purpose port i.e.

General purpose 8 bit I/O

High address lines A8 to A15

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Ports and Pin Description

Port 3 Dual purpose port i.e.Eight bit I/O OR Various functions to support serial I/O and control

P3.0 -- RxD Receive serial dataP3.1 -- TxD Transmit DataP3.2 -- INTO External interrupt 0P3. 3 -- INT1 External interrupt 1P3.4 -- T0 Timer / counter 0 External inputP3.5 -- T1 Timer / counter 1 External inputP3.6 -- \WR Ext data memory write strobeP3.7 -- \RD Ext data memory read strobe

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Memory organization

80C51 supports Harvard memory architecture i.e. separate address spaces for program and data each of 64KB

Program Space

Lower 4KB Program space is on the chip for ROM versions and /RD signal is used to access it

For the 64KB ROM space outside the chip /EA signal is used with /PSEN

Data Space

RAM occupies 64KB space out of which 128 Bytes are on the chip. The /RD and /WR signals are used to interact with data space

Memory locations can be accessed using Direct and Indirect modes

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8051 Memory Structure

EA=0

/PSEN

EA=1

0FFF

FFFF

Data MemoryProgram Memory

FF

00/RD /WR

FFFF

0000

00

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INTERNAL DATA MEMORY

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Program Memory – Interrupt Vectors

0003H EXT INT 0

000BH TIMER 0

0013H EXT INT 1

001B TIMER 1

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RAM Address Space

Four Register Banks (00H to 1FH) Bit Addressable RAM

128 general purpose bit addressable locations in the range 20H to 2FH. They can be set / Reset / ORed / ANDed under software control

General purpose RAM on the chip is 80 bytes 30H to 7Fh

Special Function Registers 80H to FFH

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Registers and SFR

4 Register Banks00 to 1FH

20-2F or 16x8 = 128 Bits

The range of Ram address 80 to FF is used by Special function registers

30-7F or 80 Bytes General RAM

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SFR Memory Map

Assignment

Make a table describing all the registers of 8051 i.e. CPU, Register Banks and Special Funtion Registers

Submission Next Class

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Register Banks

8051 has four Register banks selectable by two bits (3,4) in PSW register

When the 8051 is first booted up, Register bank 0 (addresses 00h through 07h) is used by default.

The 8051 instructions use 8 "R" registers. They are numbered from R0 through R7.

The internal memory supports 4 register banks i.e.

The first 8 bytes (00h - 07h) are "register bank 0". Followed by Bank1 (08 – 0F), Bank2 (10 – 17), Bank3 (18 – 1F)

The concept of register banks adds a great level of flexibility to the 8051, especially when dealing with interrupts.

However, always remember that the register banks really reside in the first 32 bytes of Internal RAM.

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General purpose RAM

The 80 bytes address 30 to 7F of Internal RAM, may be used by user variables that need to be accessed frequently or at high-speed.

This area is also utilized by the microcontroller as a storage area for the operating stack.

This fact severely limits the 8051’s stack. As illustrated in the memory map, the area reserved for the stack is only 80 bytes which is quite small because it has to be shared between the stack and user variables.

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External ROM / EPROM

Note:

For External EPROM EA is tied to Low

For Internal EPROM EA is tied to High

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External Data Memory