1 routing and resilience in future optical broadband telecommunications networks 21 st january 2004...
DESCRIPTION
3 2x2 Optical Buffered Switch Cells are queued using optical buffer Series of 2x2 optical switches and fibre delay lines Logarithmic scalability – discrete buffer lengths Emulates a 2x2 switch with non-optimal delayTRANSCRIPT
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Routing and Resilience in Future Optical Broadband Telecommunications Networks
21st January 2004
Andrew S. T. LeeSupervisor: Dr. David Harle
Broadband and Optical Networks Research GroupDept. of Electronic and Electrical Engineering
University of Strathclyde, Glasgow, UK
2
Introduction
All-optical physical layer using Optical Packet Switching
Synchronous operation at 100 Gbit/s
Higher layer Ethernet frames or IP packets are mapped onto multiple optical cells
IP / Ethernet IP / Ethernet
Transmitter Receiver
ConvergenceSublayer
ConvergenceSublayer
Segmentationand Reassembly(SAR) Sublayer
Segmentationand Reassembly(SAR) Sublayer
ELECTRONIC CLIENT LAYERS
AdaptationLayer
OPTICAL PACKET-SWITCHED LAYER
3
2x2 Optical Buffered Switch
Cells are queued using optical buffer Series of 2x2 optical switches and fibre delay lines Logarithmic scalability – discrete buffer lengths Emulates a 2x2 switch with non-optimal delay
2x2SW
n/221
.............
4
1log 2 n switches & delay linesB(n): chain ofmn 2,...,8,4,2,1
U
U
U
L
L
L
upperinput
lowerinput
upperoutput
loweroutput
lowerqueue
upperqueue
NL,2L, 2L
2U
UU,L2U, UU,L NL,U,U,L L,2LU,L
NU,2U,
2n
1n2n12
n10
NL,2L, NL,2L,
NU,2U, NU,2U,
NL,U,U,L
2U2U2U
2L2L2L
LU,L
4
Physical Implementation
Buffer Control
nintegratio SiSiO usingon wafer linedelay spiral 2
MMI couplers
Amplifiers
Modulators
Q Q Q Q Q QQ Q
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Synchronization, Control and Header Modification
Synchronizer
LocalClock
Routing ProcessorBuffer Scheduler
SynchronizerControl
BufferControl
2x2 SharedBuffer SwitchTap
hop_count_UI/LIdefl_count_UI/LIdest_UI/LI
hop_count_UO/LOdefl_count_UO/LO
UI
LILO
UO
HeaderRecovery
O/E
HeaderModification
E/O
HeaderUpdate
Electronic Control
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Self-Routing Networks
Each switch makes a fixed routing decision based on packet destination and other header information
Queue contention is resolved using deflection routing (different arbitration heuristics)
Ring(BS)1 2 3 4
1I
2I 2O
1OGB1 GB2Header Payload
1ns100 bit
0.32ns32 bit
1ns100 bit
3.45ns344 bit
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Self-Healing Ring Architecture
Protection against node and link failures using additional switches
8
4-Switch Cyclic Node Design
Drop(BS)
RingUpper(BS)
RingLower(BS)
Add(A3/4)
1I
2I2O
1O
1I
2I2O
1O1I
2I2O
1O
1I
2I 2O
1O
Intra-nodal system and diverse routing reduces network congestion
Improved network scalability and operation for higher loads
9
Traffic Studies
Metrics – buffer depth, packet loss probability, end-to-end delay, ring size, etc.
Bernoulli traffic (results shown) Used to contrast different network topologies
Bursty traffic models Ethernet/IP frames are carried over the network Impact on packet reordering and sequence
integrity Interconnected rings
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Packet Loss Probability
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90
Source Load
Pack
et L
oss
Prob
abili
ty
1fiber-1sw 1fiber-2-linear 1fiber-3-linear1fiber-3-cycle 2fiber-2-ardr 2fiber-2-alt2fiber-3sw -uni 2fiber-3sw -bi 2fiber-4sw -type1-uni2fiber-4sw -type1-bi 2fiber-4sw -type2
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End-To-End Delay
0
20
40
60
80
100
120
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60
Source Load
End-
To-E
nd D
elay
1fiber-1sw1fiber-2-linear1fiber-3-linear1fiber-3-cycle2fiber-2-ardr2fiber-2-alt2fiber-3sw -uni2fiber-3sw -bi2fiber-4sw -type1-uni2fiber-4sw -type1-bi2fiber-4sw -type2 tw o-fiber, unidirectional
tw o-fiber, bidirectionalsingle-f iber, unidirectional
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Conclusions
Multi-switch, bidirectional ring architectures offer best performance at modest buffering
Practical node implementation feasible with current technologies High-speed local area and metropolitan area
networks High performance computing backbone
Possible extensions Multi-wavelength networks using additional
componentry, i.e. aggregate of > 1 Tbps Mesh topologies – control and routing issues