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TDC ArchitecturesTDC ArchitecturesTDC ArchitecturesTDC Architectures

Problem: measure ∆T between 2 signals with

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Problem: measure ∆T between 2 signals with sufficient resolution

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Various solution proposed (and implemented), depending on resolution

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Detector STARTTemporaldiscriminator

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TDC 267.83 nsTDisplay

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Temporal discriminatorDetector STOP

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Time to Amplitude (TAC)Time to Amplitude (TAC)Time to Amplitude (TAC)Time to Amplitude (TAC) Convert time period

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Convert time periodto voltage andthen use an ADC

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lo20 then use an ADC Simple,

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Digital measurementsDigital measurementsDigital measurementsDigital measurements

A clock is needed but start and stop are

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A clock is needed, but start and stop are asynchronous!

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Simple digital counterSimple digital counterSimple digital counterSimple digital counter Easy idea

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Easy idea Resolution limited by toggling frequency

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Power increases with frequency Used only for low resolution (few ns)

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y ( ) Gray code used for async inputs

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START CLEAR

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COUNTERCLOCK

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STOP

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Improvement: use multi phase clockImprovement: use multi phase clockImprovement: use multi phase clockImprovement: use multi phase clock

In addition to the preceding counter using

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In addition to the preceding counter using multiphase can be useful to identify the

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Improved characteristic

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Tapped Delay LineTapped Delay LineTapped Delay LineTapped Delay Line

Having a delay element we can explore inside

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Having a delay element, we can explore inside the clock period

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Limitation: linearity, delay vs. time, T, ºC Calibration needed

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Delay line based TDC block diagramDelay line based TDC block diagramDelay line based TDC block diagramDelay line based TDC block diagram01

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ImplementationImplementationImplementationImplementation All these architecture can be implemented in

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All these architecture can be implemented in FPGA, with resolution down to 10-20 psM i f i hi h l ti i it

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implemented with delay lines

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Implementation results strongly depends on FPGA vendor and family. Big effort needed to

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DC lock resources to be used as expected

VLSI ASIC implementation gives usually better

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performances, but higher cost and longer development time (years)

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HPTDC @CERN (2004)HPTDC @CERN (2004)HPTDC @CERN (2004)HPTDC @CERN (2004)

32 channels

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32 channels 100 ps bin

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40 MHz clock Multihit

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DC for delay line

calibration

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