1

Timing Analysis - Delay Timing Analysis - Delay Analysis ModelsAnalysis Models

• Simple model 1:Simple model 1:

AAkk = arrival time = max( = arrival time = max(AA11,A,A22,A,A33) + ) + DDkk

DDkk is the delay at node is the delay at node kk, parameterized according to , parameterized according to function function ffkk and fanout node and fanout node kk

• Simple model 2:Simple model 2:

DDkk

A1A1A2A2

A3A3

AkAk

A1A1A2A2

A3A3

AkAk 00

A1A1 A2A2 A3A3

AkAk

DDk1k1 DDk2k2DDk3k3

• Can also have different times for Can also have different times for riserise time and time and fallfall time time

AAkk = max{A = max{A11+D+Dk1k1, ,

AA22+D+Dk2k2,A,A33+D+Dk3k3}}

2

Static delay analysisStatic delay analysis

• Levelize Nodes:Levelize Nodes:/* level of PI nodes initialized to 0, /* level of PI nodes initialized to 0, the others are set to -1. the others are set to -1. Invoke LEVEL from PO */Invoke LEVEL from PO */

LEVEL(k)LEVEL(k)if( if( kk.level != -1).level != -1)

return(return(kk.level).level)elseelse

kk.level = 1+max{LEVEL(.level = 1+max{LEVEL(kkii)|)|kkii fanin( fanin(kk)})}return(return(kk.level).level)

• Compute arrival times:Compute arrival times:/* Given arrival times on PI’s *//* Given arrival times on PI’s */for L = 0 to MAXLEVELfor L = 0 to MAXLEVELfor {for {kk||k.level = Lk.level = L}}

AAkk = max{ = max{AAkiki} + } + DDkk

3

Required timesRequired times

Required times:Required times:

given required times on primary outputsgiven required times on primary outputs

1.1. Traverse in reverse topological order Traverse in reverse topological order (i.e. from (i.e. from primary outputs to primary inputs)primary outputs to primary inputs)

2.2. if (if (kki i , k , k ) is an edge between ) is an edge between kkii and and kk, , RRkki i ,,k k = = RRk k - D- Dk k (this is the edge required time)(this is the edge required time)

3.3. Hence, the required time of output of node k is Hence, the required time of output of node k is RRk k = min ( = min ( RRk,kk,kjj

| | kkjj fanout( fanout(kk) )) )

4

Propagating SlacksPropagating Slacks

Slacks:Slacks: slack at the output node slack at the output node kk is is SSk k = R= Rkk-A-Akk

Since Since RRkiki,,kk==RRkk-D-Dkk

SSkiki,,k k ==RRkiki,,k k - A- Akiki

SSkiki,,k k + A+ Aki ki = = RRkk-D-Dkk = = SSk k + A+ Ak k - D- Dkk

Since ASince Akk = max { = max {AAkj kj } + } + DDkk

SSkiki,,k k = S= Skk + + max {max {AAkj kj } } - A- Akiki k kj j , k, kii fanin ( fanin (k k ))

SSki ki = = min{min{SSkiki,,jj}} j j fanout ( fanout (kki i ))

Notes:Notes:

1.1. each edge is the graph has a slack and a required timeeach edge is the graph has a slack and a required time

2.2. Negative slack is bad.Negative slack is bad.

kk

kkii

jj

SSkiki

SSkk SSjj

kkii

5

Sequential networksSequential networks

• Arrival times known at Arrival times known at ll11 and and ll22• Required times known at Required times known at ll33, , ll44, and , and ll55• Delay analysis gives arrival and required times Delay analysis gives arrival and required times

(hence slacks)(hence slacks) for for CC11, , CC22, , CC33, C, C44

C3C3

C1C1C2C2

C4C4

l1l1

l2l2 l3l3

l4l4

l5l5

6

Sequential NetworksSequential Networks

NoteNote: Latch : Latch ll55 may be transparent may be transparent

• tt11 is the beginning of latch is the beginning of latch transparenttransparent time time

• Arrival time at Arrival time at ll55 output = output =

max { arrival time at max { arrival time at ll55 input, input, tt11 } + D} + Dlatchlatch(hold)(hold)

• Required time at Required time at ll55 input = input =

min { required time at min { required time at ll5 5 output, output, tt22 } - } - DDlatchlatch(set_up)(set_up)

tt22tt11

C3C3

C1C1C2C2

C4C4

l1l1

l2l2 l3l3

l4l4

l5l5

clockclock

7

Static critical pathsStatic critical paths

Min-Max problem:Min-Max problem: minimize max{- minimize max{-SSi i , 0}, 0}

A A static critical pathstatic critical path of a Boolean network is a of a Boolean network is a path P = {path P = {ii11,i,i22,…,i,…,ip p } where S} where Siikk

, , iik+1k+1 < 0 < 0

Note:Note: if a node if a node k k is on a static critical path, then at is on a static critical path, then at least one of the fanin edges of least one of the fanin edges of kk is critical. is critical. Hence, all critical paths reach from an input to Hence, all critical paths reach from an input to an output.an output.

Note:Note: There may be several critical paths There may be several critical paths

8

Example: Static critical Example: Static critical pathspaths

22 11

22 22 11

2211

R2=5R2=5R1=5R1=5

A8=0A8=0 A9=0A9=0

998800

0011

00-1-1

-1-1-1-1

-1-11100

-1-1

-1-1

55

7766

33

11 22

44

A1=6 R1=5A2=5 R2=5

S1=-1 R3=3S2=0 R7=1S3,1=-1 R9=-1S4,1 = -1S4,2 = 0S5,2 = 1S6,3 = 0S7,3 = -1S7,4 = -1S7,5 = 1S8,6 = 0S9,7 = -1

critical path edges

Ski,k = Sk + max{Akj } - Aki , kj,ki fanin(k)Sk = Sk + min{Ski,k }, kj fanout(k)

11

44

22

3344

5566

9

Timing analysis problemsTiming analysis problems

We want to determine the We want to determine the truetrue critical paths of a critical paths of a circuit in order to:circuit in order to:1.1. determine the minimum cycle time that the circuit determine the minimum cycle time that the circuit

will functionwill function

2.2. identify critical paths from performance optimization - identify critical paths from performance optimization - don’t want to try to optimize the don’t want to try to optimize the wrongwrong (non-critical) (non-critical) pathspaths

Implications:Implications:– Don’t want Don’t want false pathsfalse paths (produced by static delay (produced by static delay

analysis)analysis)– Delay model is Delay model is worstworst case model. Need to ensure case model. Need to ensure

correctness for case where icorrectness for case where ithth gate delay gate delay D DiiMM

Functional Timing AnalysisFunctional Timing Analysis- How to Detect False - How to Detect False

PathsPathsWhat is Timing Analysis?What is Timing Analysis?

Estimate when the output of a given circuit gets Estimate when the output of a given circuit gets stablestable

The output needs to be stable by t=Tfor the correct functionality

clock

CombinationalCombinationalblockblock

00

00

T0

11

Why Timing Analysis?Why Timing Analysis?

Timing verificationTiming verification– Verifies whether a design Verifies whether a design meetsmeets a given timing a given timing

constraintconstraint• Example:Example: cycle-time constraint cycle-time constraint

Timing optimizationTiming optimization– Needs to identify Needs to identify criticalcritical portion of a design for portion of a design for

further optimizationfurther optimization• Critical path identificationCritical path identification

In both applications, the more In both applications, the more accurateaccurate, the , the betterbetter

12

Timing Analysis - BasicsTiming Analysis - BasicsNaïve approachNaïve approach - Simulate all input vectors with - Simulate all input vectors with

SPICESPICE– Accurate, but too expensiveAccurate, but too expensive

Gate-levelGate-level timing analysis timing analysis

Focus of this lectureFocus of this lecture– Less accurate than SPICE due to the level of abstraction, Less accurate than SPICE due to the level of abstraction,

but much more but much more efficientefficient– Scenario:Scenario:

• Gate/wire delays are Gate/wire delays are pre-characterizedpre-characterized (accuracy (accuracy loss)loss)

• Perform timing analysis of a gate-level circuit Perform timing analysis of a gate-level circuit assuming the assuming the gate/wire delaysgate/wire delays

Gate-level Timing AnalysisGate-level Timing AnalysisA naive approach is topological A naive approach is topological

analysisanalysis– Easy longest-path problemEasy longest-path problem– Linear in the size of a networkLinear in the size of a network

Not all paths can propagate signal Not all paths can propagate signal eventsevents– False pathsFalse paths– If all longest paths are false, If all longest paths are false,

topological analysis gives delay topological analysis gives delay overestimateoverestimate

Functional timing analysisFunctional timing analysis = = false-false-path-awarepath-aware timing analysis timing analysis– Compute false-path-aware arrival Compute false-path-aware arrival

timetime

arr(x1)=0 arr(x2)=0

False path aware

arr(z)?z

x1 x2

1

1

Example: 2-bit Carry-skip Example: 2-bit Carry-skip AdderAdder

c_in

a0

b0

a1

b1

s0

s1

c_out

muxmux

Length 5Length 5Length 1Length 1

ripple carry adderripple carry adder

10

15

End of lecture 19End of lecture 19

16

False Path Analysis - False Path Analysis - BasicsBasics

Is a path Is a path responsibleresponsible for delay? for delay?– If the answer is no, can If the answer is no, can ignoreignore the path for delay the path for delay

computationcomputation

Check the falsity of long paths until we find the Check the falsity of long paths until we find the longest true pathlongest true path– How can we determine whether a How can we determine whether a path is falsepath is false??

Delay underestimation is Delay underestimation is unacceptableunacceptable– Can lead to overlooking a timing Can lead to overlooking a timing violationviolation

Delay overestimation is not desirable, but Delay overestimation is not desirable, but acceptableacceptable– TopologicalTopological analysis can give overestimate, but never give analysis can give overestimate, but never give

underestimateunderestimate

17

Controlling/Non-Controlling/Non-Controlling ValuesControlling Values

0 0 1

Controlling value of AND

Controlled value of AND

1 1

Controlling value of OR

Controlled value of OR

Non-Controlling value of AND

0

Non-Controlling value of OR

18

Static SensitizationStatic SensitizationA path is A path is statically-sensitizablestatically-sensitizable if there exists an if there exists an

input vector such that all the side inputs to the input vector such that all the side inputs to the path are set to non-controlling valuespath are set to non-controlling values– This is This is independentindependent of gate delays of gate delays

10

Controlling value!

These paths are These paths are notnotstatically-sensitizablestatically-sensitizable

The longest The longest truetrue path pathis of length 2?is of length 2?

t=0

t=0

t=0

10

19

Static SensitizationStatic Sensitization

• The The (dashed)(dashed) path is responsible for delay! path is responsible for delay!• Delay Delay underestimationunderestimation by static sensitization by static sensitization

(delay = 2 when true delay = 3)(delay = 2 when true delay = 3)– incorrectincorrect condition condition

1

0

01

2

1

2 3

00

20

What is Wrong with Static What is Wrong with Static Sensitization?Sensitization?

The idea of forcing non-controlling values The idea of forcing non-controlling values to side inputs is okay, to side inputs is okay, butbut timing was timing was ignoredignored– The same signal can have a The same signal can have a controllingcontrolling value value

at one time and a at one time and a non-controllingnon-controlling value at value at another time.another time.

How about How about timing simulationtiming simulation as a correct as a correct method?method?

21

Timing SimulationTiming Simulation

22

11

44

11

11

0

0

2

1

4

2 3

Implies that delay = 0 for these inputsImplies that delay = 0 for these inputsBUT!BUT!

22

22

11

4->4->22

11

11

Timing SimulationTiming Simulation

0

0 2

2

1

2 3

3 4

Implies that delay = 4 with the same set of Implies that delay = 4 with the same set of inputs.inputs.

23

What is Wrong with Timing What is Wrong with Timing Simulation?Simulation?

If gate delays are If gate delays are reducedreduced, delay , delay estimates can estimates can increaseincrease

NotNot acceptable since acceptable since– Gate delays are just Gate delays are just upper-boundsupper-bounds

• Delay Delay uncertaintyuncertainty due to manufacturing due to manufacturing– We are implicitly analyzing a We are implicitly analyzing a familyfamily of of

circuits where gate delays are circuits where gate delays are withinwithin the the upper-boundsupper-bounds

24

Monotone Speedup Monotone Speedup PropertyProperty

DefinitionDefinition:: For any circuit C, if For any circuit C, if – C’ is obtained from C by reducing some gate C’ is obtained from C by reducing some gate

delays, anddelays, and– delay_estimate(C’) delay_estimate(C’) delay_estimate(C) delay_estimate(C),,

then then delay_estimatedelay_estimate has has Monotone SpeedupMonotone Speedup propertyproperty

Timing simulation does Timing simulation does notnot have this property have this property

25

Timing Simulation Timing Simulation RevisitedRevisited

2

1

4

1

1

0

0

2

1

4

3

4

4

means that the rising signalmeans that the rising signaloccurs anywhere between occurs anywhere between t = -infinity and t = 4.t = -infinity and t = 4.

X-valued simulationX-valued simulation

Timing Simulation Timing Simulation RevisitedRevisited

Timed 3-valued Timed 3-valued (0,1,X)(0,1,X) simulation simulation– called X-valued simulationcalled X-valued simulation

Monotone speedup property is Monotone speedup property is satisfied.satisfied.

Underlying model of Underlying model of • floating mode conditionfloating mode condition [Chen, Du] [Chen, Du]

– Applies to “simple gate” networks only Applies to “simple gate” networks only

• viabilityviability [McGeer, Brayton][McGeer, Brayton]– Applies to general Boolean networksApplies to general Boolean networks

27

Floating Mode AnalysisFloating Mode AnalysisAssume that all nodes have Assume that all nodes have XX before applying an before applying an

input vectorinput vector– conservative assumptionconservative assumption

Path sensitization Path sensitization (floating-mode - (floating-mode - for simple for simple gate networks only)gate networks only)

0 0For final controlled output value

1

Earliest-arriving controlling valuedetermines the output stable time

late

early

1

11For final non-controlled output value

Latest-arriving non-controlling valuedetermines the output stable time

early

late

False Path Analysis False Path Analysis AlgorithmsAlgorithms

Checking the falsity of Checking the falsity of everyevery path explicitly is too expensive - path explicitly is too expensive - exponential # of pathsexponential # of paths

State-of-the-art approach:State-of-the-art approach:1.1. StartStart: set L = L: set L = Ltoptop - - = topological longest path delay - = topological longest path delay - LLoldold = =

00

2.2. Binary search:Binary search:

If (Delay(L)) If (Delay(L)) ((**))

L = (L-LL = (L-Loldold)/2, L)/2, Loldold = L, L = L + = L, L = L + LL

Else, Else, L = (L-LL = (L-Loldold)/2, L)/2, Loldold = L, L = L - = L, L = L - LL

If If (L > L(L > Ltop top or or L < threshold),L < threshold), L = L L = Loldold , done , done

((**)) Delay(L) = 1 if Delay(L) = 1 if there an input vector under which an output gets stable there an input vector under which an output gets stable

only at time only at time tt where L where L t t ?? Can be reduced toCan be reduced to– a SAT problem a SAT problem [McGeer, Saldanha, Brayton, ASV][McGeer, Saldanha, Brayton, ASV] or or – a timed-ATPG a timed-ATPG [Devadas, Keutzer, Malik][Devadas, Keutzer, Malik]

29

SAT-based False Path SAT-based False Path AnalysisAnalysis

Decision problem:Decision problem:Is there an input vector under which the output gets stable only Is there an input vector under which the output gets stable only

after t = T ?after t = T ?

Idea:Idea:

1.1. characterize the set of all input vectors characterize the set of all input vectors S(T)S(T) that make that make the output stable no later than t = Tthe output stable no later than t = T

2.2. check if check if S(T)S(T) contains contains SS = all possible input vectors = all possible input vectors This check is solved as a SAT problem:This check is solved as a SAT problem:

Is S \ S(T) empty? - set difference + emptiness checkIs S \ S(T) empty? - set difference + emptiness check• Let F and F(T) be the characteristic functions of S and S(T)Let F and F(T) be the characteristic functions of S and S(T)• Is F !F(T) satisfiable?Is F !F(T) satisfiable?

30

ExampleExample

Assume all the PIs arrive at t = 0, all gate delays = 1Assume all the PIs arrive at t = 0, all gate delays = 1Is the output stable time t > 2?Is the output stable time t > 2?

aa

bb

cc

dd

ee ff

gg

31

ExampleExample g(1,t=2) : the set of input vectors under which g gets stable to value = 1 no later than t =2

aa

bb

cc

dd

ee ff

gg

g(1,t=2) = d(1,t=1) f(1,t=1)

g(1,t=) = onset = !a!bc = g(1,t=2) = S1

Onset:Onset:stabilized by t=2?stabilized by t=2?

= (a(0,t=0) b(0,t=0)) (c(1,t=0) e(1,t=0))= !a!b(c ) = !a!bc = S1(t=2)

32

ExampleExample g(g(00,t=2) : the set of input vectors under which,t=2) : the set of input vectors under which g gets stable to value = g gets stable to value = 00 no later than t=2 no later than t=2

aa

bb

cc

dd

ee ff

gg

g(0,t=2) = d(0,t=1) g(0,t=2) = d(0,t=1) f(0,t=1) f(0,t=1) = (a(1,t=0) = (a(1,t=0) b(1,t=0)) b(1,t=0)) (c(0,t=0) (c(0,t=0) e(0,t=0)) e(0,t=0)) = (a+b) + (!c = (a+b) + (!c ) = ) = a+ba+b = S = S00(t=2)(t=2) g(0,t=g(0,t=) = offset = ) = offset = a+b+!ca+b+!c = S = S00

33

ExampleExample g(g(00,t=2) : the set of input vectors under which,t=2) : the set of input vectors under which g gets stable to g gets stable to 00 no later than t=2 no later than t=2

aa

bb

cc

dd

ee ff

gg

g(0,t=2) = g(0,t=2) = a+ba+b

g(0,t=g(0,t=) = offset = ) = offset = a+b+!ca+b+!c

Offset:NOTstabilized by t=2under abc=000

g(0,t=g(0,t=) \ g(0,t=2) = (a+b+!c) !(a+b) = ) \ g(0,t=2) = (a+b+!c) !(a+b) = !a !b !c!a !b !c = = satisfiablesatisfiable

34

For general networksFor general networksCan build a Can build a companioncompanion network to represent each network to represent each

output: output: output(output(00,t=T’) or output(1,t=T’),t=T’) or output(1,t=T’)

Take each gate g from outputs in reverse topological Take each gate g from outputs in reverse topological order. For g(1,t=T):order. For g(1,t=T):1.1. Compute all primes of gate onsetCompute all primes of gate onset

2.2. Make AND gate for each primeMake AND gate for each prime

3.3. OR these together to form g(1,t=T)OR these together to form g(1,t=T)

For g(0,t=T), do same but for offsetFor g(0,t=T), do same but for offset

For inputs to these primes, form companion networks For inputs to these primes, form companion networks for {ffor {fii(1,t = T-D(1,t = T-Dgg), f), fii(0,t = T-D(0,t = T-Dgg), i in FI(g)}), i in FI(g)}

pp11

pp22 ++pp33

g(1,T)g(1,T)ffii(1,T-D(1,T-Dgg))

ffjj(0,T-D(0,T-Dgg))

Now form SATNow form SATclauses for thisclauses for thisnetwork andnetwork andsolvesolve

35

SummarySummary

False-path-aware arrival time analysis is False-path-aware arrival time analysis is well-well-understoodunderstood– PracticalPractical algorithms exist algorithms exist

• Can handle industrial circuits easilyCan handle industrial circuits easily

Remaining problemsRemaining problems– IncrementalIncremental analysis analysis (make it so that a small (make it so that a small

change in the circuit does not make the analysis change in the circuit does not make the analysis start all over)start all over)

– Integration with logic Integration with logic optimizationoptimization– DSM issues such as DSM issues such as cross-talk-awarecross-talk-aware false path false path

analysisanalysis