10 november 2010silicon pixel tracker – chris damerell 1 the silicon pixel tracker – beginning...
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10 November 2010Silicon Pixel Tracker Chris Damerell 1 The Silicon Pixel Tracker beginning of a revolution? Chris Damerell (RAL) SPT concept was first presented by Konstantin Stefanov in March 2008. He was made redundant by STFC shortly afterwards, but internationally, interest in the SPT has grown steadily, not only for the linear collider. CONTENTS Design concept Mechanical simulations by Steve Watson at RAL establish the robustness of a simple non-demountable design Feasibility new results with advanced CMOS pixels from Jim Janesick (California) and Dave Burt (e2V and Open U), working with Jazz/Tower Semiconductors respectively Next steps - performance simulations Norm Graf at SLAC and maybe others Practical realization for LC and other applications Slide 2 10 November 2010Silicon Pixel Tracker Chris Damerell 2 Design Concept LC as one real-life example (1) Basic goal is to devise a tracker design which significantly reduces the material budget wrt the currently projected leader, the SiD silicon microstrip tracker, which uses the same technology as the LHC GPD trackers [TPC last month dropped out of the material budget competition] Why push to minimise material in tracker? In general, we would like photons to convert in the ECAL not in the tracking system Looking at previous tracking systems, they have all gone to hell in the forward region This has diminished the physics output. Since we dont have any counter-examples, its difficult to quantify Example for LC physics: reconstruction of s in jets could significantly improve B/charm separation (a very general tool) At higher energies, most events have jets in the forward region. A chain is as strong as its weakest link A more transparent tracker may deliver a significant advantage in luminosity factor. Given the cost of operating the machine, a more expensive tracking system may be highly cost-effective Slide 3 10 November 2010Silicon Pixel Tracker Chris Damerell 3 Design Concept LC as one real-life example (2) The largest pixel tracking system in HEP (the SLD vertex detector with 307 Mpixels) used CCDs. High performance CMOS pixels have evolved from this technology, achieving much higher functionality by in-pixel and chip-edge signal processing Basic concept is a separated function design precision timing on every track but not on every point on the track. So we suggest an optimised mix of tracking layers and timing layers. Optimisation to follow from detailed simulations, not yet done. Key requirements are timing at the 10 ns level (for CLIC timing layers; we need only 300 ns for ILC), binary readout and data sparsification (for both timing and tracking layers) Thin monolithic charge-coupled CMOS pixel devices offer a different separated function feature evading the link between charge collection and charge sensing, with enormous advantages as regards power dissipation By working with a monolithic planar architecture (CMOS technology) the systems will be scalable by 2020 to the level of ~40 Gpixels Such system size may by then be achievable with more advanced architectures (eg vertical integration). However, on grounds of simplicity and minimal cost, we believe we have an attractive solution Regarding this design concept, thanks to several LC colleagues for helpful suggestions Slide 4 10 November 2010Silicon Pixel Tracker Chris Damerell 4 Tracking sensor, one of 12,000, 8x8 cm 2, 2.56 Mpixels each 5 tracking endcaps, only one shown Possible layout for the linear collider Timing layers, 3 outer and 1 or 2 inner, 3 cm separation between layers Barrels: SiC foam ladders, linked mechanically to one another along their length Tracking layers: 5 closed cylinders (incl endcaps) ~50 m square pixels ~0.6% X 0 per layer, 3.0% X 0 total, over full polar angle range, plus