10 - sequential circuit

8/22/2019 10 - Sequential Circuit

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ECE DepartmentFaculty of Engineering

University of Santo Tomas


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Consists of a combinational circuit to whichmemory elements are connected to form a

feedback path. Receives binary information from external

inputs together with the present state of thememory elements to determine the binaryvalue at the output terminals.


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Combinational

Circuit

Inputs Outputs

Memory

elements


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A device with two stable states It can maintain a binary state indefinitely until

directed by an input signal to switch states It remains in one of these states until

triggered into the other


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1. RS Flip-flop2. JK Flip-flop

3. D Flip-flop4. T Flip-flop


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NOR Latch

Logic Diagram

Schematic symbol

R

S


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Transition Table of NOR Latch

S R Q(t) Q(t+1)0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 ind

1 1 1 ind

Inputs Previous State Present State


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NOR Latch

Timing Diagram


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NAND Latch


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Transition Table of NAND Latch

S R Q(t) Q(t+1)

0 0 0 ind

0 0 1 ind

0 1 0 0

0 1 1 01 0 0 1

1 0 1 1

1 1 0 0

1 1 1 1



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NAND Latch

Timing Diagram


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Logic Diagram

Schematic symbol


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Transition Table

Input

D

Previous State

Q(t)

Present State

Q(t+1)0 0 0

0 1 0

1 0 1

1 1 1


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Logic Diagram

Schematic symbol


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Transition Table

J K Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 01 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0



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Timing Diagram


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Logic Diagram

Schematic symbol


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Transition Table

Input

T

Previous State

Q(t)

Present State

Q(t+1)0 0 0

0 1 1

1 0 1

1 1 0


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1. Level Clocking output of the flip-flopresponds during the high (or low) level of theclock signala. Positive Level Clocking

b. Negative Level Clocking

2. Edge Triggering the flip-flop produces

output only on the rising (or falling) edge ofthe clock signala. Positive Edge Triggering

b. Negative Edge Triggering


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Positive Level Negative Level


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Positive Edge Negative Edge


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Two external inputs that initiates the

condition or state of the flip-flop


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ACTIVE HIGH PR & CLR ACTIVE LOW PR & CLR


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Propagation Delay Time (tP ) This represents the amount of time it takes for the

output of a gate or flip-flop to change states

Setup Time (tSETUP ) It is the minimum length of time the data bit must be

present before the CLK egde hits

Hold Time (tHOLD ) It is the minimum length of time the data bit must be

present after the CLK edge has struck


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1. The waveform below drive a positive edge-triggered RS flip-flop. If Q is low before time A,

a. At what point does Q becomes a 1?

b. When does Q reset to 0?


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2. The clock of the figure below has a frequency of 1MHz and the flip-flop has a propagation delay timeof 25 ns.

a. What is the period of the clock?b. The frequency of the Q output? Its period?c. How long after the negative clock edge does the Q

output change

10 - sequential circuit

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