105k 250v ceramic

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LTM8023

1

8023fc

LOAD CURRENT (A)

0.01

EFFICIENCY(%)

POWERLOSS(W)

55

50

0.1 1 10

8023 TA01b

65

60

90

80

70

85

75

0.2

0.4

0.6

0.8

0

1.2

1.0

1.8

1.6

1.4

VIN = 12VVOUT = 3.3Vf = 650 kHz

FEATURES

APPLICATIONS

DESCRIPTION

2A, 36V DC/DCModule

The LTM8023 is a complete 2A, DC/DC step-down powersupply. Included in the package are the switching control-ler, power switches, inductor, and all support components.Operating over an input voltage range of 3.6V to 36V, theLTM8023 supports an output voltage range of 0.8V to 10V,and a switching frequency range of 200kHz to 2.4MHz,each set by a single resistor. Only the bulk input and outputfilter capacitors are needed to finish the design.

The low profile package (2.82mm) enables utilization ofunused space on the bottom of PC boards for high density

point of load regulation.The LTM8023 is packaged in a thermally enhanced,compact (11.25mm 9mm) and low profile (2.82mm)over-molded land grid array (LGA) package suitable forautomated assembly by standard surface mount equip-ment. The LTM8023 is RoHS compliant.

5.5VIN to 36VIN, 3.3V/2A DC/DC Module Converter

n Complete Step-Down Switch Mode Power Supplyn Wide Input Voltage Range: 3.6V to 36Vn 2A Output Currentn 0.8V to 10V Output Voltagen Selectable Switching Frequency: 200kHz to 2.4MHzn Current Mode Controln (e4) RoHS Compliant Package With Gold

Pad Finishn Programmable Soft-Startn Tiny, Low Profile (11.25mm 9mm 2.82mm)

Surface Mount LGA Package

n Automotive Battery Regulationn Power for Portable Productsn Distributed Supply Regulationn Industrial Suppliesn Wall Transformer Regulation

Efficiency and Power Loss

VOUTVIN

RUN/SS

*RUNNING VOLTAGE RANGE. PLEASEREFER TO APPLICATIONS INFORMATIONFOR START-UP DETAILS

PGOOD

BIAS

RT

ADJ

LTM8023

154k49.9k

8023 TA01

VOUT3.3V2A

SYNC

VIN*5.5V TO 36V

SELECTABLE

OPERATINGFREQUENCY

2.2F AUX

GND

2.2F

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.Module is a trademark of Linear Technology Corporation.All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

VIN, RUN/SS Voltage .................................................40VADJ, RT, SHARE Voltage .............................................5V

VOUT, AUX .................................................................10VPGOOD, SYNC ..........................................................30VBIAS ..........................................................................16VVIN + BIAS .................................................................56VInternal Operating Temperature(Note 2)..................................................40C to 125CStorage Temperature .............................. 55C to 125CSolder Temperature ............................................... 250C

(Note 1)

BANK 3

BANK 2

BANK 1

HBA D

LGA Package

50-Lead (11.25mm s 9mm s 2.82mm)

TOP VIEW

C

6

7

5

1

2

3

4

E F G

TJMAX = 125C, JA = 24C/WJA DERIVED FROM 6.6cm 5cm PCB WITH 4 LAYERS

WEIGHT = 0.93g(SEE TABLE 3 PIN ASSIGNMENT)

LEAD FREE FINISH PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE (Note 2)

LTM8023EV#PBF LTM8023V 50-Lead (11.25mm 9mm 2.82mm) 40C to 85C

LTM8023IV#PBF LTM8023V 50-Lead (11.25mm 9mm 2.82mm) 40C to 85C

LTM8023MPV#PBF LTM8023MPV 50-Lead (11.25mm 9mm 2.82mm) 55C to 125C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

ORDER INFORMATION

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LTM8023

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The l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25C. VIN = 10V, VRUN/SS = 10V, VBIAS = 3V, RT = 60.4k, COUT = 4.7F unlessotherwise specified.

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. Exposure to any AbsoluteMaximum Rating condition for extended periods may affect devicereliability and lifetime.

Note 2: The LTM8023E is guaranteed to meet performance specificationsfrom 0C to 85C ambient. Specifications over the full 40C to85C ambient operating temperature range are assured by design,characterization and correlation with statistical process controls. TheLTM8023I is guaranteed to meet specifications over the full 40C to 85Cambient operating temperature range. The LTM8023MP is guaranteed to

meet specifications over the full 55C to 125C temperature range. Notethat the maximum internal temperature is determined by specific operatingconditions in conjunction with board layout, the rated package thermalresistance and other environmental factors.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Input DC Voltage l 3.6 36 V

VOUT Output DC Voltage 0A < IOUT 2A, RADJ Open, COUT = 51F (Note 3)0A < IOUT 2A, RADJ = 43.2k, COUT = 51F (Note 3)

0.810

VV

RADJ(MIN) Minimum Allowable RADJ (Note 4) 42.2 k

IOUT Continuous Output DC Current 4 VIN 36, COUT = 51F 0 2 A

IQVIN VIN Quiescent Current VRUN/SS = 0.2V, RT = 174kVBIAS = 3V, Not Switching, RT = 174k (E, I)VBIAS = 3V, Not Switching, RT = 174k (MP)VBIAS = 0V, Not Switching, RT = 174k

l

l

0.1252585

0.560

350120

AAAA

IQBIAS BIAS Quiescent Current VRUN/SS = 0.2V, RT = 174kVBIAS = 3V, Not Switching, RT = 174k (E, I)VBIAS = 3V, Not Switching, RT = 174k (MP)VBIAS = 0V, Not Switching, RT = 174k

l

l

0.0350501

0.51202005

AAAA

VOUT/VOUT Line Regulation 5 VIN 36, IOUT = 1A, VOUT = 3.3V, COUT = 51F 0.1 %VOUT/VOUT Load Regulation VIN = 24V, 0 IOUT 2A, VOUT = 3.3V, COUT = 51F 0.4 %

VOUT(AC_RMS) Output Ripple (RMS) VIN = 24V, IOUT = 2A, VOUT = 3.3V, COUT = 51F 10 mV

fSW Switching Frequency RT = 113k, COUT = 51F 325 kHz

ISC(OUT) Output Short Circuit Current VIN = 36V, VOUT = 0V 2.9 A

VADJ Voltage at ADJ Pin COUT = 51F l 765 790 805 mV

VBIAS(MIN) Minimum BIAS Voltage for ProperOperation

2.3 2.8 V

IADJ Current Out of ADJ Pin ADJ = 1V, COUT = 51F 2 A

IRUN/SS RUN/SS Pin Current VRUN/SS = 2.5V 5 10 A

VIH(RUN/SS) RUN/SS Input High Voltage COUT = 51F 2.5 V

VIL(RUN/SS) RUN/SS Input Low Voltage COUT = 51F 0.2 VVPG(TH) PG Threshold VOUT Rising 730 mV

IPGO PG Leakage VPG = 30V 0.1 1 A

IPGSINK PG Sink Current VPG = 0.4V 200 800 A

VSYNCIL SYNC Input Low Threshold fSYNC = 550kHz, COUT = 51F 0.5 V

VSYNCIH SYNC Input High Threshold fSYNC = 550kHz, COUT = 51F 0.7 V

ISYNCBIAS SYNC Pin Bias Current VSYNC = 0V 0.1 A

Note 3: COUT = 51F is composed of a 4.7F ceramic capacitor in parallelwith a 47F electrolytic.

Note 4: Guaranteed by design.

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OUTPUT CURRENT (mA)

INPUTCURRENT

(mA)

400

0

200

8023 G09

800

600

2000

1800

1400

1200

1600

1000

VOUT = 3.3V

0 500 1000 1500 2000

5VIN12VIN24VIN36VIN

OUTPUT CURRENT (mA)

INPUTCURRENT

(mA)

400

0

200

8023 G08

800

600

1200

1000

VOUT = 5V

0 500 1000 1500 2000

12VIN24VIN36VIN

OUTPUT CURRENT (mA)

INPUTCURRENT

(mA)

400

0

200

8023 G07

800

600

1600

1400

1200

1000

VOUT = 8V

0 500 1000 1500 2000

12VIN24VIN36VIN

OUTPUT CURRENT (A)

0.01 0.1 1

EFFICIENCY(%)

60

50

55

8023 G03

70

65

90

85

80

75

VOUT = 3.3V

5VIN12VIN24VIN36VIN

OUTPUT CURRENT (A)

EFFICIENCY(%)

40

20

30

8023 G01

60

50

100

90

80

70

VOUT = 8V

0.01 0.1 1

12VIN24VIN36VIN

OUTPUT CURRENT (A)

0.01 0.1 1

EFFICIENCY(%)

60

50

55

8023 G02

70

65

90

85

80

75

VOUT = 5V

12VIN24VIN36VIN

TYPICAL PERFORMANCE CHARACTERISTICS

Minimum Required Input Voltagevs Output Voltage

36VIN Start-Up Waveforms(5VOUT)

36VIN Start-Up Waveforms(3.3VOUT)

Input Current vs Output Current Input Current vs Output Current Input Current vs Output Current

Efficiency (8VOUT) Efficiency (5VOUT) Efficiency (3.3VOUT)

OUTPUT VOLTAGE (V)

INPUT

VOLTAGE

(V)

6

2

4

8023 G04

10

8

20

18

16

14

12

IOUT = 2A

OPERATING FREQUENCYAS RECOMMENDED

IN TABLE 1

0 108642

8023 G05

RUN/SS5V/DIV

VIN = 36VIOUT = 2AVBIAS = 3V

50s/DIV

VOUT2V/DIV

IIN0.2A/DIV

8023 G06

VIN = 36VIOUT = 2AVBIAS = 3V

RUN/SS5V/DIV

50s/DIV

VOUT2V/DIV

IIN0.2A/DIV

TA = 25C unless otherwise noted

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LTM8023

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INPUT VOLTAGE (V)

LOADCURRENT(mA)

0

8023 G13

500

2500

2000

1500

1000

0 10 20 30 40

25C40C85C

INPUT VOLTAGE (V)

OUTPUTCURRENT(mA)

2000

1600

1800

8023 G10

2400

2200

3200

3000

2800

2600

0 10 20 30 40

BIAS Current vs Load Current

TYPICAL PERFORMANCE CHARACTERISTICS

Output Short-Circuit Currentvs Input Voltage

LOAD CURRENT (mA)

BIASCURRENT(mA)

10

0

5

8023 G11

20

15

30

25

0 500 1000 1500 2000

3.3VOUT5VOUT8VOUT

TA = 25C unless otherwise noted

Load Currentvs Input Voltage (5VOUT)

Load Currentvs Input Voltage (3.3VOUT)

Maximum Load Currentvs Input Voltage (8VOUT)

INPUT VOLTAGE (V)

LOADCURRENT(mA)

0

8023 G14

500

2500

2000

1500

1000

0 10 20 30 40

25C40C85C

INPUT VOLTAGE (V)

LOADCURRENT(mA)

0

8023 G15

500

2500

2000

1500

1000

0 10 20 30 40

25C40C85C

3.3VOUT Junction Temperaturevs Load

5VOUT Junction Temperaturevs Load

8VOUT Junction Temperaturevs Load

CURRENT (mA)

TEMPERATURERISE(C)

0

8023 G16

5

50

45

40

35

30

25

20

15

10

0 500 1000 1500 2000 2500

12VIN24VIN36VIN

CURRENT (mA)

TEMPERATURERISE(C)

0

8023 G17

60

50

40

30

20

10

0 500 1000 1500 2000 2500

12VIN24VIN36VIN

CURRENT (mA)

TEMPERATURERISE(C)

0

8023 G18

80

50

60

70

40

30

20

10

0 500 1000 1500 2000 2500

16VIN24VIN36VIN

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PIN FUNCTIONS

VIN (Bank 1):The VINpin supplies current to the LTM8023sinternal regulator and to the internal power switch. Thispin must be locally bypassed with an external, low ESR

capacitor of at least 2.2F.

VOUT (Bank 2): Power Output Pins. Apply the output filtercapacitor and the output load between these pins andGND pins.

AUX (Pin F5): Low Current Voltage Source for BIAS. Inmany designs, the BIAS pin is simply connected to VOUT.The VAUX pin is internally connected to VOUT and is placedadjacent to the BIAS pin to ease printed circuit board rout-ing. Although this pin is internally connected to VOUT, doNOT connect this pin to the load. If this pin is not tied to

BIAS, leave it floating.

BIAS (Pin G5): The BIAS pin connects to the internal powerbus. Connect to a power source greater than 2.8V. If theoutput is greater than 2.8V, connect this pin there. If theoutput voltage is less, connect this to a voltage sourcebetween 2.8V and 16V. Also, make sure that BIAS + VINis less than 56V.

RUN/SS (Pin H5): Tie RUN/SS pin to ground to shut downthe LTM8023. Tie to 2.5V or more for normal operation.If the shutdown feature is not used, tie this pin to the VIN

pin. RUN/SS also provides a soft-start function; see theApplications Information section.

GND (Bank 3): Tie these GND pins to a local ground planebelow the LTM8023 and the circuit components. Returnthe feedback divider (RADJ) to this net.

RT (Pin G7): The RT pin is used to program the switchingfrequency of the LTM8023 by connecting a resistor fromthis pin to ground. The Applications Information section of

the data sheet includes a table to determine the resistancevalue based on the desired switching frequency. Minimizecapacitance at this pin.

SHARE (Pin F7): Tie this to the SHARE pin of anotherLTM8023 when paralleling the outputs. Otherwise, donot connect.

SYNC (Pin G6): This is the external clock synchronizationinput. Ground this pin for low ripple Burst Mode operationat low output loads. Tie to a stable voltage source greaterthan 0.7V to disable Burst Mode operation. Do not leave

this pin floating. Tie to a clock source for synchronization.Clock edges should have rise and fall times faster than 1s.See synchronizing section in Applications Information.

PGOOD (Pin H6): The PGOOD pin is the open-collectoroutput of an internal comparator. PG remains low until theADJ pin is within 10% of the final regulation voltage. PGoutput is valid when VIN is above 3.6V and RUN/SS is high.If this function is not used, leave this pin floating.

ADJ (Pin H7): The LTM8023 regulates its ADJ pin to 0.79V.Connect the adjust resistor from this pin to ground. The

value of RADJ is given by the equation RADJ = 394.21/(VOUT 0.79), where RADJ is in k.

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LTM8023

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BLOCK DIAGRAM

VIN

8023 BD

BIAS

AUX

PGOODCURRENT MODECONTROLLER

VOUT

10F4.7pF

4.7H

0.1F

RUN/SS

SHARE

499k

SYNC

RT ADJGND

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OPERATION

The LTM8023 is a stand-alone nonisolated step-downswitching DC/DC power supply. It can deliver up to 2A ofDC output current with only bulk external input and output

capacitors. This module provides a precisely regulatedoutput voltage programmable via one external resistorfrom 0.8VDC to 10VDC. The input voltage range is 3.6Vto 36V. Given that the LTM8023 is a step-down converter,make sure that the input voltage is high enough to supportthe desired output voltage and load current. A simplifiedBlock Diagram is given on the previous page.

The LTM8023 contains a current mode controller, powerswitching element, power inductor, power Schottky diodeand a modest amount of input and output capacitance.

The LTM8023 is a fixed frequency PWM regulator. Theswitching frequency is set by simply connecting theappropriate resistor value from the RT pin to GND.

An internal regulator provides power to the control cir-cuitry. The bias regulator normally draws power from theVIN pin, but if the BIAS pin is connected to an external

voltage higher than 2.8V, bias power will be drawn fromthe external source (typically the regulated output voltage).This improves efficiency. The RUN/SS pin is used to place

the LTM8023 in shutdown, disconnecting the output andreducing the input current to less than 1A.

To further optimize efficiency, the LTM8023 automaticallyswitches to Burst Mode operation in light load situations.Between bursts, all circuitry associated with controlling theoutput switch is shut down reducing the input supply cur-rent to 50A in a typical application. The oscillator reducesthe LTM8023s operating frequency when the voltage at theADJ pin is low. This frequency foldback helps to controlthe output current during start-up and overload.

The LTM8023 contains a power good comparator whichtrips when the ADJ pin is at 92% of its regulated value.The PG output is an open-collector transistor that is offwhen the output is in regulation, allowing an externalresistor to pull the PG pin high. Power good is valid whenthe LTM8023 is enabled and VIN is above 3.6V.

For most applications, the design process is straightforward, summarized as follows:

1. Look at Table 1 and find the row that has the desiredinput range and output voltage.

2. Apply the recommended CIN, COUT, RADJ and RT values.

3. Connect BIAS as indicated.

While these component combinations have been tested forproper operation, it is incumbent upon the user to verifyproper operation over the intended systems line, load and

environmental conditions.

Capacitor Selection Considerations

The CIN and COUT capacitor values in Table 1 are theminimum recommended values for the associated oper-ating conditions. Applying capacitor values below those

indicated in Table 1 is not recommended, and may resultin undesirable operation. Using larger values is generallyacceptable, and can yield improved dynamic response, ifit is necessary. Again, it is incumbent upon the user toverify proper operation over the intended systems line,load and environmental conditions.

Ceramic capacitors are small, robust and have very lowESR. However, not all ceramic capacitors are suitable.X5R and X7R types are stable over temperature and ap-plied voltage and give dependable service. Other types,including Y5V and Z5U have very large temperature andvoltage coefficients of capacitance. In an application cir-cuit they may have only a small fraction of their nominalcapacitance resulting in much higher output voltage ripplethan expected.

APPLICATIONS INFORMATION

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Ceramic capacitors are also piezoelectric. In Burst Modeoperation, the LTM8023s switching frequency dependson the load current, and can excite a ceramic capacitor

at audio frequencies, generating audible noise. Since theLTM8023 operates at a lower current limit during BurstMode operation, the noise is typically very quiet to acasual ear.

If this audible noise is unacceptable, use a high performanceelectrolytic capacitor at the output. The input capacitor canbe a parallel combination of a 2.2F ceramic capacitor anda low cost electrolytic capacitor.

A final precaution regarding ceramic capacitors concernsthe maximum input voltage rating of the LTM8023. A

ceramic input capacitor combined with trace or cableinductance forms a high Q (under damped) tank circuit.If the LTM8023 circuit is plugged into a live supply, theinput voltage can ring to twice its nominal value, possi-bly exceeding the devices rating. This situation is easilyavoided; see the Hot-Plugging Safely section.

Frequency Selection

The LTM8023 uses a constant frequency PWM architecturethat can be programmed to switch from 200kHz to 2.4MHzby using a resistor tied from the R

Tpin to ground. Table 2

provides a list of RT resistor values and their resultantfrequencies.

Table 2. Switching Frequency vs RT Value

SWITCHING FREQUENCY (MHz) RT VALUE (k)

0.20.30.40.50.60.70.80.9

1.01.21.41.61.82.02.22.4

18712188.768.156.246.440.234

29.423.719.116.213.311.59.768.66

Operating Frequency Tradeoffs

It is recommended that the user apply the optimal RT

value given in Table 1 for the input and output operatingcondition. System level or other considerations, however,may necessitate another operating frequency. While theLTM8023 is flexible enough to accommodate a wide rangeof operating frequencies, a haphazardly chosen one mayresult in undesirable operation under certain operating orfault conditions. A frequency that is too high can reduceefficiency, generate excessive heat or even damage theLTM8023 if the output is overloaded or short circuited.A frequency that is too low can result in a final designthat has too much output ripple or too large of an output

capacitor.The maximum frequency (and attendant RT value) at whichthe LTM8023 should be allowed to switch is given in Table 1in the f(MAX) column, while the recommended frequency(and RT value) for optimal efficiency over the given inputcondition is given in the fOPTIMAL column.

There are additional conditions that must be satisfied ifthe synchronization function is used. Please refer to theSynchronization section for details.

BIAS Pin Considerations

The BIAS pin is used to provide drive power for the internalpower switching stage and operate internal circuitry. Forproper operation, it must be powered by at least 2.8V. Ifthe output voltage is programmed to be 2.8V or higher,simply tie BIAS to VOUT. If VOUT is less than 2.8V, BIAScan be tied to VIN or some other voltage source. In allcases, ensure that the maximum voltage at the BIAS pinis both less than 16V and the sum of VIN and BIAS is lessthan 56V. If BIAS power is applied from a remote or noisyvoltage source, it may be necessary to apply a decoupling

capacitor locally to the LTM8023.

Load Sharing

Two or more LTM8023s may be paralleled to produce highercurrents. To do this, tie the VIN, ADJ, VOUT and SHAREpins of all the paralleled LTM8023s together. To ensure

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that paralleled modules start up together, the RUN/SS pinsmay be tied together, as well. If the RUN/SS pins are nottied together, make sure that the same valued soft-start

capacitors are used for each module. An example of twoLTM8023 modules configured for load sharing is given inthe Typical Applications section.

Burst Mode Operation

To enhance efficiency at light loads, the LTM8023 auto-matically switches to Burst Mode operation which keepsthe output capacitor charged to the proper voltage whileminimizing the input quiescent current. During Burst Modeoperation, the LTM8023 delivers single cycle bursts of

current to the output capacitor followed by sleep periodswhere the output power is delivered to the load by the outputcapacitor. In addition, VIN and BIAS quiescent currents arereduced to typically 20A and 50A respectively duringthe sleep time. As the load current decreases towards a noload condition, the percentage of time that the LTM8023operates in sleep mode increases and the average inputcurrent is greatly reduced, resulting in higher efficiency.

Burst Mode operation is enabled by tying SYNC to GND. Todisable Burst Mode operation, tie SYNC to a stable voltageabove 0.7V. Do not leave the SYNC pin floating.

Minimum Input Voltage

The LTM8023 is a step-down converter, so a minimumamount of headroom is required to keep the output inregulation. In addition, the input voltage required to turnon is higher than that required to run, and depends uponwhether the RUN/SS is used. As shown in Figure 2, ittakes only about 3.5VIN for the LTM8023 to run a 3.3Voutput at light load. If RUN/SS is pulled up to VIN, it takes5.5VIN to start. If the LTM8023 is enabled via the RUN/SSpin, the minimum voltage to start at light loads is lower,about 4.5V. A similar curve for 5VOUT operation is alsoprovided in Figure 2.

Soft-Start

The RUN/SS pin can be used to soft-start the LTM8023,reducing the maximum input current during start-up.

The RUN/SS pin is driven through an external RC filterto create a voltage ramp at this pin. Figure 3 shows thestart-up and shutdown waveforms with the soft-startcircuit. By choosing an appropriate RC time constant,

Figure 2. The LTM8023 Needs More Voltage to Start Than to Run

Figure 3. To Soft-Start the LTM8023, Add aResistor and Capacitor to the RUN/SS Pin

LOAD CURRENT (mA)

INPUTVOLTAGE(V)

8023 F02

LOAD CURRENT (mA)

0

INPUTVOLTAGE(V)

4.0

4.5

5.0

2000

3.5

3.0

500 1000 1500

0 2000500 1000 1500

6.0

5.5

TO START

RUN/SS ENABLED

TO RUN

TO START

RUN/SS ENABLED

TO RUN

VOUT = 3.3VTA = 25Cf = 650kHz

6.5

7.0

6.0

5.0

5.5

7.5

VOUT = 5VTA = 25Cf = 650kHz

8023 F03

IL1A/DIV

VRUN/SS2V/DIV

VOUT2V/DIV

RUN/SS

GND0.22F

RUN

15k

2ms/DIV

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LTM8023

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the peak start-up current can be reduced to the currentthat is required to regulate the output, with no overshoot.Choose the value of the resistor so that it can supply at

least 20A when the RUN/SS pin reaches 2.5V.

Synchronization

The internal oscillator of the LTM8023 can be synchronizedby applying an external 250kHz to 2MHz clock to the SYNCpin.Do not leave this pin floating. The resistor tied from theRT pin to ground should be chosen such that the LTM8023oscillates 20% lower than the intended synchronizationfrequency (see the Frequency Selection section).

The LTM8023 will not enter Burst Mode operation while

synchronized to an external clock, but will instead skippulses to maintain regulation.

Shorted Input Protection

Care needs to be taken in systems where the output willbe held high when the input to the LTM8023 is absent.This may occur in battery charging applications or inbattery backup systems where a battery or some othersupply is diode OR-ed with the LTM8023s output. If theVIN pin is allowed to float and the SHDN pin is held high(either by a logic signal or because it is tied to V IN), thenthe LTM8023s internal circuitry will pull its quiescentcurrent through its internal power switch. This is fine ifyour system can tolerate a few milliamps in this state. Ifyou ground the SHDN pin, the internal power switch cur-rent will drop to essentially zero. However, if the V IN pinis grounded while the output is held high, then parasiticdiodes inside the LTM8023 can pull large currents fromthe output through the VIN pin. Figure 4 shows a circuitthat will run only when the input voltage is present andthat protects against a shorted or reversed input.

PCB Layout

Most of the headaches associated with PCB layout havebeen alleviated or even eliminated by the high level ofintegration of the LTM8023. The LTM8023 is neverthe-less a switching power supply, and care must be taken tominimize EMI and ensure proper operation. Even with the


Figure 4. The Input Diode Prevents a Shorted Input fromDischarging a Backup Battery Tied to the Output. It Also Protectsthe Circuit from a Reversed Input. The LTM8023 Runs Only Whenthe Input is Present.

Figure 5. Layout Showing Suggested External Components, GNDPlane and Thermal Vias

high level of integration, you may fail to achieve specifiedoperation with a haphazard or poor layout. See Figure 5for a suggested layout.

Ensure that the grounding and heatsinking are acceptable.A few rules to keep in mind are:

1. Place the RADJ and RT resistors as close as possible totheir respective pins.

2. Place the CIN capacitor as close as possible to the VINand GND connection of the LTM8023.

3. Place the COUT capacitor as close as possible to the

VOUT and GND connection of the LTM8023.

VOUTVIN

RUN/SS

BIAS

RTADJ

LTM8023

8023 F04

VOUT

GND

VIN

AUX

SYNC

VOUT

CINVIN

RADJRT

COUT

GND

BIASAUX

SHARE

RUN/SS

PGOODSYNC

8023 F05

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4. Place the CIN and COUT capacitors such that theirground current flow directly adjacent or underneaththe LTM8023.

5. Connect all of the GND connections to as large a copperpour or plane area as possible on the top layer. Avoidbreaking the ground connection between the externalcomponents and the LTM8023.

6. Use vias to connect the GND copper area to the boardsinternal ground plane. Liberally distribute these GNDvias to provide both a good ground connection andthermal path to the internal planes of the printed circuitboard.

Hot-Plugging Safely

The small size, robustness and low impedance of ceramiccapacitors make them an attractive option for the inputbypass capacitor of LTM8023. However, these capacitorscan cause problems if the LTM8023 is plugged into a livesupply (see Linear Technology Application Note 88 fora complete discussion). The low loss ceramic capacitorcombined with stray inductance in series with the powersource forms an underdamped tank circuit, and the volt-age at the VIN pin of the LTM8023 can ring to twice thenominal input voltage, possibly exceeding the LTM8023srating and damaging the part. If the input supply is poorlycontrolled or the user will be plugging the LTM8023 intoan energized supply, the input network should be designedto prevent this overshoot. Figure 6 shows the waveformsthat result when an LTM8023 circuit is connected to a 24Vsupply through six feet of 24-gauge twisted pair. The firstplot is the response with a 2.2F ceramic capacitor at theinput. The input voltage rings as high as 35V and the inputcurrent peaks at 20A. One method of damping the tankcircuit is to add another capacitor with a series resistor to

the circuit. In Figure 6b an aluminum electrolytic capacitorhas been added. This capacitors high equivalent seriesresistance damps the circuit and eliminates the voltageovershoot. The extra capacitor improves low frequencyripple filtering and can slightly improve the efficiency of thecircuit, though it is likely to be the largest component in thecircuit. An alternative solution is shown in Figure 6c. A 0.7

resistor is added in series with the input to eliminate thevoltage overshoot (it also reduces the peak input current).A 0.1F capacitor improves high frequency filtering. This

solution is smaller and less expensive than the electrolyticcapacitor. For high input voltages its impact on efficiencyis minor, reducing efficiency less than one-half percent fora 5V output at full load operating from 24V.

Thermal Considerations

The LTM8023 output current may need to be derated if itis required to operate in a high ambient temperature ordeliver a large amount of continuous power. The amount ofcurrent derating is dependent upon the input voltage, out-

put power and ambient temperature. The derating curvesgiven in the Typical Performance Characteristics sectioncan be used as a guide. These curves were generated by aLTM8023 mounted to a 33cm2 4-layer FR4 printed circuitboard. Boards of other sizes and layer count can exhibitdifferent thermal behavior, so it is incumbent upon the userto verify proper operation over the intended systems line,load and environmental operating conditions.

The die temperature of the LTM8023 must be lower thanthe maximum rating of 125C, so care should be takenin the layout of the circuit to ensure good heat sinking

of the LTM8023. To estimate the junction temperature,approximate the power dissipation within the LTM8023 byapplying the typical efficiency stated in this data sheet tothe desired output power, or, if you have an actual module,by taking a power measurement. Then calculate the tem-perature rise of the LTM8023 junction above the surfaceof the printed circuit board by multiplying the modulespower dissipation by the thermal resistance. The actualthermal resistance of the LTM8023 to the printed circuitboard depends upon the layout of the circuit board, butthe thermal resistance given with the Pin Configuration,

which is based upon a 33cm2 4-layer FR4 PC board, canbe used a guide.

Finally, be aware that at high ambient temperatures theinternal Schottky diode will have significant leakage current(see Typical Performance Characteristics) increasing thequiescent current of the LTM8023.

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Figure 6. A Well Chosen Input Network Prevents Input Voltage Overshoot and Ensures ReliableOperation When the LTM8023 is Connected to a Live Supply

+LTM8023

4.7F

VIN20V/DIV

IIN10A/DIV

20s/DIV

VIN

CLOSING SWITCHSIMULATES HOT PLUG

IIN

(6a)

(6b)

LOWIMPEDANCEENERGIZED24V SUPPLY

STRAYINDUCTANCEDUE TO 6 FEET(2 METERS) OFTWISTED PAIR

+LTM8023

4.7F0.1F

0.7 VIN20V/DIV

IIN10A/DIV

20s/DIV

DANGER

RINGING VIN MAY EXCEED

ABSOLUTE MAXIMUM RATING

(6c)

+LTM8023

4.7F22F35V

AI.EI.

8023 F06

VIN20V/DIV

IIN10A/DIV

20s/DIV

+


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TYPICAL APPLICATIONS

VOUTVIN

BIAS

RUN/SS

PGOOD

RT

383k79k

100F

8023 TA03

VOUT1.8V2A

VIN*3.6V TO 15V

4.7F

LTM8023

ADJ

SYNCGND

SHARE

AUX


VOUTVIN

BIAS

SHARE

RUN/SS

PGOOD

AUX

ADJ

LTM8023

200F

8023 TA02

VOUT0.82V

2A

VIN*3.6V TO 15V

10F

RT

13M105k

SYNCGND


0.82V Step-Down Converter


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LTM8023

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VIN

RUN/SS

PGOOD

LTM8023

8023 TA05

VIN*7.5V TO 36VDC

2.2F

93.1k49.9k

RT

ADJ

SYNCGND

SHARE

VOUT

BIAS

10F

VOUT5V2A

AUX


226k61.9k

VOUTVIN

RUN/SS

PGOODBIAS3.3V

LTM8023

47F

8023 TA04

VOUT2.5V2A

VIN*4.5V TO 36VDC

2.2F

RT

ADJ

SYNCGND

SHARE AUX



5V Step-Down Converter

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LTM8023

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INPUT VOLTAGE (V)

LOADCURRENT(mA)

0

8023 TA06b

500

2500

2000

1500

1000

0 10 20 30 40


VOUTVIN

RUN/SS

RT

ADJ

LTM8023

8023 TA06

5V

SYNCGND

PGOODSHARE

BIASAUX

2.2F

93.1k39.2k

10F

VIN*7V TO 31V

*RUNNING VOLTAGE RANGE. PLEASEREFER TO APPLICATIONS INFORMATION

FOR START-UP DETAILS

5V Positive to Negative Converter 5V Positive to Negative ConverterLoad Current vs Input Voltage

VOUTVIN

RUN/SS

RT

ADJ

LTM8023

GNDSYNC

PGOODSHARE

BIAS

AUX

2.2F

76.8k49.9k

VIN*6.5V TO 36V

VOUT3.3V4A

VOUTVIN

RUN/SS

RT

ADJ

LTM8023

8023 TA08

GNDSYNC

PGOODSHARE

BIAS

AUX

2.2F 0.22F

49.9k

47F2.2k


Two LTM8023s in Parallel, 3.3V at 4A

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PACKAGE DESCRIPTION

NOTES:

1.DIMENSIONINGANDTOLERANCINGPERASMEY14.5M-1994

2.ALLDIMEN

SIONSAREINMILLIMETERS

LANDDESIGNATIONPERJESDMO-222,SPP-010ANDSPP-020

5.PRIMARYDATUM

-Z-ISSEATINGPLANE

6.THETOTAL

NUMBEROFPADS:50

43

DETAILS

OFPAD#1IDENTIFIERAREOPTIONAL,

BUTMU

STBELOCATEDWITHINTHEZONEINDICATED.

THEPAD

#1IDENTIFIERMAYBEEITHERAMOLDORA

MARKED

FEATURE

SYMBOL

aaabbb

TOLERANCE

0.15

0.10

9.00

BSC

PACKAGETOP

VIEW

LGA500507REVB

11.25

BSC

4PAD1

CORNER

3PADS

SEENOTES

X

Y

aaaZ

aaaZ

2.72

2.92

DETAILA

PACKAGES

IDEVIEW

DETAILA

SUBSTRATE

MOLD

CAP

0.270.37

2.452.55

bbbZ

Z

1.27

BSC

0.6050.665

0.6050.665

8.89

BSC

7.62

BSC

C(0.30)

PAD1

H

B

A

D

C

67 5 1234

E

F PACKAGEBOTTOMVIEW

PACKAGEINTRAYLOADINGORIENTATION

G

4.445

4.445

3.175

3.175

1.905

1.905

0.000

0.635

0.635

3.810

3.810

0.95250.635

0.3175

2.540

2.540

1.270

1.270

000

0.3175

0.3175

SUGGESTEDPCB

LAYOUT

TOPVIEW

LTMXXXXXX

MModule

TRAYP

IN1

BEVEL

LGAPackage

50-Lead(11

.25mm9.0

0mm2.8

2mm)

(Reference

LTCDWG#05-0

8-1

804RevB)

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

Table 3. Pin Assignment (Sorted by Pin Number)

PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION

A1 VOUT D5 GND

A2 VOUT D6 GND

A3 VOUT D7 GND

A4 VOUT E1 GND

A5 GND E2 GND

A6 GND E3 GND

A7 GND E4 GND

B1 VOUT E5 GND

B2 VOUT E6 GND

B3 VOUT E7 GND

B4 VOUT F5 AUX

B5 GND F6 GNDB6 GND F7 SHARE

B7 GND G1 VIN

C1 VOUT G2 VIN

C2 VOUT G3 VIN

C3 VOUT G5 BIAS

C4 VOUT G6 SYNC

C5 GND G7 RT

C6 GND H1 VIN

C7 GND H2 VIN

D1 GND H3 VIN

D2 GND H5 RUN/SS

D3 GND H6 PGOOD

D4 GND H7 ADJ

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TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

LTM4600/LTM4602 10A and 6A DC/DC Module Pin Compatible, 4.5V VIN 28V, 15mm 15mm 2.8mm LGA Package

LTM4601/LTM4603 12A and 6A DC/DC Module Pin Compatible; Remote Sensing; PLL, Tracking and Margining, 4.5V VIN 28V

LTM4604 4A, Low VIN DC/DC Module 2.375V VIN 5.5V, 0.8V VOUT 5V, 9mm 15mm 2.3mm LGA Package

LTM8020 200mA, 36V DC/DC Module 4V VIN 36V, 1.25V VOUT 5V, 6.25mm 6.25mm 2.32mm LGA Package

LTM8022 1A, 36V DC/DC Module 3.6V VIN 36V, 0.8V VOUT 10V, 11.25mm 9mm 2.82mm LGA Package

VOUTVIN

RUN/SS

RT

ADJ

LTM8023

8023 TA07

VOUT3.3V2A

SYNC

VIN*5.5V TO 36V

GND

2.2F

154k49.9k

22F

BIAS

AUX

SHARE


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