11-th2paper swaminathan shuh 1

7/31/2019 11-TH2Paper Swaminathan SHuh 1

1/17

Are Power Planes Necessaryfor High Speed Signaling ?

Suzanne L. Huh * and Madhavan Swaminathan + * Intel Corporation, Folsom, CA

+ School of Electrical and Computer Engineering Georgia Tech, Atlanta, GA

Sponsored by

High Speed SignalingChallengesInteraction between Signal and Power Distribution

Return Path DiscontinuitiesCause and EffectRole of Power and Ground Planes

Power Transmission Line for Distributing PowerConstant Current

Pseudo-BalancedConstant Voltage

Summary and Conclusions

OUTLINE


2/17

TECHNOLOGY

TREND

The performance of processor-memory interface is dictated by:1)memory speed2)channel bandwidth

Chip-to-chip communication speed

Processor with integratedmemory controller

Memory*

* http://www.apple.com/macpro/features/processor.html ; ** http://www.drdobbs.com/high-performance-computing/194500234

**Processor-memory mismatch

R e

l a t i v e p e r f o r m a n c e

CPU FrequencyDram Speeds

Chip-to-chip communication speedBus width

SYSTEM-LEVEL

ELECTRICALCHALLENGES

Signaling in a digital system

Reducing power supply noise needs to be achieved toenhance the channel speed in a modern digital system aswell as minimize Return Path Discontinuity effects

Reliably passing data through a channel that can degrade the signal


3/17

PCB power delivery network

Most popular design approach

Achieve a low-impedance path from the power supply to the die

ZPDN < Z target V (noise voltage) < Vtarget

avgI

rippleV

targetZ=

DDVavgP

avgI =

ZPDN < Ztarget V = Imax ZT < Vtarget

ZPDN( )

Freq(Hz)

ZPDN > Ztarget V = Imax ZT > Vtarget

ZT( )

DESIGN OF POWERDELIVERY NETWORK

Return current

Return PathDiscontinuity (RPD)

Cavity modesCavity modes

Signal current

Maybe new methods for PDN design are required in the future !

POWER DELIVERYNETWORK


4/17

*PTL : Power Transmission Line*

*

Transmission lines replace the power plane to convey powerreduce the layer count

remove the effect of cavity mode resonance Both the power and signal transmission lines are referenced to the

same ground planeprevent the RPD

* A. E. Engin and M. Swaminathan, Power Transmission Lines: A New Interconnect Design to EliminateSimultaneous Switching Noise, in Proc. ECTC, pp. 1139-1143, 2008

POWERTRANSMISSION LINE

Signal Current

Return Current

Closed current loop

High Impedance Power Distribution

POWERTRANSMISSION LINE

CONCEPT


5/17

Dynamic DC drop on PDN due to source termination

Vdd

Vdd

IR drop data_in=0 data_in=1Vdd

No current

DOES THE POWERTRANSMISSION LINE

CONCEPT REALLY WORK ?

S. Huh, M. Swaminathan, and D. K eezer, Constant Current Power Transmission Line based Power De livery Network for Single-EndedSignaling, IEEE Transactions on Electromagnetic Compatibility, 2011

DOES MISMATCHCREATE PROBLEMS ?

Impedance mismatch in PTL

Line congestion issue

20

Using one PTL per driver will doublethe # of lines on PCB


6/17

PRACTICAL

ISSUES ?

CaseData Pattern

IPTLDC dropover PTLdata1_tx data2_tx

1 High High I1 I1RS

2High Low

I2 I2RSLow High

3 Low Low 0 0

Varying DC Level on PDN when extended to multi-bit I/Os

IPTL

IR drop

I 1 I2

CaseData Pattern Eye Height

data1_tx data2_tx da ta1_tx da ta2_ tx

1 High High 1V 1V

2High Low 1.25V 0

Low High 0 1.25V

3 Low Low 0 0

data_in=1IR drop

data_in=0

Dummypath

IR drop

Constant Current PTL (CCPTL)*

* S. Huh, M. Sw aminathan, and D. Keezer, Constant Current Power Transmission Line based Power Delivery Network for Single-Ended Signaling, IEEE Transactions on Electromagnetic Compatibility, 2011

LETS RETHINK THE CONCEPT

CONSTANT CURRENT PTL (CCPTL)TO THE RESCUE


7/17

Constant currentthrough PTL

Constant IR dropover PTL

Constant voltageat TxPwr node

Continuouslycharged PTL

No mismatcheffect

DOES CCPTL WORK ?

1.25oz

1.0oz

Port2Port1

Signal Layer

0.012"Port4 Port3

Ground Plane

Via to power plane

Via to ground plane

2.6-long

Dummy path

Driver

Via to ground plane

2.6-long

Dummy path

Power transmission lineDriver

PTL-based test vehicle

Power-plane-based test vehicle

DOES CCPTL WORK ONLY INTHEORY ?

A SIMPLE TEST VEHICLE TOILLUSTRATE THE CONCEPT


8/17

Modeling in frequency domainConverted to Macromodel

Power-plane-based TV PTL-based TV

SPICE simulation setup

1st resonant frequency = 750MHz

1.5Gbps

Eye height improves by19.6%Jitter im roves b 58%

MODELING AND

SIMULATION

Measurement setup

Dummy path

1.5Gbps

Dummy path is implemented outside the off-the-shelf chip.AC coupling capacitor is used

to suppress the DC current flow. to provide bias for the oscilloscope.

The supply voltage of 3.47V was used for the PTL-based TV, while 2.5V was used forthe plane-based TV.

MEASUREMENTSETUP


9/17

Plane-based TV CCPTL-based TV

Signal generator output

Eye height P-P jitter

Power plane 430mV 39.1ps

CCPTL 495mV 24.9ps

Improvement 15.1% 36.3%

MEASUREMENT

RESULTS

PTL: Both RMS and P-P Jitters have relatively monotonic behavior.

Power plane: Both RMS and P-P Jitters have non-monotonic behavior,showing similarity to the insertion loss of the signal line.

RMS AND PEAK-PEAKJITTER COMPARISON


10/17

Power plane CCPTL

PRBSGenerator

clock

reset

Control SignalGenerator

Dummy Path

1

1

Pre-driverOutput buffer

Power Plane

data_in

3.109V

data_in

50

DummyPath

Z=2525

Z0=505036u/0.35u

18u/0.35u

CCPTL

CCPTL IMPLEMENTATIONUSING

CMOS 0.18UM PROCESS

MEASUREMENTCOMPARISON

200 Mbps 500 Mbps

Eye height improvement of 34%Jitter improvement of 35%


P o w e r

P l a n e

C C P T L


11/17

*Assumption: Four bits provide 16 data patterns, each of which has an e qual probability.When one output buffer draws current from the power supply, power of 1 is consumed.For the PBPTL scheme, 4b/6b encoder is used to generate the balanced data with three 1s and three 0s.

N Plane CCPTL PBPTL M

1 bit P 1 2P 1 - 2 bit

2 bit P 2 2P 2 2P 2 4 bit

4 bit P 4 2P 4 1.5P 4 6 bit

5 bit P 5 2P 5 1.4P 5 7 bit

PDN type Eyeheight

4 bit Expectation ofPower

PowerpenaltyHHHH HHHL HHLL HLLL LLLL

Power Plane V DD/2 4 3 2 1 0 2 -

CCPTL V DD/2 4 4 4 4 4 4 100%

PBPTL V DD/2 3 3 3 3 3 3 50%

Probability 0.0625 0.25 0.375 0.25 0.0625

Static power consumption

The same amount of dynamic power is consumed regardless of the PDN type.

The power consumption doubles when usingthe CCPTL regardless of the bit number. The overhead decreases with the increase of bit number when using the PBPTL scheme.

WHAT ABOUT

POWER ?

PSEUDO BALANCED

POWER TRANSMISSIONLINE (PBPTL)

6bits aretransmitted through

the interconnects

Pseudo Balanced PTL (PBPTL) *

1bit is discarded:balancing bit

5bits aretransmitted through

the interconnects

6bit balanced Data :# of 1s = 3, # of 0s = 3

4bitPRBS

Encode

PTL

Expected Advantages The coupling between the PDN and s ignal network is removed. The current through the PTL is constant at all times.

The dynamic dc drop is removed.The PTL is kept fully charged.

Pseudo-Balanced Signaling

Pseudo Balanced PTL

* S. Huh, M. Swaminathan, D. Keezer; Pseudo-Balanced Signaling Using Power Transmission Line for Parallel Links,i n Proc. IEEE EMC, 2011* S. Huh, M. Swaminathan, D. Keezer; Design of Power Delivery Networks using Power Transmission Line for Multiple I/Os using Pseudo-Balanced Signaling, in Proc. IEEE EPEPES, 2011.


12/17

CODING CONCEPT FORPBPTL

After encoding,

the number of 1s is 3 the number of 0s is 3

4-bit data information is mapped onto 2 4 balanced symbols.

Original Data Encoded Data

OR1 OR2 OR3 OR4 EN1 EN2 EN3 EN4 EN5 EN6

0 0 1 0 0 1 0 0 1 1

0 1 0 1 1 0 1 1 0 0

Constant number of 1s and 0s

Original Data Encoded Data

OR1 OR2 OR3 OR4 EN1 EN2 EN3 EN4 EN5 EN6

0 0 1 0 0 1 0 0 1 1

0 1 0 1 1 0 1 1 0 0

3I constantcurrent throughthe PTL

PBPTL SIGNALINGSCHEME


13/17

PBPTL TEST

VEHICLEPower-plane-based test vehicle

PTL-based test vehicle

Automatic test equipment is used. to feed 6-bit encoded data to drivers to supply power & ground

The output of the 4 th channel is connected the oscilloscope.

to maximize the crosstalk effect on the waveform to maintain the same ISI effect before and after encoding

MEASUREMENTSETUP


14/17

707ps

835ps

200mV

598mV

643ps

835ps

200mV775mV

620.7ps

835ps

200mV773mV

Power Plane PBPTL w/o termination PBPTL w/ termination

-9.1% -3.5% P R B S D a t a

-16.4%

691.7ps

835ps

200mV732mV

590mV

537.8ps

835ps

200mV801mV

555.7ps

835ps

200mV809mV

B a

l a n c e

d D a t a

-22.2%

-10.5%-23.9%

54 2ps

835ps

200mV795mV

539.3ps

835ps

200mV809mV

693.3ps

835ps

200mV724mV

592mV

P s e u

d o - B

a l a n c e

d D a t a

-0.5%

+0.8%

-21.8%

-3%-21.6%

MEASURED EYE

DIAGRAMS

Based on measurements, using the PBPTL schemeimproves the eye height by 34.8% on average.reduces p-p jitter by 10.5% on average.

MEASUREMENTSUMMARY


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PBPTL IMPLEMENTATIONUSING

CMOS 0.18UM PROCESS

To synchronize 6 outputsfrom the encoder

3.109V

data1_in

50

Z0=505032u/0.35u

16u/0.35u

PowerPlane

3.109V

data1_in

50

Z=25Z=25

Z0=505042u/0.35u

20u/0.35u

PBPTL

To synchronize 6 outputsfrom the encoder

Power plane PBPTL

3.109V

data1_in

50

Z0=505032u/0.35u

16u/0.35u

Power Plane

3.109V

data1_in

50

Z=25Z=25

Z0=505042u/0.35u

20u/0.35u

PBPTL

MEASUREMENTRESULTS


P o w e r

P l a n e

P B P T L

200 Mbps 500 Mbps

Eye height improvement of 35%


16/17

Power Plane

Power Transmission Line

Constant Current PTL

Pseudo Balanced PTL

To remove the RPD issue andthe cavity resonance

To remove the dynamic DCdrop and the mismatch issue

To reduce the power penalty

Constant Voltage PTL*

To reduce the power penaltyfurther

ALTERNATE

APPROACH

*S. Huh, D. Chung and M. Swaminathan; "Near Zero SSN Power Delivery Networks Using Constant VoltagePower Transmission Lines, in Proc. IEEE EDAPS, Dec. 2009

A possible solution for further reducing power: Constant-VoltagePower Transmission Line (CVPTL)

Depending on the input data, a resistor path is selected to keep theimpedance looking into the IC power supply node ( Z pwr ) constant

Rpath [0n001]

1

+-

2

data 1

V s

data 2

Rs

Rpath [0n000]

Rpath [0n010]

Rpath [1n111]

Z 0,PTL

Z 0,sig

Z 0,sig

R L

R L

Z pwr

data1_rx

data2_rx

V dd

CONSTANT-VOLTAGEPOWER

TRANSMISSION LINE(CVPTL) CONCEPT


17/17

CV-PTL & CC-PTL POWERCONSUMPTION

COMPARISON

Power Savings (%) over CC-PTL

0

5

10

15

20

25

30

35

40

0 100 200 300 400 500 600 700 800 900 1000

Number of 11s in input data

P o w e r s a v i n g s

( % ) o v e r

C C - P

T L


0

5

10

15

20

25

30

35

40

0 200 400 600 800 1000 1200

Number of 00s in input data

P o w e r s a v

i n g s

( % )


0

5

10

15

20

25

30

35

40

0 100 200 300 400 500 600Number of 01s or 10s in input data

P o w e r s a v

i n g s

( % )

Simulation of 2-bit CV-PTL and CC-PTL topologies under same conditions multiple times

SUMMARY ANDCONCLUSIONS

Power and Ground Planes induce Return Path Discontinuities (RPD) on Signal Lines

RPDs create reduced eye height and increased jitter due to cavity resonances

These can be eliminated by replacing the power plane using Power TransmissionLine (PTL)

Using Constant Current, Pseudo-balanced and Constant Voltage methods, the PTLconcept can be used to reduce power supply noise

Theory and Measurements indicate ~35% improvement in eye height and jittercompared to the use of power planes

PTL results are very promising and could help eliminate capacitors as well(not covered in this presentation)

Remember: PTL is a High Impedance Power Distribution Network(not Low Impedance)

11-th2paper swaminathan shuh 1

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