1[1][1][1].sdh basics
DESCRIPTION
SDHTRANSCRIPT
1
SDH BASICS
What is SDH? Characteristics of SDH ITU-T’s Recommendations Bit Rates Path and Section Review Questions
SDH TRANSMISSION SYSTEM
2
What is SDH?
• A New Digital Hierarchy· 155.52 Mb/s, 622.08 Mb/s, 2488.32 Mb/s, 9953.28 Mb/s,
39813.120Mb/s
· Existing PDH and future ATM signals are carried over the SDH system.
• Very basic functions are same as PDH.· Multiplex low bit rate digital signals to higher bit rate
and transmit large information efficiently.
3
What are the differences ?
Synchronous Network
Basically, all network elements work on a single clock source.
• Abundant Overhead Bits
To carry large information for Network Management.
• Unified Interface and Multiplexing Specifications
Common to all countries.
Standardized optical interfaces.
4
What are the benefits? (1) - Synchronous Network -
Simple multiplexing process Easy access to tributary signals in a multiplexed high
bit rate signal.ADD/DROP distribution
RING survivabilityCROSS CONNECT capacity management
band width managementprotection route diversity
1 40M 140M
34 M 34M
8M 8M
2M
DD F
ADD /DR O P MU X
PD HSTM -1 ST M -1
M IN I X -C O NN
2M
S D H
Simple Access to Tributaries
5
What are the benefits? (2) - Overhead Bits –
• Realization of highly advanced Network Management System for:
Fault management
Configuration management
Performance management
Security management
Accounting management
6
What are benefits SDH? (3) - Unified Interface –
• Multi-vendor Environment
• International Connection
7
What are SDH? - in conclusion –
• SDH is the infrastructure for the telecommunication network of the 21st century, providing board band and intelligent services.
8
ITU-T’s Recommendations on SDH
G.707 Network Node Interface for the SDH
G.773 Protocol Suits for Q-interface
G.774 SDH Management Information Model for the Network Element View
G.781 Synchronization layer functions
G.782 Types and General Characteristics of SDH Multiplexing Equipment
G.783 Characteristics of SDH Multiplexing Equipment Functional Blocks
G.784 SDH Management
G.803 Architecture of Transport Networks Based on the SDH
G.813 Timing characteristics of SDH equipment slave clocks(SEC)
G.842 Interworking of SDH network protection architectures
G.957 Optical Interfaces for Equipments and Systems Relating to SDH
G.958 Digital Line Systems Based on SDH for Use on Optical Fiber Cables
9
SDH Bit Rates
SDHG.707
STM: Synchronous Transport Module
CEPT North America Japan2.048 Mb/s 1.544 Mb/s 1.544 Mb/s8.448 Mb/s 6.312 Mb/s 6.312 Mb/s
34.368 Mb/s 44.376 Mb/s 32.064 Mb/s139.264 Mb/s 97.728 Mb/s
G.702PDH
STM-256 39,813.120 Mb/s
STM-0 51.840 Mb/s
STM-64 9,953.280 Mb/s
STM-16 2,488.320 Mb/s
STM-4 622.080 Mb/s
STM-1 155.520 Mb/s
10
Path and Section
MUX LT LT MUX
RegeneratorSection
Multiplex Section
Path
Regenerator RegeneratorSection Section
REG REG
VC Processing STM-N Processing
11
Review Questions
Fill up the following sentences with correct words:
A) When the SDH and PDH are compared, the ( 1 ) is an asynchronous system and the ( 2 ) is a synchronous system. The ( 3 ) conforms to the worldwide unique standard. On the other hand, there are three different ( 4 ) standards, for Europe and others, North America, and Japan.
B) The peculiarities of the SDH are that the entire network basically operates with one ( 1 ), it conforms to the ( 2 ) recommendation, and advanced ( 3 ) is easily enabled by using abundant ( 4 ).
C) The bit rate of STM-1 is ( 1 ) Mb/s, bit rate of STM-4 is ( 2 ) Mb/s, and bit rate of STM-16 is ( 3 ) Mb/s. They are ( 4 ) multiple of STM- ( 5 ).
D) The regenerator section is a section between ( 1 ) ( 2 ) or a section between a ( 3 ) and its neighbor ( 4 ).
E) The multiplex section is a section between nodes where ( 1 ) is generated and ( 2 ) .
F) The path is a connection between assembling and disassembling points of ( 1 ).
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13
MULTIPLEXING STRUCTURE, FRAME STRUCTURE AND
POINTER
Multiplexing Structure Frame Structure Pointer Review Questions
SDH TRANSMISSION SYSTEM
14
SDH Multiplexing Structure (1)
X1 AUG-64
Poi nter processi ng
Multiplexing
Aligning
Mapping
6312 kb/s
2048 kb/s
1544 kb/sC-11
C-12
C-2
34368 kb/s44736 kb/s
139264 kb/s
C-3
VC-3TU-3
TU-2
x 3
VC-2
VC-12TU-12
VC-11
x 4
TU-11
x 1
C-4
TUG-2
x 7x 7
TUG-3x 1
x 3AU-4 VC-4
VC-3AU-3
x 3
x 1
AUG-1
C-4-4c
VC-4-256cAU-4-256c
C-4-16c
C-4-64c
C-4-256c
AUG-4
X1AUG-256STM-256
STM-64
STM-16X1
STM-4X1
STM-1X1
STM-0X1
VC-4-16cAUG-16
x 4
x 4
x 4
x 4
x 1
x 1
x 1
x 1
VC-4-64cAU-4-64c
AU-4-16c
VC-4-4cAU-4-4c
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SDH Multiplexing Structure (2)
X1 AUG-64
Poi nter processi ng
Multiplexing
Aligning
Mapping
6312 kb/s
2048 kb/s
1544 kb/sC-11
C-12
C-2
34368 kb/s44736 kb/s
139264 kb/s
C-3
VC-3TU-3
TU-2
x 3
VC-2
VC-12TU-12
VC-11
x 4
TU-11
x 1
C-4
TUG-2
x 7x 7
TUG-3x 1
x 3AU-4 VC-4
VC-3AU-3
x 3
x 1
AUG-1
C-4-4c
VC-4-256cAU-4-256c
C-4-16c
C-4-64c
C-4-256c
AUG-4
X1AUG-256STM-256
STM-64
STM-16X1
STM-4X1
STM-1X1
STM-0X1
VC-4-16cAUG-16
x 4
x 4
x 4
x 4
x 1
x 1
x 1
x 1
VC-4-64cAU-4-64c
AU-4-16c
VC-4-4cAU-4-4c
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Multiplexing Process of SDHExample: 2 Mb/s to STM-4
TUG-3HO POH TUG-3TUG-3 123
C-12LO POH
S
AU-4 PTR
pointer offset valueTU-1 PTR
C-12
VC-12
TU-12
TUG-3
VC-4
AUG-1
2.048Mb/s
TU-1 PTR
TUG-2
TUG-2
PDH
SOH
AU-4 PTR
11VC-12
VC-12
1
VC-4 AU-4
AUG-4
AUG-4
STM-4
pointer offset value
2.048Mb/s
AUG-1AUG-1AUG-1AUG-1
TU-1 PTR 2TU-1 PTR 3 12VC-1213VC-121
TUG-2 7
1234
VC-4
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STM-1 Frame Structure
5
3
R-SOH: Regenerator Section OverheadM-SOH: Multiplex Section Overhead
1 2 3 5 6 7 84
( 1) ( 2) ( 9)
270 bytes
125 µs
8 bits = 1 byte
270 columns
9
rows
125 µs
( 1)
( 2)
( 9)
9 261
Payload Capacity
R-SOH
1 AU PTR
M-SOH
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Byte Interleaved Multiplex and Frame Structure STM-N STM-1 (AU-4) STM-N
N CBA N
NNNSTM-1
STM-1AU-4
AAASTM-1
BBB
CCCSTM-N
byte interleaved multiplexing
R SOH
M SOH
N
N
9 x N 261 x N
9 rows
125 µs
STM-1AU-4
AU-4
AU-4
CBA
AU PTRs
ABC NABC N
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Pointer Function
R SOH
STM-4
Example:2 Mb/s to STM-4 via AU-4
AU PTR
M SOH
VC-4(3)
VC-4(2)
VC-4(1)
VC-4 (4)
VC-12 (63)
63
2
1
2 M signal
()
VC4
POH
TU12 PTR
TU-3 PTR area
POHVC-12
POHVC-12
POHVC-12
20
AU-4 Pointer and Pointer Offset Number
N N N N S S D DD DDI I II I
10 bits
H1 H2
H1 * * H2 * * H3H3H3
782 # #
521 # #
86 # #
435 # #
696 # #
87 # #
522 # #
# same number for 3 consecutive bytes
0 0 0
VC-4
Pointer Configuration
1 1 1
21
TU-12 Pointer and Pointer Offset Numbering
105
0
35
70
139
34
69
104VC-12
TU-12
N N N N S S D DD DDI I II I
10 bits
V1 V2
V1
V2
V3
V4
35 bytes
125 µs
36 bytes
500 µs
V 1
V 2
V 3
V 4
Pointer Structure
J2
Z6
K4
V5
V5
500 µs
125 µs
20 *
*In this case, pointer offset value is set20(0000010100)
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Pointer Renewal
( )
B
( )
A
B
A
STM-1
STM-N
delay
input signal
frame aligned signal
multiplexed signal
A B
STM-1
STM-1
STM-1
delay
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AU-4 Justification (1)
N N N N S S I I II ID DD DD
H1 H2
pointer value
1
4
9
N ega tive justif ica tion opportun ity(3 bytes)
P ositive justifica tion opportun ity(3 byte )
Negative justification controlinvert five D-bits accept majority vote
Positive justification controlinvert five I-bits accept majority vote
I : Increment bitD : Decrement bitN : New data flag bit
0 0 0
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AU-4 Justification (2) - Positive Justification -
n+1n+1n n nn-1
H1 H2 H3 H3 H311Y Y
H1 H2 H3 H3 H311Y Y
start of VC-4
pointer value (n)
pointer value (I bits inverted)
positive justification start of VC-4 (new)
pointer value (n+1)
H1 H2 H3 H3 H311Y Y
H1 H2 H3 H3 H311Y Y
n+1n+1n n nn-1
n+1n+1n n nn-1
n+1n+1n n nn-1
Frame 1
Frame 2
Frame 3
Frame 4
125 µs
250 µs
375 µs
500 µs
25
AU-4 Justification (3) - Negative Justification -
n-2 n-1
n+1n+1
H1 H2 H3 H3 H311Y Y
H1 H2 H3 H3 H311Y Y
start of VC-4
pointer value (n)
pointer value (D bits inverted)
negative justification start of VC-4 (new)
pointer value (n-1)
H1 H2 11Y Y
H1 H2 H3 H3 H311Y Y
n+1n+1n n nn-1
n+1n+1n n n
n+1n+1n n nn-1
Frame 1
Frame 2
Frame 3
Frame 4
125 µs
250 µs
375 µs
500 µs
n-1
n-2 n-1 n-1n-1
n-1n-1n-2
n n nn-1n-1n-1n-2
26
Review QuestionsFill up the spaces enclosed in parentheses in the following sentences with correct words: 1. The cycle of the frame structure of STM-1 is ( a ) and composed of ( b ) bytes. (
c ) vertical matrixes and ( d ) horizontal matrixes represent the frame structure.2. An STM-4 signal has four times the rate of an STM-1 signal. The STM-4 signal has rate of (
a )Mbit/s (=( b ) x ( c )Mbit/s). There are 36 columns for section overhead plus ( d ) pointer. There are ( e ) columns or byte for an STM-4 signal.
3. Multiplexing process route via AU-( a ) is ( b ) standard and used in most countries. One AUG is equivalent one ( c ). A three of ( d ) signals is formed an AUG.
4. VC-3 or VC-4 POH starts immediately after ( a ) (if the pointer offset value is 0); but for VC12 POH, V5 is placed right after the ( b ) byte not after the ( c ).
5.. The five I bits in the (H1, H2) pointer word are inverted if the system request a ( a ) frequency justification while the five D bits used for ( b ) frequency justification. In either case, the majority vote rule is applicable to both the I and the D bits. Under a normal operation condition, the pointer value can be increased or decreased by ( c ). If the pointer value is 728, and a positive frequency justification is requested, the new pointer value will become ( d ) for the next three frames. If the pointer value is 0, and a negative frequency justification is requested, the new pointer value will become ( e ) for the next three frames.
6. The NDF of SDH pointer has a code of ( a ) for a normal operation; on the other hand, for re-starting (rebooting ) a new pointer while ignoring the existing one, NDF should be set to ( b ).
27
28
29
OVERHEAD AND MAPPING
• Overhead• Mapping• Review Questions
SDH TRANSMISSION SYSTEM
30
STM-1 Frame Structure and SOH
RSOH
MSOH
AU PTR
STM-1 PAYLOAD
261 bytes9 bytes
Section O verhead
9ro
ws
A U P o in te r(s )
R S O H
M S O H
}
}: bytes reserved for national use
A 1 A 1 A 1 A 2 A 2 A 2 J0B 1 E1 F 1D 1 D 2 D 3
B 2 B 2 B 2 K1 K 2D 4 D 5 D 6D 7 D 8 D 9
D 1 0S 1 Z 1 Z 1 Z 2 Z 2 M 1 E2
D 11 D 1 2
31
Function of SOH (1)Framing (A1, A2)Regenerator section trace (J0) regenerator section connection check Data communication channel (D1-3) regenerator section DCC, 192 kb/s
(D4-12) multiplex section DCC, 576 kb/sOrder wire (E1) accessible at regenerators
(E2) accessible at multiplexersUser channel (F1) 64 kb/s clear channelError monitoring (B1) regenerator section BIP-8
(B2) multiplexer section BIP-24NAPS signaling (K1,2) automatic protection switching
(K2) also used as MS-AIS and MS-RDISynchronization status (S1) indication of quality levelSection status reporting (M1) REI (count of BIP-24N)
RDI ; Remote Defect Indication
(formerly FERF, Far End Receive Failure)
REI ; Remote Error Indication
(formerly FEBE, Far End Block Error)
MS ; Multiplex Section
DCC ; Data Communication Channel
A 1 A 1 A 1 A 2 A 2 A 2 J 0B 1 E1 F 1D 1 D 2 D 3
B 2 B 2 B 2 K1 K 2D 4 D 5 D 6D 7 D 8 D 9
D 1 0S 1 Z 1 Z 1 Z 2 Z 2 M 1 E2
D 11 D 1 2
A U P o in te r(s )
R S O H
M S O H
}
}: bytes reserved for national use
32
Function of SOH (2)Framing (A1, A2)Regenerator section trace (J0) regenerator section connection check Data communication channel (D1-3) regenerator section DCC, 192 kb/s
(D4-12) multiplex section DCC, 576 kb/sOrder wire (E1) accessible at regenerators
(E2) accessible at multiplexersUser channel (F1) 64 kb/s clear channelError monitoring (B1) regenerator section BIP-8
(B2) multiplexer section BIP-24NAPS signaling (K1,2) automatic protection switching
(K2) also used as MS-RDISynchronization status (S1) indication of quality levelSection status reporting (M1) REI (count of BIP-24N)
RDI ; Remote Defect Indication
(formerly FERF, Far End Receive Failure)
REI ; Remote Error Indication
(formerly FEBE, Far End Block Error)
MS ; Multiplex Section
DCC ; Data Communication Channel
A1 A1 A1 A2 A2 A2 J0B1 E1 F1D1 D2 D3
B2 B2 B2 K1 K2D4 D5 D6D7 D8 D9D10S1 Z1 Z1 Z2 Z2 M1 E2
D11 D12
AU Pointer(s)
RSOH
MSOH
; bytes reserved for national use
}
}
33
Section and Path Trace Method
RSTMSTHPTLPT RST LPTHPTMSTRST
J0: Section trace
VC-4 POH (J1: Path trace)
VC-3 POH(J1: Path trace)VC-12(J2: Path trace)
Node A
RST: Regenerator Section Termination MST: Multiplex Section TerminationHPT: High Order Path Termination LPT: Lower Order Path Termination
Node -A Node -BPath Trace : Used
Transmit path trace : 123-565656
Path Trace expected value
: ABCDEGF
Received value : ABCDEFG
Path Trace : Used
Transmit path trace : ABCDEFG
Path Trace expected value
: 123-565656
Received value : 123-565656
Node B
34
Section Trace(J0)
RST
RST
Node A Node B
RST
RST
RST
RST
Node C
RST: Regenerator Section Termination
Terminated Section ofSection Trace
Terminated Section ofSection Trace
a
c
a’
c’
b
d
b’
d’
35
Principle of BIP 8
1
n
K i =even - - - - - K=0odd - - - - - K=1
B1 byte
# nBlock
# n+1Block
1121 * * *K1 * * * 81 1222 * * * K2 * * *82
1i 2i * * * Ki * * *8i
1n 2n * * * Kn * * *8n
1 2* * * **K * * * *8
36
BIP Computing Area
AU PTR
B1
B2 B2 B2
countedafter scrambling
countedbefore scrambling
BIP 8 for Regenerator Section BIP N x 24 for Multiplex Section
B1 renewed at every regenerator
B2 renewed only at multiplexer
RSOH RSOH
MSOH
AU PTR
MSOH
#n
#n+1
37
Higher-Order POH Functions (VC-3, VC-4)
Path error monitor (B3) BIP-8Path status report (G1) REI (Remote Error Indication)
count of error (BIP-8 results)RDI (Remote Defect Indication)
receiving path AIS, signal failurepath trace mismatch
Path trace (J1) verification of VC connectionuser programmable, 15 characters
Signal label (C2) indication of VC compositionunequipped, equipped-non-specific,TUG structure, locked TU, ATM,async. 34M or 45M, async. 140M,MAN (DQDB), FDDI
Path user channels (F2, F3) 64 kb/s clear channelsAPS signaling (K3) automatic protection switching at the
higher order path levelPosition indicator (H4) multiframe position for the VC-1, VC-2Network operator byte (N1) for tandem connection maintenance
REI; formerly FEBE (Far End Block Error), RDI; formerly FERF (Far End Receive Failure)
J1
B3
C2
G1
F2
H4
F3
K3
N1
VC-3 / VC-4payload
VC-3 / VC-4
38
TU-12 multiframe indication byteVC-3/VC-4POH Portion
VC-3/VC-4 Payload
(V4)
In H4(X Y), X Y represent bits 7 and 8 of H4
H4(00)9 rows
PTR(V1)
PTR(V2)
PTR(V3)
(V4)
VC-3/VC-4 PayloadH4(01)
VC-3/VC-4 PayloadH4(10)
VC-3/VC-4 PayloadH4(11)
VC-3/VC-4 PayloadH4(00)
H4 bits1 2 3 4 5 6 7 8 Frame No TimeX X 1 1 X X 0 1 0 0X X 1 1 X X 1 0 1X X 1 1 X X 1 0 2X X 1 1 X X 1 1 3 500s TU-n multiframe
X: Bit reserved for future international standardization. Its contentshall be set to “1" in the interim.
39
Path Trace (J1)
LPT
Node A Node B
Crossconnection
LPT
Node C
LPT: Lower Order Path Termination[It will change to HPT(High Order Path Termination) when VC-4 J1 is used]
Terminated Section of J1 (J2) Path Trace
a
c
b
d
40
Tandem Connection
B3 monitor B3 monitor
Compare
Error in TC
Error detection (for all VCs in a bundle)
Data link (for the first VC in the bundle)
Error count
N1 byte in VC
VC
* The Tandem Connection is applicable to a single VC or bundled VCs.
B Network (Operator Administrative area)A Network C Network
RS RS RSMS MSMS
Path
RS: Regenerator SectionMS: Multiplex Section
VC
Tandem Connection
41
Functions of POH (VC-1x, VC-2)
K4
N2
J2
V5
500µs
125µs
REI RFI RDI1 2 4 5 6 7 83
Signal LabelBIP-2
V5 byte
Path error monitor (V5) BIP-2Path status report (V5) REI (Remote Error Indication)
count of error (BIP-2 results)RFI (Remote Failure Indication)RDI (Remote Defect Indication)
receiving path AIS, signal failure
Signal label (V5) indication of VC compositionunequipped, equipped-non-specific,asynchronous, bit synchronous,byte synchronous, equipped-unused
Path access point identifier (J2) verification of VC connectionuser programmable, 15 characters
Network operator byte (N2) for tandem connection maintenanceAPS signaling (K4) automatic protection switching at the
lower order path level
REI ; former FEBE (Far End Block Error)RDI ; former FERF (Far End Receive Failure)RFI ; formerly this bit was assigned to Path Trace
VC
-1x
/V
C-2
42
Table for SAPI & API
Total 94 characters plus space
0 x x x x x x x(o)
0 x x x x x x x(k)
1 C1C2C3C4C5C6C7
0 x x x x x x x(T)
J1
J1
J1
J1
0 x x x x x x x(2)
0 x x x x x x x(1)
0 x x x x x x x(#)
J1
J1
J1
16
mu
lti-f
ram
e
125s
2ms
example : VC-4 or VC-3 case
CRC of previous 16 multiframe for J1
maximum 15 characters (ex. Tokyo-Osaka #21)
(Space) 3 F Y l
! 4 G Z m
“ 5 H [ n
# 6 I \ o
$ 7 J ] p
& 8 K ^ q
% 9 L _ (Under Bar) r
‘ (Apostrophe) : (Colon) M ! s
( ; (Semicolon) N a t
) < O b u
* = P c v
+ > Q d w
, (Comma) ? R e x
- (Hyphen) @ S f y
. (Period) A T g z
/ B U h {
0 C V i |
1 D W j }
2 E X k ~
43
End-to-End Maintenance Signal
AIS AIS
Low Order Path Section
High Order Path Section
Multiplex Section
RegeneratorSection
RegeneratorSection
LOVC HOVC LT REG LT HOVC LOVC
AIS AISAIS AIS
LOPLOPLOSLOF
LOSLOF
RDI (FERF)
RDI (FERF)
RDI (FERF)
REI (FEBE)
REI (FEBE)
REI (FEBE)
BIP-8BIP-8
BIP-24N
BIP-2
BIP-8
MUXTerminal Equipment generation detection
44
Mapping 2M Signal into VC-12
R
32 bytes
32 bytes
32 bytes
V5
RJ2
RN2
RK4
R
1 0 O O O O R R
1 0 O O O O R R
1 0 R R R R R R
32 bytes
V5R
RJ2
RN2
RK4
R
31 bytes + 7 bits
32 bytes
C1C2O O O O R R
C1 C2 O O O O R R
C1 C2 R R R R R S1
S2 I I I I I I I
32 bytes
32 bytes
* The latest recommendation deletedbit synchronous mapping.
Asynchronous Byte Synchronous
140bytes
500 µs
35 bytes125 µs
Bit Synchronous
I ; informationO ; overheadC ; justification controlS ; justification opportunityR ; fixed stuff
R
TS1 to 15
TS16
TS17 to 31
R
V5
J2
RN2
RK4
R
R
TS1 to 15
TS16
TS17 to 31
R
TS1 to 15
TS 0
TS16
TS17 to 31
R
TS1 to 15
TS16TS17 to 31
TS0
TS0
TS0
TS0
45
Mapping 34M Signal into VC-3
1
C = R R R R R R C1 C2 A B = R R R R R R R S1 S2 I I I I I I= R R R R R R R R
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x 8 I
3x 8 I
3x 8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x 8 I
3x 8 I
3x 8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
C
C
C
C
C
A B 8I
J1B3C2G1F2
H4Z3K3Z5
T1
T2
T3
125µs
3 rows
3 rows
3 rows
84 bytes
VC-3 POH
R : Fixed stu ffing bitC 1, C2 : Justi fication control bitS1, S 2 : Justi fication opportunity bitI : Information bit
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
3x8 I
46
Mapping 140M Signal into VC-4
Y Y Y Z
Y Y Y Y96 I 96 I 96 I 96 I 96 I
I ; in fo rm a tionO ; ove rheadC ; just ifica tion con tro lS ; just ifica tion opportunityR ; f ixed stuff
96 I 96 I 96 I 96 I 96 I
96 I 96 I 96 I 96 I 96 I
96 I 96 I 96 I 96 I 96 I
W X Y Y Y
Y Y Y
POH
1 12 bytes1
W = I I I I I I I IX = C R R R R R OOY = R R R R R R R RZ = I I I I I I S R
X X
X
X
J1B3C2
G1
H4F3K3N1
F2
SOH
PTR
SOH
1 byte 13 bytes
POH 20 blocks of 3 bytes
VC-4
STM-1
47
Mapping ATM Cell Into VC-4
J1
B3
C2
G1
F2
H4
F3
K3
N1
VC-4 POH
V C -4
A T M ce ll
header
53 bytes
48
VC-12 (2 Mb/s) to VC-4 (STM-1)
36
36
36
36
9
1 2 3
PTR
PTR
4
1 2 3 1 2 3 1 2
9
12 = 4 x 3
1 2 7 1 2 7 1 2 7 1 2 77
(12)(4) ~ (11)(3)(2)(1)SS
86 = 12 x 7 + 2
9POH
S S
1 2 3 1 2 3 1 2 3 1 2 31
261 = 86 x 3 + 3
AU PTR
AU PTR
SOH
SOH
PTR
PTR
3
x 3
x 7
x 3V3
V2
V1
R
125 µs
9
9
9
270 = 261 + 9
VC 12
(NPI)
NPI
125 µs
125 µs
125 µs
125 µs
125 µs500 µs
STM-1
AU-4
VC-4
TUG-3
TUG-2
TU-12
125 µs
49
Mapping of VC-12 into VC-4
50
VC-3 (34 Mb/s) to VC-4 (STM-1)
51
Scrambler
scrambled
1111111000000100 - - - -
1111111000000100 - - - -
not scrambled
Payl oadSOH
123.....
9
Payload
D Q
C S
D Q
C S
D Q
C S
D Q
C S
D Q
C S
D Q
C S
D Q
C Sclock
set = frame pulse
+
+
data
scrambleddata
+
1 1 1 1 1 1 10 1 1 1 1 1 10 0 1 1 1 1 10 0 0 1 1 1 10 0 0 0 1 1 10 0 0 0 0 1 10 0 0 0 0 0 11 0 0 0 0 0 00 1 0 0 0 0 00 0 1 0 0 0 00 0 0 1 0 0 00 0 0 0 1 0 00 0 0 0 0 1 01 0 0 0 0 0 11 1 0 0 0 0 00 1 1 0 0 0 0
. .
. .
. .
modulo 2 addition
A + B = C
1 + 1 = 0
1 + 0 = 1
0 + 1 = 1
0 + 0 = 0
scrambler output
52
2M PDH Signal Extraction from STM-1
V1
V2
V3
V4
V5
36
36
36
36
144TS
V1
V2
V3
V4
V5
9Row
3435
V5
J2
N2
K4
9Rows
9 bytes 261 bytes
H1 H2 H3AU PTR
J1
C-12
2.048Mbit/sInformation
VC-12(4Multi-frames)
35
35
35
140TS
STM-1 Frame
TU-12(4Multi-frames)
(4x9Frame)
TU-12frame in a row
9Row
9Row
* * * ** *
H1 H2 H3* * * ** * J1
J1
J1
H1 H2 H3* * * ** *
H1 H2 H3* * * ** *
9Rows
9Rows
9Rows
P T R
NPI
1
3
4
1
2
3
4
VC-4
2 6 1= 8 6 x3 + 3
9Row
(N P I)POH
S S
1 2 3 1 2 3 1 2 3 1 2 3
86 = 1 2 x7 + 2
1 2 7 1 2 7 1 2 7 1 7 1 2 7S
4
12 = 4 x3
S (1 2 )(4 ) ~ (11 )(3 )(2 )(1 )
1 2 3 1 2 3 1 2 3 1 2 3
P T R
P T R
2
TU-12(4x9 frame)
VC-12
4 bytes
TU-12
TUG-2
TUG-3
P T R
53
Contiguous & Virtual Concatenation
STM-16
STM-1
STM-1
STM-1
NE-A
STM-4
STM-4c VC-4-4c
NE-CNE-B NE-D
ContiguousConcatenation
VirtualConcatenation
STM-16
ContiguousConcatenation
AU-4#1
AU-4#2
AU-4#3
AU-4#4
AU-4-4c
AU-4#1
AU-4#2
AU-4#3
AU-4#4
AU-4#1
AU-4#2
AU-4#3
AU-4#4
AU-4-4c
54
Virtual Concatenation
• For the transport of payloads that do not fit efficiently into the standard set of virtual containers (VC-3/4/12)
• VC concatenation can be used. VC concatenation is defined for:
VC-3/4- to provide transport for payloads requiring greater capacity than one Container-3/4;
VC-12- to provide transport for payloads that require capacity greater than one Container-12.
55
Contiguous Concatenation of X VC-4s (VC-4-Xc, X=4, 16, 64, 256)
AU-4-4c PTRs
MSOH
RSOH
9X 261X
5
3
1
261X1J1B3C2
F3K3N1
G1F2H4
FixedStuff
C-4-Xc
X-1VC-4 POH
STM-N
AU-4-4 PTRs
MSOH
RSOH
9N 261N
5
3
1
1261N
VC-4 POH
STM-N
VC-4-Xc
Concatenated VC-4-XcVC-4-N
J1B3C2
F3K3N1
G1F2H4
J1B3C2
F3K3N1
G1F2H4
VC-4 POH
N
C-4-N
VC-4-N
56
AU-4 Pointer and Concatenation Indication
N N N N S S I D I D I D I D I D
H1 Y 1* 1* H2 H3 H3 H3
1 0 0 1 U U 1 1 1 1 1 1 1 1 1 1
a) Nine AU-4 pointer bytes
b) Normal AU-4 pointer
c) Concatenation indication
H1 H2
(H1, H2) = AU-4 pointer, H3= pointer action byte , Y=(100UU11)U=Unspecified, 1*=(11111111)
N = New data flag bit, S= size bit, I= increment bit, D= decrementbit, U=Unspecified
57
Virtual concatenation of X VC-3/4s(VC-3/4-Xv, X=1….256)
J1B3C2G1F2H4F3K3N1
1
9
851
VC-3#X125s
1
9
851
VC-3#1125s
J1B3C2G1F2H4F3K3N1
X1 X x 841
9
C-3-#X
125s
VC-3-Xc
J1B3C2G1F2H4F3K3N1
1
9
2611
VC-4#X125s
1
9
2611
VC-4#1125s
J1B3C2G1F2H4F3K3N1
X1 X x 2601
9
C-4-#X
125s
VC-4-Xc
a) VC-3-Xv Structure b) VC-4-Xv Structure
58
Virtual Concatenation Multiframe Structure
a) Mulltiframe indicator MFI1 Configuration(from Frame 0 to 15)
b) Mulltiframe indicator MFI2( from Frame 0 to 255)
Bit No in H4 1
MFI X
2 3 4 5 6 7 8
No used
Bit No in H4 1
MFI2(LSB)
2 3 4 5 6 7 8
MFI2(MSB)
Frame 0 0 0 0 0 0 0 0 1Frame 1 0 0 0 0 0 0 1 0Frame 2 0 0 0 0 0 0 1 1
Frame 126 0 1 1 1 1 1 1 0Frame 127 0 1 1 1 1 1 1 1Frame 128 1 0 0 0 0 0 0 0Frame 129 1 0 0 0 0 0 0 0Frame 130 1 0 0 0 0 0 0 0
Frame 254 1 1 1 1 1 1 1 0Frame 255 1 1 1 1 1 1 1 1
SequencceindiccatorSQ LSB(bit 5-8)
SequencceindiccatorSQ MSB(bit 1-4)
Frame 0 0 0 0 0Frame 1 0 0 0 1Frame 2 0 0 1 0
Frame 14 1 1 1 0Frame 15 1 1 1 1
59
VC-3/VC-4-Xv multiframe and sequence indicator
C-4/3-Xc C-4/3-Xc
PO
HP
OH
PO
HP
OH
PO
H
MFI1:0MF12_MSB:0
MFI1:1MF12_LSB:0
MFI1:15
MFI1:0MF12_MSB:0
MFI1:1MF12_LSB:1
PO
HP
OH
PO
HP
OH
PO
H
MFI1:1MF12_LSB:0
MFI1:15
MFI1:0MF12_MSB:0
MFI1:1MF12_LSB:1
MFI1:0MF12_MSB:0
SQ:0
SQ:X-1
Mu
ltifr
am
e(M
F)
1 X
60
VC-12-Xv Structure
1
2
3
4
V5
J2
N2
K4
V5
J2
N2
K4
1
2
3
4
1 35
1 35
VC-12#1
VC-12#X500s
500s
1
2
3
4
1 X X34
500s
C-12#Xc
VC-12#Xv
61
Capacity of virtually concatenated VC-12-Xv
If carried in X Capacity In steps of
VC-12-Xv VC-3 1 to 21 2176 kbit/s to 45 696 kbit/s 2176 kbit/s
VC-12-Xv VC-4 1 to 63 2176 kbit/s to 137 088 kbit/s 2176 kbit/s
VC-12-Xv Unspecified 1 to 64 2176 kbit/s to 139 264 kbit/s 2176 kbit/s
62
VC12 Extended Signal label byte coding -in K4 bit 1-
MSB LSB MFAS: Multiframe Alignment Signal0: ZeroR: Reserved bit
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MFAS0 R R R R R R R R R R R R
Extended Signal Label0 1 1 1 1 1 1 1 1 1 0
MSBb12 b13 b14 b15
LSBb16 b17 b18 b19
Hexcode
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 0
07
0 0 0 0 1 0 0 0 0 8
0 0 0 0 1 0 0 1 0 9
0 0 0 0 1 0 1 0 0 A
0 0 0 0 1 0 1 1 0 B
0 0 0 0 1 1 0 0 0 C
Interpretation
Reserved
Mapping under development
ATM mapping
Mapping of HDLC/PPP framed signal
Mapping of HDLC/LAPS framed signals
Virtually concatenated test signal, O.181specific mapping
Flexible Topology Data Link mapping0 0 0 0 1 1 0 1 0 D
1 1 1 1 1 1 1 1 F F Reserved
63
K4 bit 2 multiframe:K4 (b2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Frame countR R R R R R R R R R R R R R R R R R R R R
Sequence indicator
R: Reserved bit
64
65
66
Review QuestionsFill up the spaces enclosed in parentheses in the following sentences with correct words. 1. B1 is to monitor a ( a ) error and B2 is for monitor a ( b ) error. For STM-4, th
e monitoring method of B1 is ( c ) and the monitoring method of B2 is ( d ).2. K1 and K2 are called ( a ) signaling and used to exchange of transfer control informat
ion among nodes in an ( b ) Ring and a ( c ) – protection ( d ) system. 3. M1 is used to report a result of error detection by ( a ) , by number of ( b ) violatio
n. 4. G1 is used to report the receiving status of ( a ) back to the ( b ) side.5. H4 is used to display a ( a ) number in a multiframe required to process the TU point
er.6. ( a ) 2,048 kb/s signal is required in frequency justification between ( b ) and SDH
is necessary. ( c ) synchronous 2,048 kb/s signal is always ( d ) bit is used and ( e ) bit is not used. To indicate this status ( f ) and ( g ) are always set to 1 and 0 automatically. ( h ) synchronous 2,048 kb/s signal location of 64 kb/s channels of 2M in VC-12 is allocated
7. SDH pointers require 10 bits (5 Is and 5 Ds) of pointer value because of the maximum possible pointer offset value of AU-4 pointer is ( a )