120 mA, Current Sinking,10-Bit, I2C DAC

AD5398A

Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.

FEATURES Current sink: 120 mA 2-wire, (I2C-compatible) 1.8 V serial interface 10-bit resolution Integrated current sense resistor Power supply: 2.7 V to 5.5 V Guaranteed monotonic over all codes Power down to: 0.5 μA typical Internal reference Ultralow noise preamplifier Power-down function Power-on reset Available in 3 × 3 array WLCSP package

APPLICATIONS Consumer

Lens autofocus Image stabilization Optical zoom Shutters Iris/exposure Neutral density (ND) filters Lens covers Camera phones Digital still cameras Camera modules Digital video cameras/camcorders Camera-enabled devices Security cameras Web/PC cameras

Industrial Heater control Fan control Cooler (Peltier) control Solenoid control Valve control Linear actuator control Light control Current loop control

GENERAL DESCRIPTION

The AD5398A is a single, 10-bit digital-to-analog converter (DAC) with a current sink output capability of 120 mA. This device features an internal reference and operates from a single 2.7 V to 5.5 V supply. The DAC is controlled via a 2-wire (1.8 V, I2C®-compatible) serial interface that operates at clock rates up to 400 kHz.

The AD5398A incorporates a power-on reset circuit, which ensures the DAC output powers up to 0 V and remains there until a valid write takes place. It has a power-down feature that reduces the current consumption of the device to 0.5 μA typically.

The AD5398A is designed for autofocus, image stabilization, and optical zoom applications in camera phones, digital still cameras, and camcorders. The AD5398A is also suitable for many industrial applications, such as controlling temperature, light, and movement without derating, over temperatures ranging from −30°C to +85°C. The I2C address range for the AD5398A is 0x18 to 0x1F inclusive.

FUNCTIONAL BLOCK DIAGRAM

0779

5-00

1

POWER-ONRESET

D1SDA

AGNDDGND

VDD

SCL

PD

ISINK

VDD

RSENSE3.3Ω

I2C SERIALINTERFACE

10-BITCURRENT

OUTPUT DAC

REFERENCE

R

AD5398A

DGND Figure 1.

AD5398A

Rev. 0 | Page 2 of 16

TABLE OF CONTENTS Features .............................................................................................. 1

Consumer Applications ................................................................... 1

Industrial Applications .................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Specifications .......................................................................... 4

Timing Specifications .................................................................. 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ..............................6

Typical Performance Characteristics ..............................................7

Terminology .......................................................................................9

Theory of Operation ...................................................................... 10

Serial Interface ............................................................................ 10

I2C Bus Operation ...................................................................... 10

Data Format ................................................................................ 11

Power Supply Bypassing and Grounding ................................ 12

Applications Information .............................................................. 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

REVISION HISTORY

10/08—Revision 0: Initial Version

AD5398A

Rev. 0 | Page 3 of 16

SPECIFICATIONS VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance (RL) = 25 Ω connected to VDD; all specifications TMIN to TMAX, unless otherwise noted.

Table 1. B Version1 Parameter Min Typ Max Unit Test Conditions/Comments DC PERFORMANCE VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V

with reduced performance Resolution 10 Bits 117 μA/LSB Relative Accuracy2 ±1.5 ±4 LSB Differential Nonlinearity2, 3 ±1 LSB Guaranteed monotonic over all codes Zero Code Error2, 4

0 0.5 1 mA All 0s loaded to DAC Offset Error @ Code 162 0.5 mA Gain Error2 ±0.6 % of FSR at 25°C Offset Error Drift2, 4, 5 10 μA/°C Gain Error Drift2, 5 ±0.2 ±0.5 LSB/°C

OUTPUT CHARACTERISTICS Minimum Sink Current4 3 mA Maximum Sink Current 120 mA VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V;

specified maximum sink current may not be achieved Output Current During PD5 80 nA PD = 1 Output Compliance5 0.6 VDD V Output voltage range over which maximum 120 mA

sink current is available Output Compliance5

0.48 VDD V Output voltage range over which 90 mA sink current is available

Power-Up Time5 20 μs To 10% of FS, coming out of power-down mode; VDD = 5 V

LOGIC INPUT (PD)5

Input Current ±1 μA Input Low Voltage, VINL 0.54 V VDD = 2.7 V to 5.5 V Input High Voltage, VINH 1.26 V VDD = 2.7 V to 5.5 V Pin Capacitance 3 pF

LOGIC INPUTS (SCL, SDA)5 Input Low Voltage, VINL −0.3 +0.54 V VDD = 2.7 V to 3.6 V Input High Voltage, VINH 1.26 VDD + 0.3 V VDD = 2.7 V to 3.6 V Input Low Voltage, VINL −0.3 +0.54 V VDD = 3.6 V to 5.5 V Input High Voltage, VINH 1.4 VDD + 0.3 V VDD = 3.6 V to 5.5 V Input Leakage Current, IIN ±1 μA VIN = 0 V to VDD Input Hysteresis, VHYST 0.05 VDD V Digital Input Capacitance, CIN 6 pF Glitch Rejection6 50 ns Pulse width of spike suppressed

POWER REQUIREMENTS VDD 2.7 5.5 V IDD (Normal Mode) 0.5 1 mA IDD specification is valid for all DAC codes;

VIH = VDD, VIL = GND, VDD = 5.5 V IDD (Power-Down Mode)7 0.5 μA VIH = VDD, VIL = GND, VDD = 3 V

1 Temperature range for the B version is −30°C to +85°C. 2 See the Terminology section. 3 Linearity is tested using a reduced code range: Code 32 to Code 1023. 4 To achieve near zero output current, use the power-down feature. 5 Guaranteed by design and characterization; not production tested. PD is active high. SDA and SCL pull-up resistors are tied to 1.8 V. 6 Input filtering on both the SCL and SDA inputs suppresses noise spikes that are less than 50 ns. 7 PD is active high. When PD is taken high, the AD5389A enters power-down mode.

AD5398A

Rev. 0 | Page 4 of 16

AC SPECIFICATIONS VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, RL = 25 Ω connected to VDD, unless otherwise noted.

Table 2. B Version1, 2 Parameter Min Typ Max Unit Test Conditions/Comments Output Current Settling Time 250 μs VDD = 5 V, RL = 25 Ω, LL = 680 μH

¼ scale to ¾ scale change (0x100 to 0x300) Slew Rate 0.3 mA/μs Major Code Change Glitch Impulse 0.15 nA-sec 1 LSB change around major carry Digital Feedthrough3 0.06 nA-sec 1 Temperature range for the B version is –30°C to +85°C. 2 Guaranteed by design and characterization; not production tested. 3 See the Terminology section.

TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.

Table 3. Parameter1

B Version Unit

Description Limit at TMIN, TMAX

fSCL 400 kHz max SCL clock frequency t1 2.5 μs min SCL cycle time t2 0.6 μs min tHIGH, SCL high time t3 1.3 μs min tLOW, SCL low time t4 0.6 μs min tHD, STA, start/repeated start condition hold time t5 100 ns min tSU, DAT, data setup time t6

2 0.9 μs max tHD, DAT, data hold time 0 μs min t7 0.6 μs min tSU, STA, setup time for repeated start t8 0.6 μs min tSU, STO, stop condition setup time t9 1.3 μs min tBUF, bus free time between a stop condition and a start condition t10 300 ns max tR, rise time of both SCL and SDA when receiving 0 ns min Can be CMOS driven t11 250 ns max tF, fall time of SDA when receiving 300 ns max tF, fall time of both SCL and SDA when transmitting 20 + 0.1 Cb

3 ns min Cb 400 pF max Capacitive load for each bus line 1 Guaranteed by design and characterization; not production tested. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) to bridge the undefined region of the SCL

falling edge. 3 Cb is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD.

Timing Diagram

0779

5-00

2

SDA

t9

SCL

t3 t10 t11t4

t4 t6 t2 t5 t7 t1 t8

STARTCONDITION

REPEATEDSTART

CONDITION

STOPCONDITION

Figure 2. 2-Wire Serial Interface Timing Diagram

AD5398A

Rev. 0 | Page 5 of 16

ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.1

Table 4. Parameter Rating VDD to AGND −0.3 V to +7 V VDD to DGND −0.3 V to VDD + 0.3 V AGND to DGND −0.3 V to +0.3 V SCL, SDA to DGND −0.3 V to VDD + 0.3 V PD to DGND −0.3 V to VDD + 0.3 V ISINK to AGND −0.3 V to VDD + 0.3 V Operating Temperature Range

Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C θJA Thermal Impedance2

Mounted on 2-Layer Board 84°C/W Mounted on 4-Layer Board 48°C/W

Lead Temperature, Soldering Maximum Peak Reflow Temperature3 260°C (±5°C)

1 Transient currents of up to 100 mA do not cause SCR latch-up. 2 To achieve the optimum θJA, it is recommended that the AD5398A be

soldered onto a 4-layer board. 3 As per Jedec J-STD-020C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.

ESD CAUTION

AD5398A

Rev. 0 | Page 6 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

0779

5-02

1

A

12

VIEW FROM BALL SIDE

3

B

C

Figure 3. 9-Ball WLCSP Pin Configuration

Table 5. 9-Ball WLCSP Pin Function Description Pin Number Mnemonic Description A1 ISINK Output Current Sink. A2 NC No Connection. A3 PD Power-Down. Asynchronous power-down signal. B1 AGND Analog Ground Pin. B2 DGND Digital Ground Pin. B3 SDA I2C Interface Signal. C1 DGND Digital Ground Pin. C2 VDD Digital Supply Voltage. C3 SCL I2C Interface Signal.

0779

5-02

3

PD1

DGND2

SDA3

SCL4

ISINK8

AGND7

VDD6

DGND5

1400µm

1690µm

Figure 4. Metallization Photograph Dimensions shown in μm

Contact Factory for Latest Dimensions

AD5398A

Rev. 0 | Page 7 of 16

TYPICAL PERFORMANCE CHARACTERISTICS 2.0

–0.5

0

0.5

1.0

1.5

INL VDD = 3.8VTEMP = 25°C

1008

102395

289

684

078

472

867

261

656

050

444

839

233

628

022

416

811

2560

0779

5-00

4

CODE

INL

(LSB

)

Figure 5. Typical INL vs. Code Plot

1008

102395

289

684

078

472

867

261

656

050

444

839

233

628

022

416

811

2560

0.6

–0.3

–0.2

–0.1

0

0.1

0.2

0.3

0.4

0.5

0779

5-00

5

CODE

DN

L (L

SB)

DNL VDD = 3.8VTEMP = 25°C

Figure 6. Typical DNL vs. Code Plot

91.5

92.0

91.0

90.5

90.0

89.5

89.0

88.5

88.0300.0–6 333.1–6250.0–6200.0–6150.0–6100.0–653.5–6

0779

5-00

6

TIME

OU

TPU

T C

UR

REN

T (m

A)

Figure 7. ¼ to ¾ Scale Settling Time (VDD = 3.6 V)

0779

5-00

7

CH3 M50.0ms

VERT = 50µs/DIV

HORIZ = 468µA/DIV

3

Figure 8. Settling Time for a 4-LSB Step (VDD = 3.6 V)

0779

5-00

8

CH1 M2.0s

VERT = 2µA/DIV 4.8µA p-p

HORIZ = 2s/DIV

1

Figure 9. 0.1 Hz to 10 Hz Noise Plot (VDD = 3.6 V)

1008

102395

289

684

078

472

867

261

656

050

444

839

233

628

022

416

811

2560

0.14

0.12IOUT @ +25°C

IOUT @ +85°C

IOUT @ –40°C

0.10

0.08

0.06

0.04

0.02

0 0779

5-00

9

CODE

I OU

T (A

)

Figure 10. Sink Current vs. Code vs. Temperature (VDD = 3.6 V)

AD5398A

Rev. 0 | Page 8 of 16

2000

1800

1600

1400

1200

1000

800

600

400

200

010 100 1k 100k10k

0779

5-01

0

FREQUENCY (Hz)

AC

PSR

R (µ

A/V

)

Figure 11. AC Power Supply Rejection Ratio (VDD = 3.6 V)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

–0.5

85–40 –30 –20 –10 0 15 25 35 45 55 65 75–1.0 07

795-

011

TEMPERATURE (°C)

INL

(LSB

)

POSITIVE INL (VDD = 3.6V)

POSITIVE INL (VDD = 4.5V)POSITIVE INL (VDD = 3.8V)

NEGATIVE INL (VDD = 3.6V)

NEGATIVE INL (VDD = 4.5V)

NEGATIVE INL (VDD = 3.8V)

Figure 12. INL vs. Temperature vs. Supply Voltage

1.0

85–40 –30 –20 –10 0 15 25 35 45 55 65 75–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

0779

5-01

2

TEMPERATURE (°C)

DN

L (L

SB)

POSITIVE DNL (VDD = 3.6V)

POSITIVE DNL (VDD = 4.5V)

POSITIVE DNL (VDD = 3.8V)

NEGATIVE DNL (VDD = 3.6V)NEGATIVE DNL (VDD = 4.5V)

NEGATIVE DNL (VDD = 3.8V)

Figure 13. DNL vs. Temperature vs. Supply Voltage

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.05

0.10

85–40 –30 –20 –10 0 15 25 35 45 55 65 750 07

795-

013

TEMPERATURE (°C)

ZER

O C

OD

E ER

RO

R (m

A)

VDD = 3.6V

VDD = 3.8VVDD = 4.5V

Figure 14. Zero Code Error vs. Temperature vs. Supply Voltage

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

85–40 –30 –20 –10 0 15 25 35 45 55 65 75–2.0 07

795-

096

TEMPERATURE (°C)

FS E

RR

OR

(mA

)

VDD = 3.6V

VDD = 3.8V

VDD = 4.5V

Figure 15. Full-Scale Error vs. Temperature vs. Supply Voltage

AD5398A

Rev. 0 | Page 9 of 16

TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 5.

Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot is shown in Figure 6.

Zero-Code Error Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output is 0 mA. The zero-code error is always positive in the AD5398A because the output of the DAC cannot go below 0 mA. This is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mA.

Gain Error This is a measurement of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percent of the full-scale range.

Gain Error Drift This is a measurement of the change in gain error with changes in temperature. It is expressed in LSB/°C.

Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nA-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition.

Digital Feedthrough Digital feedthrough is a measurement of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, however is measured when the DAC output is not updated. It is specified in nA-sec and measured with a full- scale code change on the data bus, that is, from all 0s to all 1s and vice versa.

Offset Error Offset error is a measurement of the difference between ISINK

(actual) and IOUT (ideal) in the linear region of the transfer function, expressed in mA. Offset error is measured on the AD5398A with Code 16 loaded into the DAC register.

Offset Error Drift This is a measurement of the change in offset error with a change in temperature. It is expressed in μV/°C.

AD5398A

Rev. 0 | Page 10 of 16

THEORY OF OPERATION The AD5398A is a fully integrated 10-bit DAC with 120 mA output current sink capability and is intended for driving voice coil actuators in applications such as lens autofocus, image sta-bilization, and optical zoom. The circuit diagram is shown in Figure 16. A 10-bit current output DAC coupled with Resistor R generates the voltage that drives the noninverting input of the operational amplifier. This voltage also appears across the RSENSE resistor and generates the sink current required to drive the voice coil.

The R and RSENSE resistors are interleaved and matched. There-fore, the temperature coefficient and any nonlinearities over temperature are matched and the output drift over temperature is minimized. Diode D1 is an output protection diode.

0779

5-01

5

POWER-ONRESET

SDA

AGNDDGND

VDD

SCL

PD

ISINK

VDD

VBAT

VOICE COILACTUATOR

D1

RSENSE3.3Ω

I2C SERIALINTERFACE

10-BITCURRENT

OUTPUT DAC

REFERENCE

R

AD5398A

DGND Figure 16. Circuit Diagram Showing Connection to

Voice Coil

SERIAL INTERFACE The AD5398A is controlled using the industry-standard I2C 2-wire serial protocol. Data can be written to or read from the DAC at data rates up to 400 kHz. After a read operation, the contents of the input register are reset to all zeros.

I2C BUS OPERATION An I2C bus operates with one or more master devices that generate the serial clock (SCL), and read/write data on the serial data line (SDA) to/from slave devices such as the AD5398A. On all devices on an I2C bus, the SCL pin is connected to the SCL line and the SDA pin is connected to the SDA line. I2C devices can only pull the bus lines low; pulling high is achieved by the pull-up resistors, RP. The value of RP depends on the data rate, bus capacitance, and the maximum load current that the I2C device can sink (3 mA for a standard device).

0779

5-01

6

SCL

SDA

I2C MASTERDEVICE AD5398A I2C SLAVE

DEVICEI2C SLAVE

DEVICE

RPRP

VDD

Figure 17. Typical I2C Bus

When the bus is idle, SCL and SDA are both high. The master device initiates a serial bus operation by generating a start condition, which is defined as a high-to-low transition on the SDA line while SCL is high. The slave device connected to the bus responds to the start condition and shifts in the next eight data bits under the control of the serial clock. These eight data bits consist of a 7-bit address, plus a read/write bit, which is 0 if data is to be written to a device, and 1 if data is to be read from a device. Each slave device on an I2C bus must have a unique address. The address of the AD5398A is 0001100; however, 0001101, 0001110, and 0001111 address the part because the last two bits are unused/don’t care (see Figure 18 and Figure 19). Because the address plus R/W bit always equals eight bits of data, another way of looking at it is that the write address of the AD5398A is 0001 1000 (0x18) and the read address is 0001 1001 (0x19). Again, Bit 6 and Bit 7 of the address are unused, and, therefore, the write addresses can also be 0x1A, 0x1C, and 0x1E, and the read address can be 0x1B, 0x1D, and 0x1F (see and ).

Figure 18Figure 19

At the end of the address data, after the R/W bit, the slave device that recognizes its own address responds by generating an acknowledge (ACK) condition. This is defined as the slave device pulling SDA low while SCL is low before the ninth clock pulse, and keeping it low during the ninth clock pulse. Upon receiving an ACK, the master device can clock data into the AD5398A in a write operation, or it can clock it out in a read operation. Data must change either during the low period of the clock, because SDA transitions during the high period define a start condition as described previously, or during a stop condi-tion as described in the section. Data Format

I2C data is divided into blocks of eight bits, and the slave generates an ACK at the end of each block. The AD5398A requires 10 bits of data; two data-words must be written to it when a write operation occurs, or read from it when a read operation occurs. At the end of a read or write operation, the AD5398A acknowledges the second data byte. The master generates a stop condition, defined as a low-to-high transition on SDA while SCL is high, to end the transaction.

AD5398A

Rev. 0 | Page 11 of 16

DATA FORMAT Data is written to the AD5398A high byte first, MSB first, and is shifted into the 16-bit input register. After all data is shifted in, data from the input register is transferred to the DAC register.

Because the DAC requires only 10 bits of data, not all bits of the input register data are used. The MSB is reserved for an active-high, software-controlled, power-down function.

The data format is shown in Table 6. When referring to this table, note that Bit 14 is unused; Bit 13 to Bit 4 correspond to the DAC data bits, D9 to D0; and Bit 3 to Bit 0 are unused.

During a read operation, data is read in the same bit order.

0779

5-01

7

PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X0 0

SCL

SDA

START BYMASTER

ACK BYAD5398A

1 19 1

ACK BYAD5398A

ACK BYAD5398A

STOP BYMASTER

FRAME 3LEAST SIGNIFICANT

DATA BYTE

FRAME 2MOST SIGNIFICANT

DATA BYTE

FRAME 1SERIAL BUS

ADDRESS BYTE

0 1 1 X X R/W

9

Figure 18. Write Operation

0779

5-01

8

PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X0 0

SCL

SDA

START BYMASTER

ACK BYAD5398A

1 19 1

ACK BYAD5398A

ACK BYAD5398A

STOP BYMASTER

FRAME 3LEAST SIGNIFICANT

DATA BYTE

FRAME 2MOST SIGNIFICANT

DATA BYTE

FRAME 1SERIAL BUS

ADDRESS BYTE

0 1 1 X X R/W

9

Figure 19. Read Operation

Table 6. Data Format

Serial Data-Words

High Byte Low Byte Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Serial Data Bits SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Input Register R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Function1 PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

1 PD = soft power-down; X = unused/don’t care; and D7 to D0 = DAC data.

AD5398A

Rev. 0 | Page 12 of 16

POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in an application, it is beneficial to consider power supply and ground return layout on the PCB. The PCB for the AD5398A should have separate analog and digital power supply sections. Where shared AGND and DGND is necessary, the connection of grounds should be made at only one point, as close as possible to the AD5398A.

Pay special attention to the layout of the AGND return path and track it between the voice coil motor and ISINK to minimize any series resistance. Figure 20 shows the output current sink of the AD5398A and illustrates the importance of reducing the effective series impedance of AGND, and the track resistance between the motor and ISINK. The voice coil is modelled as Inductor LC and Resistor RC. The current through the voice coil is effectively a dc current that results in a voltage drop, VC, when the AD5398A is sinking current; the effect of any series inductance is minimal. The maximum voltage drop allowed across RSENSE is 400 mV, and the minimum drain to source voltage of Q1 is 200 mV. This means that the AD5398A output has a compliance voltage of 600 mV. If VDROP falls below 600 mV, the output transistor, Q1, can no longer operate properly and ISINK might not be maintained as a constant.

0779

5-01

9

AGND

VG

Q1

D1

GROUNDRESISTANCE

GROUNDINDUCTANCE

ISINK

RSENSE3.3Ω

RG

LG

VDROP

VT

VC

VBAT

RT

RCVDD

LC

TRACERESISTANCE

VOICECOIL

ACTUATOR

Figure 20. Effect of PCB Trace Resistance and Inductance

As the current increases through the voice coil, VC increases and VDROP decreases and eventually approaches the minimum specified compliance voltage of 600 mV. The ground return path is modelled by the RG and LG components. The track resis-tance between the voice coil and the AD5398A is modelled as RT. The inductive effects of LG influence RSENSE and RC equally, and because the current is maintained as a constant, it is not as critical as the purely resistive component of the ground return path.

When the maximum sink current is flowing through the motor, the resistive elements, RT and RG, may have an impact on the voltage headroom of Q1 and may, in turn, limit the maximum value of RC because of voltage compliance.

For example, if

VBAT = 3.6 V

RG = 0.5 Ω

RT = 0.5 Ω

ISINK = 120 mA

VDROP = 600 mV (the compliance voltage)

then the largest value of resistance of the voice coil, RC, is

=×+×+−

=SINK

GSINKTSINKDROPBATC I

RIRIVVR

)]()([

Ω24mA120

Ω)]0.5mA(1202mV[600V3.6=

××+−

For this reason, it is important to minimize any series impedance on both the ground return path and interconnect between the AD5398A and the motor.

The power supply of the AD5398A should be decoupled with 0.1 μF and 10 μF capacitors. These capacitors should be kept as physically close as possible, with the 0.1 μF capacitor serving as a local bypass capacitor, and therefore should be located as close as possible to the VDD pin. The 10 μF capacitor should be a tantalum bead-type; the 0.1 μF capacitor should be a ceramic type with a low effective series resistance and effective series inductance. The 0.1 μF capacitor provides a low impedance path to ground for high transient currents.

The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible.

When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is to use a multilayer board with ground and power planes, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.

AD5398

Rev. 0 | Page 13 of 16

APPLICATIONS INFORMATION The AD5398A is designed to drive both spring preloaded and nonspring linear motors used in applications such as lens autofocus, image stabilization, or optical zoom. The operating principle of the spring-preloaded motor is that the lens position is controlled by the balancing of a voice coil and a spring. Figure 21 shows the transfer curve of a typical spring preloaded linear motor for autofocus. The key points of this transfer function are displacement or stroke, which is the actual distance the lens moves in millimeters (mm), and the current through the motor in milliamps (mA).

A start current is associated with spring-preloaded linear motors, which is effectively a threshold current that must be exceeded for any displacement in the lens to occur. The start current is usually 20 mA or greater; the rated stroke or displacement is usually 0.25 mm to 0.4 mm; and the slope of the transfer curve is approxi-mately 10 μm/mA or less.

The AD5398A is designed to sink up to 120 mA, which is more than adequate for available commercial linear motors or voice coils. Another factor that makes the AD5398A the ideal solution for these applications is the monotonicity of the device, which ensures that lens positioning is repeatable for the applica-tion of a given digital word.

Figure 22 shows a typical application circuit for the AD5398A.

0779

5-02

0

0.5

0.4

0.3

0.2

0.1

010 20 30 40

STARTCURRENT

50 60 70 80 90 100 110 1200

SINK CURRENT (mA)

STR

OK

E (m

m)

Figure 21. Spring Preloaded Voice Coil Stroke vs. Sink Current

0779

5-02

2

POWER-ONRESET

D1

POWER-DOWNRESET VOICE

COILACTUATOR

RSENSE3.3Ω

VDD

I2C SERIALINTERFACE

10-BITCURRENT

OUTPUT DAC

REFERENCE

R

AD5398A

SCL

SDA

I2C MASTERDEVICE

I2C SLAVEDEVICE

I2C SLAVEDEVICE

RPRP

VDD

VDD VCC0.1µF 10µF

+0.1µF10µF

+

SDA

AGNDDGND

VDD

SCL

PD

ISINK

DGND

Figure 22. Typical Application Circuit

AD5398A

Rev. 0 | Page 14 of 16

OUTLINE DIMENSIONS

SEATINGPLANE

0.50 BSCBALL PITCH

1.5751.5151.455

1.7501.6901.630

0.280.240.20

0.350.320.29

0.650.590.53

BOTTOM VIEW(BALL SIDE UP)

TOP VIEW(BALL SIDE DOWN)

A

123

B

C

BALL 1IDENTIFIER

0913

06-B

Figure 23. 9-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-9-1) Dimensions shown in millimeters

ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD5398ABCBZ-REEL71 −30°C to +85°C 9-Ball Wafer Level Chip Scale (WLCSP) CB-9-1 1Z AD5398ABCBZ-REEL1

−30°C to +85°C 9-Ball Wafer Level Chip Scale (WLCSP) CB-9-1 1Z AD5398A-WAFER −40°C to +85°C Bare Die Wafer EVAL-AD5398AEBZ1

Evaluation Board 1 Z = RoHS Compliant Part.

AD5398A

Rev. 0 | Page 15 of 16

NOTES

AD5398A

Rev. 0 | Page 16 of 16

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07795-0-10/08(0)